JPH06176960A - Feedthrough type laminated ceramic capacitor - Google Patents

Feedthrough type laminated ceramic capacitor

Info

Publication number
JPH06176960A
JPH06176960A JP4353427A JP35342792A JPH06176960A JP H06176960 A JPH06176960 A JP H06176960A JP 4353427 A JP4353427 A JP 4353427A JP 35342792 A JP35342792 A JP 35342792A JP H06176960 A JPH06176960 A JP H06176960A
Authority
JP
Japan
Prior art keywords
internal electrode
capacitor
thickness
grounding
resonance frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4353427A
Other languages
Japanese (ja)
Inventor
Fumio Uchikoba
文男 内木場
Taku Ito
卓 伊藤
Makoto Furubayashi
眞 古林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP4353427A priority Critical patent/JPH06176960A/en
Publication of JPH06176960A publication Critical patent/JPH06176960A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To raise a resonance frequency by lowering resistance of a ground internal electrode of a capacitor by specifying the thickness of the ground internal electrode. CONSTITUTION:There are formed on a sheet a ground internal electrode 1 and a signal internal electrode 2 into a feedthrough type laminated capacitor by making use of screen printing of palladium paste. The sheets after printed are laminated at proper pressure, and are divided for each capacitor element and are thereafter sintered. Thereafter, the capacitor is yielded by forming external electrodes 4-6. The thickness of the ground internal electrode 1 is set to be 5mum or more. Further, since a resonance frequency is raised irrespective of the thickness of the ground internal electrode is increased, the thickness of the signal internal electrode 2 is made thinner than the thickness of the ground internal electrode 1. Hereby, in a feedthrough type laminated ceramic capacitor having a higher resonance frequency, it is possible to deal with the need of a higher radio frequency.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高周波用貫通形積層セ
ラミックコンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency feedthrough multilayer ceramic capacitor.

【0002】[0002]

【従来の技術および発明が解決しようとする課題】移動
体通信、衛星通信等の例を初めとして電子通信における
高周波、デジタル化は一つの傾向として定着してきてい
る。これに伴い、電子部品も高周波対応が盛んに行われ
てきた。コンデンサ素子については、かっての円盤形素
子から積層チップタイプに移行しており、これにより、
リード線が廃止された分の寄生インダクタンスの低減が
達成できるので、積層チップタイプへの移行は、高周波
対応という立場から考えると傾向に添ったものである。
すなわち、通常、コンデンサ素子の高周波側での使用限
界はこの寄生インダクタンスによって説明されることか
ら、積層チップタイプとすることは、高周波化に寄与す
ることになる。このことを以下に数式を用いて説明す
る。
2. Description of the Related Art High frequency and digitalization in electronic communication have been established as one tendency, starting with examples of mobile communication, satellite communication and the like. Along with this, electronic components have been actively used for high frequencies. Regarding the capacitor element, the former disk-shaped element has been changed to the laminated chip type.
Since the parasitic inductance can be reduced by eliminating the lead wires, the transition to the laminated chip type is in line with the trend from the viewpoint of high frequency compatibility.
That is, since the limit of use of the capacitor element on the high frequency side is usually explained by this parasitic inductance, the multilayer chip type contributes to higher frequency. This will be described below using mathematical expressions.

【0003】コンデンサのインピーダンスZは、理想的
な場合、静電容量をC、信号周波数をf、複素記号をi
として、 Z=1/2πfCi (1) で記述される。しかしながら、実際にはリード線の有
無、電極の構造素子の実装方法などに応じてコンデンサ
素子は寄生インダクタンスを有し、また、それに応じた
純抵抗成分をも有する。従って、実際にはそのインピー
ダンスZは、寄生インダクタンスをLとし、純抵抗分を
Rとした場合、 Z=2πfLi+1/2πfCi+R (2) と記述できる。この式から分かるように、信号周波数が
低周波の場合は第1項の寄与は少なく、理想に近いと考
えられるが、周波数が上昇するにつれ、第1項の寄与が
顕著になり、もはやコンデンサとしては機能せず、むし
ろインダクターとして機能する領域に達する。このイン
ピーダンスの周波数特性を(2)式に従って考えると、
低周波側では周波数の上昇に伴いインピーダンスが単調
減少を示すが、 1/f=2π(LC)1/2 (3) を満たす共振周波数でインピーダンスの最小値Rを示
し、共振周波数以上では周波数の上昇に伴い単調増加を
示す。また、位相も共振周波数を前後に−i(1−δ)
からi(1+δ):(0<δ<1)に変化する。
In the ideal case, the impedance Z of a capacitor is C for capacitance, f for signal frequency, and i for complex symbol.
As follows, Z = 1 / 2πfCi (1) However, actually, the capacitor element has a parasitic inductance depending on the presence / absence of a lead wire, a mounting method of a structural element of an electrode, and the like, and also has a pure resistance component corresponding thereto. Therefore, in actuality, when the parasitic inductance is L and the pure resistance is R, the impedance Z can be described as Z = 2πfLi + 1 / 2πfCi + R (2). As can be seen from this equation, when the signal frequency is low, the contribution of the first term is small and is considered to be close to the ideal, but as the frequency rises, the contribution of the first term becomes remarkable and the capacitor no longer functions as a capacitor. Does not work, but rather reaches the area of functioning as an inductor. Considering the frequency characteristic of this impedance according to the equation (2),
On the low frequency side, the impedance shows a monotonic decrease with increasing frequency, but at the resonance frequency that satisfies 1 / f = 2π (LC) 1/2 (3), the minimum value R of the impedance is shown. It shows a monotonic increase with the rise. Also, the phase is -i (1-δ) before and after the resonance frequency.
To i (1 + δ): (0 <δ <1).

【0004】以上議論したように、コンデンサ素子にお
いては、高周波に対する性能の指標の一つに自己共振周
波数が広く使われている。前述のように、積層チップコ
ンデンサはリード線がなく、寄生インダクタンスが円盤
形コンデンサよりも小さい特長を有し、高周波化にとっ
て優れた特性を示す。しかしながら、この場合でも寄生
インダクタンスがあり、昨今の著しい高周波化のもとで
はやはり高周波側での限界が見えてきている。つまり、
自己共振周波数を上げるためになるべく静電容量の小さ
くてすむような回路設計がその対処法となっていて、お
おかたの目安として、1GHzでは10pF以下の定数のも
のを使うようになっている。
As discussed above, in the capacitor element, the self-resonant frequency is widely used as one of the performance indicators for high frequencies. As described above, the multilayer chip capacitor has no lead wire and has the characteristic that the parasitic inductance is smaller than that of the disk type capacitor, and exhibits excellent characteristics for high frequency. However, even in this case, there is a parasitic inductance, and the limit on the high frequency side is becoming apparent under the recent remarkable increase in frequency. That is,
The solution is to design the circuit so that the capacitance is as small as possible in order to raise the self-resonant frequency, and as a rule of thumb, use a constant value of 10 pF or less at 1 GHz.

【0005】こうしたなかで、実開昭49−12736
号公報において、図1(A)の斜視図およびそのE−
E、F−F断面図である(B)、(C)に示す構造の貫
通形積層コンデンサが提案されている。この貫通形積層
コンデンサは、接地用内部電極1と信号用内部電極2と
が誘電体層3を挟んでほぼ直角に交差して1組以上積層
され、前記信号用内部電極2は誘電体層3を貫通し、相
対する2つ側面に到達して該2つの側面に形成した信号
用外部電極4、5に接続され、前記接地用内部電極1は
誘電体層3を貫通して前記2つの側面にそれぞれ隣接し
かつ相対する2つの側面に到達して該2面に形成された
接地用外部電極6に接続したものである。また、図2
は、該図1の構造をベースとして提案され、特公昭64
−10927号公報において開示されたもので、接地用
外部電極6をコンデンサの全周に形成したものである。
図1、図2に示す貫通形積層コンデンサは、従来の積層
セラミックコンデンサに比べて自己共振周波数が2倍程
度あり、高周波に用いるコンデンサとして優れている。
[0005] In such a situation, the actual exploitation Sho 49-12736
1 (A) and its E-
Proposed are through-type multilayer capacitors having the structures shown in (B) and (C) of FIGS. In this feedthrough multilayer capacitor, one or more sets of a grounding internal electrode 1 and a signal internal electrode 2 intersect at a substantially right angle with a dielectric layer 3 sandwiched therebetween, and the signal internal electrode 2 is a dielectric layer 3. Through, and reach two opposite side surfaces to be connected to the signal external electrodes 4 and 5 formed on the two side surfaces, and the grounding internal electrode 1 penetrates the dielectric layer 3 to form the two side surfaces. To the two side surfaces adjacent to and opposite to each other and connected to the grounding external electrode 6 formed on the two surfaces. Also, FIG.
Is proposed based on the structure shown in FIG.
No. 10927, the grounding external electrode 6 is formed all around the capacitor.
The feedthrough multilayer capacitor shown in FIGS. 1 and 2 has a self-resonant frequency about twice that of the conventional multilayer ceramic capacitor, and is excellent as a capacitor used for high frequencies.

【0006】本発明者は、上記した貫通形積層セラミッ
クコンデンサにおいて、コンデンサの基板に対する実装
構造によって共振周波数が著しく影響を受けることを見
いだしている。特に、コンデンサの接地用外部電極6を
基板の安定した接地回路にできるだけ近い距離で接続す
れば、100MHz以上の周波数領域では共振周波数を大
幅に上昇させうることを見いだしている。
The inventor of the present invention has found that in the above-mentioned feedthrough multilayer ceramic capacitor, the resonance frequency is significantly affected by the mounting structure of the capacitor on the substrate. In particular, it has been found that if the grounding external electrode 6 of the capacitor is connected to a stable grounding circuit of the substrate as close as possible, the resonance frequency can be greatly increased in the frequency range of 100 MHz or higher.

【0007】しかしながら、このような実装構造によっ
て共振周波数の上昇を図ることは、コンデンサやその他
の素子の実装時の配置等の制約を促すことになり、実施
上の困難を伴う場合もあるので、コンデンサ自体の構造
自体で共振周波数の上昇を図ることが好ましい。
However, increasing the resonance frequency by such a mounting structure imposes restrictions on the arrangement of capacitors and other elements during mounting, which may be difficult to implement. It is preferable to increase the resonance frequency by the structure of the capacitor itself.

【0008】このような観点から、本発明は、貫通形積
層セラミックコンデンサにおいて、コンデンサ自体の構
造を改良して共振周波数を高めたものを提供することを
目的とするものである。
From this point of view, it is an object of the present invention to provide a feedthrough type monolithic ceramic capacitor having an improved structure and improved resonance frequency.

【0009】[0009]

【課題を解決するための手段】従来の貫通形積層セラミ
ックコンデンサにおいては、内部電極はコスト等の点か
ら薄いほど良いとされており、その厚みを通常3μm前
後に設定している。しかし、本発明者の研究によると、
このような電極厚みにした場合、接地用内部電極1の抵
抗値が問題になり、接地用内部電極1による高周波化の
ためのシールド効果が期待するほど無いことを見いだし
た。そこで、本発明は、接地用内部電極の抵抗値を引き
下げるため、前記接地用内部電極の厚みを5μm以上に
したものである。なお、当該厚みの上限については特に
制限はないが、通常はデラミネーション(層剥離)防止
の観点から20μm以下にすることが好ましい。
In the conventional feedthrough type monolithic ceramic capacitor, it is said that the thinner the internal electrode is, the better in terms of cost and the like, and the thickness thereof is usually set to about 3 μm. However, according to the research of the inventor,
It has been found that when such an electrode thickness is used, the resistance value of the grounding internal electrode 1 becomes a problem, and the shielding effect for increasing the frequency by the grounding internal electrode 1 is not as expected. Therefore, in the present invention, in order to reduce the resistance value of the grounding internal electrode, the thickness of the grounding internal electrode is set to 5 μm or more. The upper limit of the thickness is not particularly limited, but normally it is preferably 20 μm or less from the viewpoint of preventing delamination (layer separation).

【0010】[0010]

【作用】前記接地用内部電極のシールド効果は、接地用
内部電極の抵抗値を低くすることにより向上し、共振周
波数を高める作用をなす。
The shield effect of the grounding inner electrode is improved by lowering the resistance value of the grounding inner electrode, and the resonance frequency is increased.

【0011】[0011]

【実施例】特性測定を行うコンデンサの作製に当たって
は、積層セラミックコンデンサの作製技術を踏襲した。
すなわち、誘電体(誘電率55のものを用いた)となる
粉体を樹脂成分溶媒とともにスラリー状とし、このスラ
リーからドクターブレード法によってグリーシートを得
た。このシートに貫通形積層コンデンサとなるように、
図3、4で示した接地用内部電極1、信号用内部電極2
をパラジュームペーストのスクリーン印刷により形成し
た。印刷後のシートを適当な圧力で積層し、素子1個ご
とに分割し、その後焼成した。シートの積層は、焼成後
の電極1、2の厚みが3μm、5μm、8μm、10μ
m、15μm、20μmになるようにパス回数を変えて
行った。その後、外部電極4〜6を形成してコンデンサ
を得た。これらのコンデンサはその外形の信号用内部電
極2の長さ方向の外形寸法(縦)を3.2mm、横を1.
6mmとし、高さを0.5mm、1mm、1.2mm、1.5mm
とした。表1はこのようにして作製して後述の特性測定
に用いたコンデンサの一覧である。表1において、形状
の欄の1は図1の構造であり、2は図2の構造である。
[Examples] In manufacturing a capacitor for measuring characteristics, a manufacturing technique of a laminated ceramic capacitor was followed.
That is, a powder to be a dielectric (having a dielectric constant of 55) was made into a slurry with a resin component solvent, and a green sheet was obtained from this slurry by a doctor blade method. To make a feedthrough multilayer capacitor on this sheet,
Grounding inner electrode 1 and signal inner electrode 2 shown in FIGS.
Was formed by screen-printing a palladium paste. The printed sheets were laminated at an appropriate pressure, divided into individual elements, and then fired. The sheets are laminated such that the thickness of the electrodes 1 and 2 after firing is 3 μm, 5 μm, 8 μm and 10 μm.
The number of passes was changed so that m, 15 μm, and 20 μm were obtained. Then, the external electrodes 4 to 6 were formed to obtain capacitors. In these capacitors, the external dimension (vertical) of the external shape of the signal internal electrode 2 in the length direction is 3.2 mm, and the horizontal dimension is 1.
6mm, height 0.5mm, 1mm, 1.2mm, 1.5mm
And Table 1 is a list of capacitors manufactured in this manner and used for the characteristic measurement described later. In Table 1, 1 in the column of shape is the structure of FIG. 1 and 2 is the structure of FIG.

【0012】これらの試料に対して、図3(A)に示す
平面図および(B)の側面図に示すように、本発明によ
るコンデンサの実装構造を採用した場合の特性測定のた
め、絶縁材でなる基板10に図4(A)に示すように、
スルーホールを設けるか、あるいは図4(B)に示すよ
うにスルーホールを設けないものを用いてコンデンサ9
を実装し、共振周波数を測定する試験を行った。この基
板10は、その表面に導体膜でなるストリップライン1
1、12を形成し、裏面には接地層13を形成し、各ス
トリップライン11、12間に試作したコンデンサ9を
搭載し、各ストリップライン11、12の端部をSMA
コネクタ14、15に接続してなるものである。
For these samples, as shown in the plan view of FIG. 3A and the side view of FIG. 3B, an insulating material was used to measure the characteristics when the capacitor mounting structure according to the present invention was adopted. As shown in FIG. 4 (A), the substrate 10 made of
A capacitor 9 is provided by providing a through hole or using one having no through hole as shown in FIG.
Was mounted and a test for measuring the resonance frequency was performed. This substrate 10 has a strip line 1 formed of a conductive film on its surface.
1 and 12, the ground layer 13 is formed on the back surface, the prototype capacitor 9 is mounted between the strip lines 11 and 12, and the end portions of the strip lines 11 and 12 are connected to the SMA.
It is connected to the connectors 14 and 15.

【0013】なお、図4(A)、(B)の実装構造につ
いてより詳しく説明すると、図4(A)の例は、基板1
0上にコンデンサ9の接地用外部電極6に対応してそれ
ぞれ接地用パターン16を形成し、基板10の裏面の接
地層13と各接地用パターン16とを、接地用外部電極
6になるべく近い2箇所(接地用外部電極6から基板1
0の面方向に3mm以内とすることが好ましい)に設けた
スルーホール17により接続し、前記各接地用パターン
16にコンデンサ9の接地用外部電極6を半田18によ
って接続したものである。また、図4(B)は、スルー
ホール17を設けず、基板10の表面の接地用パターン
16を側面導体19を介して裏面の接地層13に接続し
た例であり、従来の実装構造を踏襲した構造である。
The mounting structure shown in FIGS. 4A and 4B will be described in more detail. In the example shown in FIG.
A ground pattern 16 is formed on the surface of the capacitor 9 corresponding to the ground external electrode 6 of the capacitor 9, and the ground layer 13 on the back surface of the substrate 10 and each ground pattern 16 are as close to the ground external electrode 6 as possible. Location (grounding external electrode 6 to substrate 1
It is preferable that the distance is within 3 mm in the plane direction of 0), and the grounding external electrode 6 of the capacitor 9 is connected to each of the grounding patterns 16 by the solder 18. Further, FIG. 4B is an example in which the through hole 17 is not provided and the grounding pattern 16 on the front surface of the substrate 10 is connected to the ground layer 13 on the back surface via the side surface conductor 19, which follows the conventional mounting structure. It is a structure.

【0014】前述のように電極1、2の厚みを変え、ま
た実装構造をそれぞれ、図4(A)、(B)のように変
え、共振周波数を測定した。この測定にはマイクロ波ネ
ットワークアナライザーを用いてS21パラメーターの
減衰特性から共振周波数を求めた。表2は前記試料番号
1〜5の各試料を用いて図4(A)、(B)にそれぞれ
示した実装構造を採用した場合(図4(A)の実装構造
をA、(B)の実装構造をBで表す)の共振周波数を示
すものである。 表1 静電容量 形状 内部電極数 電極間距離 高さ寸法 試料番号 (pF) (μm) (mm) 1 120 1 4 50 0.5 2 120 2 4 50 0.5 3 560 1 20 50 1.0 4 1000 1 38 50 1.2 5 3300 1 50 15 1.5 表2 内部電極厚み(μm) 実装 共振周波数(MHz) 信号用電極 接地用電極 構造 試料1 試料2 試料3 試料4 試料5 3 3 A 4000 4000 1200 500 210 3 3 B 1980 2100 560 320 90 5 3 A 4000 4000 1200 500 210 5 3 B 1900 2000 550 310 95 10 3 A 4050 4020 1200 510 210 10 3 B 1900 1900 600 290 90 3 5 A 4000 4000 1200 500 210 3 5 B 3900 3900 1150 490 200 3 8 A 4000 4000 1200 500 210 3 8 B 4000 4000 1200 500 210 3 10 A 4050 4050 1200 510 210 3 10 B 4050 4080 1200 510 210 3 15 A 4100 4100 1200 520 220 3 15 B 4100 4100 1200 500 205 上記の試験結果から次のことが判明した。接地用内部電
極1を5μm以上にすれば、従来のように3μm程度に
したものに比較して、実装構造の如何に関わらず共振周
波数を高くすることができる。特に接地用内部電極厚み
を8μm〜10μmとした場合、もっとも良好な特性を
示した。また、内部電極の厚みを20μm以上を超える
とデラミネーション(層剥離)を生じやすくなるので、
内部電極の厚みは20μm以下にすることが好ましい。
また、信号用内部電極の厚みの如何に拘らず、接地用内
部電極の厚みを大きくすれば共振周波数を高くすること
ができるので、信号用内部電極の厚みを接地用内部電極
の厚みより薄くすることが、印刷の工程数を少なくし、
かつデラミネーションの発生を抑え、しかも原価を低減
する意味で好ましい。
As described above, the thickness of the electrodes 1 and 2 was changed, and the mounting structure was changed as shown in FIGS. 4A and 4B, and the resonance frequency was measured. For this measurement, the resonance frequency was obtained from the attenuation characteristic of the S21 parameter using a microwave network analyzer. Table 2 shows the case where the mounting structures shown in FIGS. 4 (A) and 4 (B) are used by using the samples of the sample numbers 1 to 5 (the mounting structure of FIG. The mounting structure is represented by B). Table 1 Capacitance Shape Number of internal electrodes Distance between electrodes Height dimension Sample number (pF) (μm) (mm) 1 120 1 4 50 0.5 2 120 2 2 4 50 0.5 3 560 1 20 50 50 1.0 4 1000 1 38 50 50 1.2 5 3300 1 50 15 1.5 Table 2 Internal Electrode Thickness (μm) Mounting Resonance Frequency (MHz) Signal Electrode Grounding Electrode Structure Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 3 3 A 4000 4000 1200 500 210 3 3 B 1980 2100 560 320 90 5 5 3 A 4000 4000 1200 500 210 5 5 3 B 1900 2000 550 310 95 10 3 A 4050 4020 1200 510 210 10 3 B 1900 1900 600 290 90 3 5 A 4000 4000 1200 500 210 3 5 B 3900 3900 1150 490 200 3 8 A 4000 4000 1200 500 210 3 8 B 4000 4000 1200 500 210 3 10 A 4050 4050 1200 510 210 310 3 10 B 4050 4080 1200 510 210 315 A 4100 4100 1200 520 220 3 15 B 4100 4100 1200 500 205 Above The test results revealed the following. When the grounding internal electrode 1 has a thickness of 5 μm or more, the resonance frequency can be increased regardless of the mounting structure, as compared with the conventional one having a thickness of about 3 μm. Particularly, when the thickness of the grounding internal electrode was 8 μm to 10 μm, the best characteristics were exhibited. Further, when the thickness of the internal electrode exceeds 20 μm or more, delamination (layer separation) is likely to occur,
The thickness of the internal electrodes is preferably 20 μm or less.
Further, regardless of the thickness of the signal inner electrode, the resonance frequency can be increased by increasing the thickness of the grounding inner electrode, so that the thickness of the signaling inner electrode is made thinner than that of the grounding inner electrode. Reduces the number of printing steps,
In addition, it is preferable in terms of suppressing the occurrence of delamination and reducing the cost.

【0015】また、静電容量が10000pF以上のコン
デンサは、共振周波数が100MHzよりも小さく、実施
例で示したように、接地用内部電極を厚くした場合と従
来のように厚くしない場合とで同等の特性となった。こ
のことから、本発明は、10000pF未満の静電容量、
または、100MHz以上の周波数成分の除去を行う場合
に効果的である。
Further, a capacitor having an electrostatic capacity of 10,000 pF or more has a resonance frequency lower than 100 MHz, and as shown in the embodiment, it is equivalent when the grounding internal electrode is thicker and when it is not thicker as in the conventional case. Became a characteristic of. From this, the present invention provides a capacitance of less than 10,000 pF,
Alternatively, it is effective when removing frequency components of 100 MHz or higher.

【0016】[0016]

【発明の効果】請求項1によれば、共振周波数の高い貫
通形積層セラミックコンデンサにおいて、より高い高周
波化の要求に応えることが可能となる。また、本発明に
おいては、コンデンサ自体の構造によって高周波化を達
成するため、コンデンサや他の素子の基板への実装構造
に対する制約を与えることがなく、汎用性がある。
According to the first aspect of the present invention, it is possible to meet the demand for higher frequency in the feedthrough multilayer ceramic capacitor having a high resonance frequency. Further, in the present invention, since the high frequency is achieved by the structure of the capacitor itself, there is no restriction on the mounting structure of the capacitor and other elements on the substrate, and there is versatility.

【0017】請求項2によれば、共振周波数の高めるこ
とが可能となる他、印刷法により作製する場合には工程
数を少なくし、かつデラミネーションの発生を抑え、し
かも原価を低減するという効果をあげることができる。
According to the second aspect, the resonance frequency can be increased, and in the case of manufacturing by the printing method, the number of steps is reduced, the delamination is suppressed, and the cost is reduced. Can be raised.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)は貫通形積層セラミックコンデンサの一
例を示す斜視図、(B)、(C)はそれぞれ(A)のE
−E、F−F断面図である。
FIG. 1A is a perspective view showing an example of a feedthrough multilayer ceramic capacitor, and FIGS. 1B and 1C are E of FIG.
FIG. 7E is a cross-sectional view taken along line E-F.

【図2】貫通形積層セラミックコンデンサの他の例を示
す斜視図である。
FIG. 2 is a perspective view showing another example of a through-type monolithic ceramic capacitor.

【図3】(A)、(B)はそれぞれ図1の実装構造のコ
ンデンサの特性測定に用いた基板の構成を示す平面図及
び側面図である。
3A and 3B are a plan view and a side view, respectively, showing the configuration of a substrate used for measuring the characteristics of the capacitor having the mounting structure shown in FIG.

【図4】(A)、(B)はそれぞれ本発明によるコンデ
ンサの特性試験に供した実装構造の例を示す断面図であ
る。
4 (A) and 4 (B) are cross-sectional views showing an example of a mounting structure used for a characteristic test of a capacitor according to the present invention.

【符号の説明】[Explanation of symbols]

1 接地用内部電極 2 信号用内部電極 3 誘電体層 4、5 信号用外部電極 6 接地用外部電極 9 コンデンサ 10 基板 11、12 ストリップライン 13 接地層 14、15 SMAコネクタ 16 接地用パターン 17 スルーホール 18 半田 1 Grounding Internal Electrode 2 Signal Internal Electrode 3 Dielectric Layer 4, 5 Signal External Electrode 6 Grounding External Electrode 9 Capacitor 10 Substrate 11, 12 Stripline 13 Grounding Layer 14, 15 SMA Connector 16 Grounding Pattern 17 Through Hole 18 Solder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】接地用内部電極と信号用内部電極とが誘電
体層を挟んでほぼ直角に交差して1組以上積層され、前
記信号用内部電極は誘電体層を貫通し、コンデンサの相
対する2つ側面に到達して該2つの側面に形成した信号
用外部電極に接続され、前記接地用内部電極は誘電体層
を貫通し、前記2つの側面に隣接しかつ相対する2つの
側面に到達して少なくとも該2つの側面に形成された接
地用外部電極に接続されてなる貫通形積層セラミックコ
ンデンサにおいて、前記接地用内部電極の厚みを5μm
以上にしたこと特徴とする貫通形積層セラミックコンデ
ンサ。
1. An internal electrode for grounding and an internal electrode for signals are laminated at least one pair so as to intersect at a substantially right angle with a dielectric layer sandwiched therebetween, the internal electrode for signals penetrating the dielectric layer, and a capacitor relative to each other. To the two side surfaces that are connected to the signal external electrodes formed on the two side surfaces, the ground internal electrode penetrates the dielectric layer, and is connected to the two side surfaces that are adjacent to and opposite to the two side surfaces. In the feedthrough multilayer ceramic capacitor which reaches and is connected to at least the grounding external electrodes formed on the two side surfaces, the grounding internal electrode has a thickness of 5 μm.
A through type monolithic ceramic capacitor characterized by the above.
【請求項2】前記信号用内部電極の厚みを前記接地用内
部電極の厚みより薄くしたことを特徴とする貫通形積層
セラミックコンデンサ。
2. A through-type monolithic ceramic capacitor, wherein the signal internal electrode has a thickness smaller than that of the grounding internal electrode.
JP4353427A 1992-12-10 1992-12-10 Feedthrough type laminated ceramic capacitor Pending JPH06176960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4353427A JPH06176960A (en) 1992-12-10 1992-12-10 Feedthrough type laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4353427A JPH06176960A (en) 1992-12-10 1992-12-10 Feedthrough type laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH06176960A true JPH06176960A (en) 1994-06-24

Family

ID=18430769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4353427A Pending JPH06176960A (en) 1992-12-10 1992-12-10 Feedthrough type laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH06176960A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113960357A (en) * 2021-10-27 2022-01-21 重庆大学 High-bandwidth differential voltage probe of multistage microstrip transmission line

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083234U (en) * 1983-11-14 1985-06-08 株式会社ケンウッド multilayer capacitor
JPH0115164Y2 (en) * 1981-12-11 1989-05-08
JPH0373422U (en) * 1989-11-22 1991-07-24

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0115164Y2 (en) * 1981-12-11 1989-05-08
JPS6083234U (en) * 1983-11-14 1985-06-08 株式会社ケンウッド multilayer capacitor
JPH0373422U (en) * 1989-11-22 1991-07-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113960357A (en) * 2021-10-27 2022-01-21 重庆大学 High-bandwidth differential voltage probe of multistage microstrip transmission line

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