JP3233302B2 - Feed-through multilayer ceramic capacitors - Google Patents
Feed-through multilayer ceramic capacitorsInfo
- Publication number
- JP3233302B2 JP3233302B2 JP35342992A JP35342992A JP3233302B2 JP 3233302 B2 JP3233302 B2 JP 3233302B2 JP 35342992 A JP35342992 A JP 35342992A JP 35342992 A JP35342992 A JP 35342992A JP 3233302 B2 JP3233302 B2 JP 3233302B2
- Authority
- JP
- Japan
- Prior art keywords
- internal electrode
- grounding
- capacitor
- signal
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高周波用貫通形積層セ
ラミックコンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency feedthrough multilayer ceramic capacitor.
【０００２】[0002]
【従来の技術および発明が解決しようとする課題】移動
体通信、衛星通信等の例を初めとして電子通信における
高周波、デジタル化は一つの傾向として定着してきてい
る。これに伴い、電子部品も高周波対応が盛んに行われ
てきた。コンデンサ素子については、かっての円盤形素
子から積層チップタイプに移行しており、これにより、
リード線が廃止された分の寄生インダクタンスの低減が
達成できるので、積層チップタイプへの移行は、高周波
対応という立場から考えると傾向に添ったものである。
すなわち、通常、コンデンサ素子の高周波側での使用限
界はこの寄生インダクタンスによって説明されることか
ら、積層チップタイプとすることは、高周波化に寄与す
ることになる。このことを以下に数式を用いて説明す
る。2. Description of the Related Art High frequency and digitization in electronic communication such as mobile communication and satellite communication have been established as one trend. Along with this, electronic components have been actively used for high frequencies. Regarding capacitor elements, there has been a shift from the former disc-shaped element to a multilayer chip type,
Since the reduction of the parasitic inductance due to the elimination of the lead wire can be achieved, the transition to the multilayer chip type follows the trend from the standpoint of supporting high frequencies.
That is, since the use limit of the capacitor element on the high frequency side is usually explained by the parasitic inductance, the multilayer chip type contributes to the increase in the frequency. This will be described below using mathematical expressions.
【０００３】コンデンサのインピーダンスＺは、理想的
な場合、静電容量をＣ、信号周波数をｆ、複素記号をｉ
として、 Ｚ＝１／２πｆＣｉ （１） で記述される。しかしながら、実際にはリード線の有
無、電極の構造素子の実装方法などに応じてコンデンサ
素子は寄生インダクタンスを有し、また、それに応じた
純抵抗成分をも有する。従って、実際にはそのインピー
ダンスＺは、寄生インダクタンスをＬとし、純抵抗分を
Ｒとした場合、 Ｚ＝２πｆＬｉ＋１／２πｆＣｉ＋Ｒ （２） と記述できる。この式から分かるように、信号周波数が
低周波の場合は第１項の寄与は少なく、理想に近いと考
えられるが、周波数が上昇するにつれ、第１項の寄与が
顕著になり、もはやコンデンサとしては機能せず、むし
ろインダクターとして機能する領域に達する。このイン
ピーダンスの周波数特性を（２）式に従って考えると、
低周波側では周波数の上昇に伴いインピーダンスが単調
減少を示すが、 １／ｆ＝２π（ＬＣ）1/2 （３） を満たす共振周波数でインピーダンスの最小値Ｒを示
し、共振周波数以上では周波数の上昇に伴い単調増加を
示す。また、位相も共振周波数を前後に−ｉ（１−δ）
からｉ（１＋δ）：（０＜δ＜１）に変化する。The impedance Z of a capacitor is ideal
, The capacitance is C, the signal frequency is f, and the complex symbol is i
Z =＝ πfCi (1) However, in practice,
No, depending on the mounting method of the electrode structural element, etc.
The device has a parasitic inductance, and
It also has a pure resistance component. Therefore, the impedance is actually
In the dance Z, the parasitic inductance is L and the pure resistance is
In the case of R, it can be described as Z = 2πfLi + 1 / 2πfCi + R (2) As can be seen from this equation, the signal frequency is
In the case of low frequency, the contribution of the first term is small and is considered to be close to ideal.
As the frequency increases, the contribution of the first term
Noticeable, no longer functioning as a capacitor,
Reach the area that functions as an inductor. This Inn
Considering the frequency characteristic of the impedance according to equation (2),
On the low frequency side, the impedance is monotonic as the frequency increases
1 / f = 2π (LC)1/2 (3) Indicates the minimum value R of the impedance at the resonance frequency that satisfies
However, above the resonance frequency, a monotonic increase
Show. Also, the phase is -i (1-δ) before and after the resonance frequency.
To i (1 + δ): (0 <δ <1).
【０００４】以上議論したように、コンデンサ素子にお
いては、高周波に対する性能の指標の一つに自己共振周
波数が広く使われている。前述のように、積層チップコ
ンデンサはリード線がなく、寄生インダクタンスが円盤
形コンデンサよりも小さい特長を有し、高周波化にとっ
て優れた特性を示す。しかしながら、この場合でも寄生
インダクタンスがあり、昨今の著しい高周波化のもとで
はやはり高周波側での限界が見えてきている。つまり、
自己共振周波数を上げるためになるべく静電容量の小さ
くてすむような回路設計がその対処法となっていて、お
おかたの目安として、１GHz では１０pF以下の定数のも
のを使うようになっている。As discussed above, in the capacitor element, the self-resonant frequency is widely used as one of the indexes of performance at high frequencies. As described above, a multilayer chip capacitor has no lead wire, has a smaller parasitic inductance than a disk capacitor, and has excellent characteristics for higher frequencies. However, even in this case, there is a parasitic inductance, and the limit on the high frequency side is becoming apparent under the recent remarkable increase in the frequency. That is,
To increase the self-resonant frequency, a circuit design that requires as small a capacitance as possible is a countermeasure. As a general rule, a constant of 10 pF or less at 1 GHz is used.
【０００５】こうしたなかで、実開昭４９−１２７３６
号公報において、図１（Ａ）の斜視図およびそのＥ−
Ｅ、Ｆ−Ｆ断面図である（Ｂ）、（Ｃ）に示す構造の貫
通形積層コンデンサが提案されている。この貫通形積層
コンデンサは、接地用内部電極１と信号用内部電極２と
が誘電体層３を挟んでほぼ直角に交差して１組以上積層
され、前記信号用内部電極２は誘電体層３を貫通し、相
対する２つ側面に到達して該２つの側面に形成した信号
用外部電極４、５に接続され、前記接地用内部電極１は
誘電体層３を貫通して前記２つの側面にそれぞれ隣接し
かつ相対する２つの側面に到達して該２面に形成された
接地用外部電極６に接続したものである。また、図２
は、該図１の構造をベースとして提案され、特公昭６４
−１０９２７号公報において開示されたもので、接地用
外部電極６をコンデンサの全周に形成したものである。
図１、図２に示す貫通形積層コンデンサは、従来の積層
セラミックコンデンサに比べて自己共振周波数が２倍程
度あり、高周波に用いるコンデンサとして優れている。Under these circumstances, Japanese Utility Model Laid-Open No. 49-12736
In the publication, a perspective view of FIG.
A through-type multilayer capacitor having a structure shown in (B) and (C) which is a cross-sectional view taken along lines E and FF has been proposed. In this feed-through multilayer capacitor, one or more pairs of a grounding internal electrode 1 and a signal internal electrode 2 are laminated at substantially right angles with a dielectric layer 3 interposed therebetween, and the signal internal electrode 2 is formed of a dielectric layer 3. And reaches two opposing side surfaces and is connected to signal external electrodes 4 and 5 formed on the two side surfaces, and the grounding internal electrode 1 penetrates the dielectric layer 3 and is connected to the two side surfaces. Are connected to the grounding external electrodes 6 formed on the two sides adjacent to and opposed to each other. FIG.
Has been proposed based on the structure of FIG.
This is disclosed in Japanese Patent Application Publication No. 10927, in which a grounding external electrode 6 is formed on the entire circumference of a capacitor.
The through-type multilayer capacitors shown in FIGS. 1 and 2 have a self-resonant frequency of about twice that of a conventional multilayer ceramic capacitor, and are excellent as capacitors used at high frequencies.
【０００６】本発明者は、上記した貫通形積層セラミッ
クコンデンサにおいて、コンデンサの基板に対する実装
構造によって共振周波数が著しく影響を受けることを見
いだしている。特に、コンデンサの接地用外部電極６を
基板の安定した接地回路にできるだけ近い距離で接続す
れば、１００MHz 以上の周波数領域では共振周波数を大
幅に上昇させうることを見いだしている。The present inventor has found that in the above-mentioned through-type multilayer ceramic capacitor, the resonance frequency is significantly affected by the mounting structure of the capacitor on the substrate. In particular, it has been found that if the grounding external electrode 6 of the capacitor is connected as close as possible to a stable grounding circuit on the substrate, the resonance frequency can be significantly increased in a frequency region of 100 MHz or more.
【０００７】しかしながら、このような実装構造によっ
て共振周波数の上昇を図ることは、コンデンサやその他
の素子の実装時の配置等の制約を促すことになり、実施
上の困難を伴う場合もあるので、コンデンサ自体の構造
自体で共振周波数の上昇を図ることが好ましい。However, increasing the resonance frequency by such a mounting structure imposes restrictions on the arrangement of capacitors and other elements at the time of mounting, and may cause practical difficulties. It is preferable to increase the resonance frequency by the structure of the capacitor itself.
【０００８】このような観点から、本発明は、貫通形積
層セラミックコンデンサにおいて、コンデンサ自体の構
造を改良して共振周波数を高めたものを提供することを
目的とするものである。In view of the above, an object of the present invention is to provide a through-type multilayer ceramic capacitor in which the structure of the capacitor itself is improved to increase the resonance frequency.
【０００９】[0009]
【課題を解決するための手段】本発明者の研究による
と、従来の貫通形積層セラミックコンデンサの場合、接
地用内部電極１による高周波化のためのシールド効果が
期待するほど無いことを見いだした。この理由は、接地
用内部電極によるシールド効果が充分に得られず、電磁
界成分が流出し、外部接地パターンと影響しあうものと
考えられる。そこで、本発明は、信号用内部電極と積層
方向に対向する形の接地用内部電極の他に、信号用内部
電極と対向しない形に、共振周波数を高める接地用内部
電極を付加したことを特徴とする。According to the study of the present inventor, it has been found that in the case of a conventional through-type multilayer ceramic capacitor, the shielding effect for increasing the frequency by the internal electrode 1 for grounding is not so high as expected. It is considered that the reason for this is that the shielding effect of the internal electrode for grounding is not sufficiently obtained, and the electromagnetic field component flows out and affects the external grounding pattern. Therefore, the present invention is characterized in that, in addition to the grounding internal electrode facing the signal internal electrode in the stacking direction, a grounding internal electrode that raises the resonance frequency is added so as not to face the signal internal electrode. And
【００１０】[0010]
【作用】前記接地用内部電極として、信号用内部電極と
対向しない形のものを付加したので、付加された接地用
内部電極によりシールド効果が向上し、共振周波数が高
くなる。Since the grounding internal electrode which does not face the signal internal electrode is added, the added grounding internal electrode improves the shielding effect and increases the resonance frequency.
【００１１】[0011]
【実施例】特性測定を行うコンデンサの作製に当たって
は、積層セラミックコンデンサの作製技術を踏襲した。
すなわち、誘電体となる粉体を樹脂成分溶媒とともにス
ラリー状とし、このスラリーからドクターブレード法に
よってグリーシートを得た。このシートに貫通形積層コ
ンデンサとなるように、接地用内部電極１、信号用内部
電極２を、図３について後述するように、本発明による
構造と、従来構造とについて種々の形にパラジュームペ
ーストのスクリーン印刷により形成した。印刷後のシー
トを適当な圧力で積層し、素子１個ごとに分割し、その
後焼成した。その後、外部電極４〜６を形成してコンデ
ンサを得た。DESCRIPTION OF THE PREFERRED EMBODIMENTS In manufacturing a capacitor for measuring characteristics, the manufacturing technology of a multilayer ceramic capacitor was followed.
That is, a powder to be a dielectric was made into a slurry together with a solvent for a resin component, and a grease sheet was obtained from the slurry by a doctor blade method. The inner electrode 1 for grounding and the inner electrode 2 for signal are formed on the sheet by using a palladium paste in various shapes for the structure according to the present invention and the conventional structure as described later with reference to FIG. Formed by screen printing. The printed sheets were laminated under an appropriate pressure, divided into individual elements, and then fired. Thereafter, external electrodes 4 to 6 were formed to obtain a capacitor.
【００１２】図３（イ）は従来の信号用内部電極２の構
造を示す平面図であり、また、このような信号用内部電
極２を用いて構成したコンデンサの断面構造は図１
（Ｂ）、（Ｃ）で示したとおりである。また、図３
（ロ）、（ハ）は本発明による電極構造を示すもので、
（ニ）、（ホ）はそれぞれ（ロ）、（ハ）の電極構造を
採用したコンデンサの断面図である。図３（ロ）または
（ハ）に示すように、本発明においては、接地用内部電
極として、信号用内部電極２に積層方向に対向する接地
用内部電極１以外に、信号用内部電極２と対向しない形
に、共振周波数を上げるための接地用内部電極１ａを付
加したものである。図３（ロ）、（ニ）の例は信号用内
部電極２の片側でかつ該電極２の形成層と同一面に接地
用内部電極１ａを形成した例であり、（ハ）、（ホ）の
例は両側に形成した例である。FIG. 3A is a plan view showing the structure of the conventional signal internal electrode 2. FIG. 1 is a sectional view of a capacitor formed using such a signal internal electrode 2. As shown in FIG.
(B) and (C). FIG.
(B) and (c) show the electrode structure according to the present invention,
(D) and (e) are cross-sectional views of the capacitor employing the electrode structures (b) and (c), respectively. As shown in FIG. 3 (b) or (c), in the present invention, in addition to the grounding internal electrode 1 opposing the signal internal electrode 2 in the laminating direction, the signal internal electrode 2 is used as the grounding internal electrode. In this embodiment, a grounding internal electrode 1a for increasing a resonance frequency is added to a shape not facing the ground. FIGS. 3B and 3D are examples in which the grounding internal electrode 1a is formed on one side of the signal internal electrode 2 and on the same surface as the layer on which the electrode 2 is formed. Are examples formed on both sides.
【００１３】試作したコンデンサの外形寸法は、信号用
内部電極２の長手方向の寸法（縦幅Ｌ）を３．２mm、横
幅Ｗを１．６mmとし、高さは内部電極数に応じて表１に
示すように０．５mm、１mm、１．２mm、１．５mmと変化
させた。また、信号用内部電極２の幅ａを５００μｍ、
同層の接地用内部電極１ａと信号用内部電極２との間隔
ｂを１００μｍ、各内部電極１、１ａ、２の厚みを３μ
ｍとした。The external dimensions of the prototyped capacitor were as follows: the longitudinal dimension (longitudinal width L) of the signal internal electrode 2 was 3.2 mm, the horizontal width W was 1.6 mm, and the height was determined according to the number of internal electrodes. As shown in the figure, the thickness was changed to 0.5 mm, 1 mm, 1.2 mm, and 1.5 mm. The width a of the signal internal electrode 2 is 500 μm,
The distance b between the grounding internal electrode 1a and the signal internal electrode 2 in the same layer is 100 μm, and the thickness of each of the internal electrodes 1, 1a, 2 is 3 μm.
m.
【００１４】試作したコンデンサの特性測定は、図４
（Ａ）の平面図および（Ｂ）の側面図に示すように、絶
縁材でなる基板１０に図５（Ａ）に示すように、スルー
ホールを設けるか、あるいは図５（Ｂ）に示すようにス
ルーホールを設けないものを用いてコンデンサ９を実装
し、共振周波数を測定することにより行った。この基板
１０は、その表面に導体膜でなるストリップライン１
１、１２を形成し、裏面には接地層１３を形成し、各ス
トリップライン１１、１２間に試作したコンデンサ９を
搭載し、各ストリップライン１１、１２の端部をＳＭＡ
コネクタ１４、１５に接続してなるものである。The characteristics of the prototype capacitor were measured as shown in FIG.
As shown in the plan view of FIG. 5A and the side view of FIG. 5B, a through hole is provided in the substrate 10 made of an insulating material as shown in FIG. 5A, or as shown in FIG. This was performed by mounting the capacitor 9 using no through hole and measuring the resonance frequency. This substrate 10 has a strip line 1 made of a conductive film on its surface.
1 and 12 are formed, a ground layer 13 is formed on the back surface, and a capacitor 9 prototyped between the strip lines 11 and 12 is mounted. An end of each of the strip lines 11 and 12 is SMA.
These are connected to connectors 14 and 15.
【００１５】なお、図５（Ａ）、（Ｂ）の実装構造につ
いてより詳しく説明すると、図５（Ａ）の例は、基板１
０上にコンデンサ９の接地用外部電極６に対応してそれ
ぞれ接地用パターン１６を形成し、基板１０の裏面の接
地層１３と各接地用パターン１６とを、接地用外部電極
６になるべく近い２箇所（接地用外部電極６から基板１
０の面方向に３mm以内とすることが好ましい）に設けた
スルーホール１７により接続し、前記各接地用パターン
１６にコンデンサ９の接地用外部電極６を半田１８によ
って接続したものである。また、図５（Ｂ）は、スルー
ホール１７を設けず、基板１０の表面の接地用パターン
１６を側面導体１９を介して裏面の接地層１３に接続し
た例であり、従来の実装構造を踏襲した構造である。The mounting structure shown in FIGS. 5A and 5B will be described in more detail. The example shown in FIG.
A grounding pattern 16 is formed on each of the capacitors 9 so as to correspond to the grounding external electrodes 6 of the capacitor 9. Location (from grounding external electrode 6 to substrate 1
(Preferably within 3 mm in the direction of the plane 0)), and the grounding external electrode 6 of the capacitor 9 is connected to each of the grounding patterns 16 by solder 18. FIG. 5B is an example in which the grounding pattern 16 on the front surface of the substrate 10 is connected to the ground layer 13 on the rear surface via the side conductor 19 without providing the through-hole 17, and follows the conventional mounting structure. It is the structure which did.
【００１６】表１に示すように、内部電極数、電極間
隔、外部電極構造等を変え、また前述のように接地用内
部電極１ａを付加したものと付加しないものを構成し、
さらに実装構造をそれぞれ図５（Ａ）、（Ｂ）のように
変えたものについて、共振周波数を測定した。この測定
にはマイクロ波ネットワークアナライザーを用いてＳ２
１パラメーターの減衰特性から共振周波数を求めた。表
１において、外部接地電極形状の欄の図１は側面２面に
接地用外部電極６を形成した構造であり、図２は全周に
形成した構造である。また、表２−１〜表２−５はそれ
ぞれ表１に示した試料番号１〜５に示した構造のものに
おいて、内部電極構造が図３（イ）、（ロ）、（ハ）に
ついて、さらにこれらについてそれぞれ実装構造を図５
（Ａ）、（Ｂ）のように構成した場合について、共振周
波数を示すもので、表中のイ、ロ、ハは図３（イ）、
（ロ）、（ハ）の内部電極構造のものを示し、また、
Ａ、Ｂはそれぞれ図５（Ａ）、（Ｂ）の実装構造のもの
を示す。As shown in Table 1, the number of internal electrodes, the electrode spacing, the external electrode structure, etc. were changed, and those with and without the addition of the grounding internal electrode 1a as described above were constructed.
Further, the resonance frequency was measured for the mounting structure that was changed as shown in FIGS. 5A and 5B. This measurement was performed using a microwave network analyzer at S2.
The resonance frequency was determined from one parameter of the attenuation characteristic. In Table 1, in the column of the shape of the external ground electrode, FIG. 1 shows a structure in which ground external electrodes 6 are formed on two side surfaces, and FIG. In Tables 2-1 to 2-5, the internal electrode structures shown in FIGS. 3A, 3B, and 3C in the structures shown in Sample Nos. 1 to 5 shown in Table 1, respectively. Furthermore, the mounting structure of each of them is shown in FIG.
3A shows resonance frequencies in the case of the configuration as shown in FIGS. 3A and 3B.
(B) and (c) showing the internal electrode structure.
A and B show the mounting structures of FIGS. 5A and 5B, respectively.
【００１７】 表１（実施例に用いた積層コンデンサ） 静電容量 接地用外部 内部 電極間距離 高さ寸法 試料番号 （pF） 電極形状 電極数 （μｍ） （ｍｍ） １ １２０ 図１ ４ ５０ ０．５ ２ １２０ 図２ ４ ５０ ０．５ ３ ５６０ 図１ ２０ ５０ １．０ ４ １０００ 図１ ３８ ５０ １．２ ５ ３３００ 図１ ５０ １５ １．５ 表2-1 （試料番号１） 表2-2 （試料番号２） 表2-3 （試料番号３） 電極 実装 共振周波 電極 実装 共振周波 電極 実装 共振周波 構造 構造 数(MHz) 構造 構造 数(MHz) 構造 構造 数(MHz) イ Ａ 4000 イ Ａ 4000 イ Ａ 1200 イ Ｂ 1980 イ Ｂ 1980 イ Ｂ 560 ロ Ａ 4000 ロ Ａ 4050 ロ Ａ 1200 ロ Ｂ 3700 ロ Ｂ 3700 ロ Ｂ 1000 ハ Ａ 4150 ハ Ａ 4150 ハ Ａ 1260 ハ Ｂ 4100 ハ Ｂ 4100 ハ Ｂ 1200 表2-4 （試料番号４） 表2-5 （試料番号５） 電極 実装 共振周波 電極 実装 共振周波 構造 構造 数(MHz) 構造 構造 数(MHz) イ Ａ 500 イ Ａ 210 イ Ｂ 320 イ Ｂ 90 ロ Ａ 500 ロ Ａ 210 ロ Ｂ 480 ロ Ｂ 180 ハ Ａ 510 ハ Ａ 210 ハ Ｂ 510 ハ Ｂ 210 上記の試験結果から次のことが判明した。信号用内部電
極２と同層に接地用内部電極１ａを設ければ、実装構造
の如何に関わらず、共振周波数を高くすることができ
る。特に図５（Ｂ）に示したような従来構造にこの接地
用内部電極１ａを付加すれば、共振周波数上昇効果が顕
著である。また、接地用内部電極１ａを信号用内部電極
２の両側に設ければその効果が助長される。Table 1 (Multilayer capacitor used in the examples) Capacitance Grounding external Internal Distance between electrodes Height dimensions Sample number (pF) Electrode shape Number of electrodes (μm) (mm) 1 120 1450 FIG. 5 2 120 FIG. 2 4 50 0.5 3 560 FIG. 1 20 50 1.0 4 1000 FIG. 1 38 50 1.2 5 3300 FIG. 1 50 15 1.5 Table 2-1 (Sample No. 1) Table 2-2 (Sample No. 2) Table 2-3 (Sample No. 3) Electrode mounting Resonance frequency Electrode mounting Resonance frequency electrode Mounting Resonance frequency Structure Number of structures (MHz) Structure Number of structures (MHz) Structure Number of structures (MHz) A A4000 A A4000 A A 1200 B B 1980 B B 1980 B 560 B A 4000 B A 4050 B A 1200 B 3700 B B 3700 B B 1000 B A 4150 C A 4150 C A 1260 C B 4100 C B 4100 C B 1200 Table 2 -4 (Sample No. 4) Table 2-5 (Sample No. 5) Electrode Mounting Resonance Frequency Electrode Actual Resonance frequency structure Number of structures (MHz) Structure Number of structures (MHz) A A500 B A210 B B320 B B90 B A500 B A210 B B480 B B 180 C A 510 C A 210 C B 510 C B 210 The following was found from the above test results. If the grounding internal electrode 1a is provided on the same layer as the signal internal electrode 2, the resonance frequency can be increased regardless of the mounting structure. In particular, if this grounding internal electrode 1a is added to the conventional structure as shown in FIG. 5B, the effect of increasing the resonance frequency is remarkable. If the grounding internal electrodes 1a are provided on both sides of the signal internal electrode 2, the effect is promoted.
【００１８】また、静電容量が１００００pF以上のコン
デンサは、共振周波数が１００MHzよりも小さく、接地
用内部電極１ａを設けた場合と設けない場合とで同等の
特性となった。このことから、本発明は、１００００pF
未満の静電容量、または、１００MHz以上の周波数成分
の除去を行う場合に効果的である。The capacitor having a capacitance of 10,000 pF or more has a resonance frequency smaller than 100 MHz, and has the same characteristics when the internal electrode 1a for grounding is provided and when it is not provided. Based on this, the present invention provides 10,000 pF
This is effective when removing a capacitance less than or less than 100 MHz or more.
【００１９】また、本発明において、前記接地用内部電
極１ａは必ずしも信号用内部電極２と同層に設ける必要
はないが、印刷工程数を少なくする上では同層に形成す
ることが好ましい。In the present invention, the grounding internal electrode 1a is not necessarily provided in the same layer as the signal internal electrode 2, but is preferably formed in the same layer in order to reduce the number of printing steps.
【００２０】[0020]
【発明の効果】請求項１によれば、共振周波数の高い貫
通形積層セラミックコンデンサにおいて、より高い高周
波化の要求に応えることが可能となる。また、本発明に
おいては、コンデンサ自体の構造によって高周波化を達
成するため、コンデンサや他の素子の基板への実装構造
に対する制約を与えることがなく、汎用性がある。According to the first aspect of the present invention, it is possible to meet the demand for a higher frequency in a through-type multilayer ceramic capacitor having a high resonance frequency. Further, in the present invention, since the high frequency is achieved by the structure of the capacitor itself, there is no restriction on the mounting structure of the capacitor and other elements on the substrate, and the present invention is versatile.
【００２１】請求項２によれば、前記共振周波数を高め
る接地用内部電極を、前記信号用内部電極の形成面と同
一面でかつ信号用内部電極の側方に付加したので、シー
ルド効果がさらに向上し、共振周波数を高める上でさら
に効果がある。According to the second aspect, the grounding internal electrode for increasing the resonance frequency is added to the same plane as the surface on which the signal internal electrode is formed and to the side of the signal internal electrode. It is more effective in improving the resonance frequency.
【図１】（Ａ）は貫通形積層セラミックコンデンサの一
例を示す斜視図、（Ｂ）、（Ｃ）はそれぞれ（Ａ）のＥ
−Ｅ、Ｆ−Ｆ断面図である。FIG. 1A is a perspective view showing an example of a through-type multilayer ceramic capacitor, and FIGS. 1B and 1C are E in FIG.
It is an E and FF sectional view.
【図２】貫通形積層セラミックコンデンサの他の例を示
す斜視図である。FIG. 2 is a perspective view showing another example of a through-type multilayer ceramic capacitor.
【図３】（イ）は従来の内部電極構造を示す平面図、
（ロ）、（ハ）はそれぞれ本発明による内部電極構造を
示す平面図、（ニ）、（ホ）はそれぞれ（ロ）、（ハ）
の内部電極構造を採用したコンデンサを示す断面図であ
る。FIG. 3A is a plan view showing a conventional internal electrode structure;
(B) and (c) are plan views showing the internal electrode structure according to the present invention, respectively, and (d) and (e) are (b) and (c) respectively.
FIG. 4 is a sectional view showing a capacitor employing the internal electrode structure of FIG.
【図４】（Ａ）、（Ｂ）はそれぞれコンデンサの特性測
定に用いた基板の構成を示す平面図及び側面図である。FIGS. 4A and 4B are a plan view and a side view, respectively, showing the configuration of a substrate used for measuring the characteristics of a capacitor.
【図５】（Ａ）、（Ｂ）はそれぞれ本発明によるコンデ
ンサの特性試験に供した実装構造の例を示す断面図であ
る。FIGS. 5A and 5B are cross-sectional views each showing an example of a mounting structure subjected to a characteristic test of a capacitor according to the present invention.
１ 接地用内部電極 １ 付加した接地用内部電極 ２ 信号用内部電極 ３ 誘電体層 ４、５ 信号用外部電極 ６ 接地用外部電極 ９ コンデンサ １０ 基板 １１、１２ ストリップライン １３ 接地層 １４、１５ ＳＭＡコネクタ １６ 接地用パターン １７ スルーホール １８ 半田 １９ 側面導体 DESCRIPTION OF SYMBOLS 1 Grounding internal electrode 1 Additional grounding internal electrode 2 Signaling internal electrode 3 Dielectric layer 4, 5 Signaling external electrode 6 Grounding external electrode 9 Capacitor 10 Substrate 11, 12 Stripline 13 Grounding layer 14, 15 SMA connector 16 Grounding pattern 17 Through hole 18 Solder 19 Side conductor
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭55−80313（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01G 4/00 - 4/40 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-55-80313 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01G 4/00-4/40
Claims (2)
体層を挟んでほぼ直角に交差して１組以上積層され、前
記信号用内部電極は誘電体層を貫通し、コンデンサの相
対する２つ側面に到達して該２つの側面に形成した信号
用外部電極に接続され、前記接地用内部電極は誘電体層
を貫通し、前記２つの側面に隣接しかつ相対する２つの
側面に到達して少なくとも該２つの側面に形成された接
地用外部電極に接続されてなる貫通形積層セラミックコ
ンデンサにおいて、信号用内部電極と積層方向に対向す
る形の接地用内部電極の他に、信号用内部電極と対向し
ない形に、共振周波数を高める接地用内部電極を付加し
たことを特徴とする貫通形積層セラミックコンデンサ。An internal electrode for grounding and an internal electrode for signal are laminated at least one pair at a right angle with a dielectric layer interposed therebetween, and the internal electrode for signal penetrates the dielectric layer and is opposed to a capacitor. To reach the two side surfaces to be connected to the signal external electrodes formed on the two side surfaces, and the grounding internal electrode penetrates through the dielectric layer and is adjacent to and opposed to the two side surfaces. In a through-type multilayer ceramic capacitor which reaches and is connected to a grounding external electrode formed on at least the two side surfaces, in addition to a grounding internal electrode facing the signal internal electrode in the stacking direction, a signal A through-type multilayer ceramic capacitor characterized by adding a grounding internal electrode for increasing a resonance frequency to a shape not facing the internal electrode.
る接地用内部電極を、前記信号用内部電極の形成面と同
一面でかつ信号用内部電極の側方に付加したことを特徴
とする貫通形積層セラミックコンデンサ。2. The through hole according to claim 1, wherein the grounding internal electrode for increasing the resonance frequency is added to the same plane as the surface on which the signal internal electrode is formed and to the side of the signal internal electrode. Type multilayer ceramic capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35342992A JP3233302B2 (en) | 1992-12-10 | 1992-12-10 | Feed-through multilayer ceramic capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35342992A JP3233302B2 (en) | 1992-12-10 | 1992-12-10 | Feed-through multilayer ceramic capacitors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06176962A JPH06176962A (en) | 1994-06-24 |
| JP3233302B2 true JP3233302B2 (en) | 2001-11-26 |
Family
ID=18430785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35342992A Expired - Lifetime JP3233302B2 (en) | 1992-12-10 | 1992-12-10 | Feed-through multilayer ceramic capacitors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3233302B2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890854A (en) * | 2003-12-22 | 2007-01-03 | X2Y艾泰钮埃特有限责任公司 | Internally shielded energy conditioner |
| US8761895B2 (en) | 2008-03-20 | 2014-06-24 | Greatbatch Ltd. | RF activated AIMD telemetry transceiver |
| JP5042892B2 (en) * | 2008-03-14 | 2012-10-03 | Ｔｄｋ株式会社 | Feedthrough capacitor |
| US10080889B2 (en) | 2009-03-19 | 2018-09-25 | Greatbatch Ltd. | Low inductance and low resistance hermetically sealed filtered feedthrough for an AIMD |
| US11147977B2 (en) | 2008-03-20 | 2021-10-19 | Greatbatch Ltd. | MLCC filter on an aimd circuit board conductively connected to a ground pin attached to a hermetic feedthrough ferrule |
| WO2009117599A2 (en) | 2008-03-20 | 2009-09-24 | Greatbatch Ltd. | Shielded three-terminal flat-through emi/energy dissipating filter |
| US10596369B2 (en) | 2011-03-01 | 2020-03-24 | Greatbatch Ltd. | Low equivalent series resistance RF filter for an active implantable medical device |
| US9931514B2 (en) | 2013-06-30 | 2018-04-03 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
| US11198014B2 (en) | 2011-03-01 | 2021-12-14 | Greatbatch Ltd. | Hermetically sealed filtered feedthrough assembly having a capacitor with an oxide resistant electrical connection to an active implantable medical device housing |
| US20130046354A1 (en) | 2011-08-19 | 2013-02-21 | Greatbatch Ltd. | Implantable cardioverter defibrillator designed for use in a magnetic resonance imaging environment |
| US9093974B2 (en) | 2012-09-05 | 2015-07-28 | Avx Corporation | Electromagnetic interference filter for implanted electronics |
| USRE46699E1 (en) | 2013-01-16 | 2018-02-06 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
| US10905888B2 (en) | 2018-03-22 | 2021-02-02 | Greatbatch Ltd. | Electrical connection for an AIMD EMI filter utilizing an anisotropic conductive layer |
| US10912945B2 (en) | 2018-03-22 | 2021-02-09 | Greatbatch Ltd. | Hermetic terminal for an active implantable medical device having a feedthrough capacitor partially overhanging a ferrule for high effective capacitance area |
-
1992
- 1992-12-10 JP JP35342992A patent/JP3233302B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06176962A (en) | 1994-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR970003365B1 (en) | Filter and electrical connector with filter | |
| JP3233302B2 (en) | Feed-through multilayer ceramic capacitors | |
| US9490768B2 (en) | High frequency band pass filter with coupled surface mount transition | |
| CN100550234C (en) | Multilayer chip capacitor and be embedded with the printed circuit board (PCB) of multilayer chip capacitor | |
| JP3106942B2 (en) | LC resonance components | |
| JP3756129B2 (en) | Transmission line type noise filter | |
| US20020024407A1 (en) | Distributed constant type noise filter | |
| JP5110807B2 (en) | Multilayer capacitor | |
| JP3067612B2 (en) | Stacked bandpass filter | |
| JP2005044871A (en) | Three terminal feed-through capacitor | |
| JP2817540B2 (en) | Low-pass filter | |
| JP4693588B2 (en) | Bandpass filter | |
| JP3230586B2 (en) | Central conductor for non-reciprocal circuit device and non-reciprocal circuit device | |
| JP4539440B2 (en) | Multilayer capacitor mounting structure | |
| JP3031957B2 (en) | Noise filter | |
| JP2000252164A (en) | Multilayer ceramic filter | |
| JP5384395B2 (en) | Distributed noise filter | |
| JP2010177696A (en) | Multilayer capacitor | |
| CN217589384U (en) | Filtering structure and electronic equipment | |
| JP3061092B2 (en) | Noise filter block with varistor function | |
| JPH06176959A (en) | Feedthrough type laminated ceramic capacitor | |
| JPH06176958A (en) | Packaging structure of feedthrough type laminated ceramic capacitor | |
| JPH06176961A (en) | Feedthrough type laminated ceramic capacitor | |
| CN112002551B (en) | Ultra-wideband capacitor with stable structure and using frequency reaching 40G + | |
| JPH06176960A (en) | Feedthrough type laminated ceramic capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20010905 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070921 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080921 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090921 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100921 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110921 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120921 Year of fee payment: 11 |