JPH06175876A - Semiconductor inspecting device - Google Patents

Abstract

PURPOSE:To provide the semiconductor inspector which can prevent the abnormal current of a device to be measured and can prevent the element destruction at the time of reference OFF. CONSTITUTION:Concerning the reference OFF of the semiconductor inspector defining a logic integrated circuit device provided with a self-diagnostic function as the device to be measured, the high level of test input signals TI11-TI1k or TIj1-Tljk at the high level when ending a test are first reduced to the lower limit value of an input high level voltage, namely, to a potential V1 close to +2V when a power supply voltage VCC is at a specified value, namely, at +5V, and the potential of the power supply voltage VCC is reduced to this potential V1 later. Next, the high level of the test input signal is reduced to the lower limit value of the input high level voltage, namely, to a potential V2 close to +1.5V when the power supply voltage VC is at the potential V1, and the potential of the power supply voltage VCC is reduced to this potential V2 later. Then, the absolute values of the power supply voltage VCC and the test input signal are stepwise and mutually reduced while repeating the similar processing afterwards.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor inspection apparatus, for example, a semiconductor inspection apparatus having a logic integrated circuit device having a self-diagnosis function as a device to be measured and a technique particularly effective for reference off thereof.

[0002]

2. Description of the Related Art There is a logic integrated circuit device such as a single-chip microcomputer having a self-diagnosis function. Further, there is a semiconductor inspection device in which such a logic integrated circuit device is an inspection target, that is, a device under test.

A semiconductor inspection apparatus using a logic integrated circuit device or the like as a device under test is described in, for example, April 1989.
"T3344 V" issued by Advantest Co., Ltd.
LSI test system general specifications ”.

[0004]

In the semiconductor inspection apparatus using the logic integrated circuit device having the self-diagnosis function as a device to be measured as described above, in order to prevent an abnormal operation at the time of power-off, for example, a high-level signal is generated at the end of the function. A reference-off procedure for the test input signal to be leveled is specified. That is, in the case of the conventional semiconductor inspection device, as illustrated in FIG. 4, the test input signal to the logic integrated circuit device LSI is, for example, the test input signal TI1 for each function or each block.
1 to TI1k to TIj1 to TIjk are divided into groups, and the test input signals are changed from the high level to the low level stepwise for each group over the time T1 to Tj. This prevents the test input signals from becoming a specific combination, and prevents an abnormal operation of the logic integrated circuit device LSI when the power is turned off.

However, with the progress of miniaturization and high integration of the logic integrated circuit device LSI, the following problems remain in the semiconductor inspection device adopting the above reference-off procedure. It became clear by the people.
That is, in the semiconductor inspection device, the test input signal to the logic integrated circuit device LSI is gradually changed from the high level to the low level for each function or block, and a relatively long time of several milliseconds is required until the reference off is completed. Will be needed. During this period, the logic integrated circuit device LSI is
Channel and N-Channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor. In this specification, MO
When a CMOS (complementary MOS) circuit composed of an SFET and collectively referred to as an insulated gate field effect transistor) is basically configured, a relatively large through current flows through these CMOS circuits, and particularly When the logic integrated circuit device LSI has a self-diagnosis function, all test output terminals TO11 of the logic integrated circuit device LSI are included.
A case where high levels are simultaneously output from TO1n or TOm1 to TOmn also occurs. For this reason, a remarkably large operating current is applied to the logic integrated circuit device LSI, and a large inductive power supply noise is generated with the change in the operating current. As a result, elements such as MOSFETs whose breakdown voltage has been lowered due to miniaturization may be destroyed, and the device under test as a product may be rendered unusable by the semiconductor inspection device.

An object of the present invention is to provide a semiconductor inspection apparatus capable of preventing an abnormal current in a device under test at the time of reference off and preventing element destruction.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the reference-off of the semiconductor inspection device having a logic integrated circuit device or the like having a self-diagnosis function as a device under test is first defined by the potential of the power supply voltage that defines the high level of the test input signal that is set to the high level at the end of the functional test. Value to the first potential close to the lower limit of the input high-level voltage, the power supply voltage is reduced to the first potential, and then the high level of the test input signal is changed to the power supply potential. After reducing to a second potential close to the lower limit value of the input high level voltage at the above-mentioned first potential, the potential of the power supply voltage is reduced to the second potential, and while repeating the same processing, that is, the power supply. The voltage and the absolute value of the test input signal are reduced stepwise and alternately.

[0009]

According to the above-mentioned means, the power supply voltage of the device under test can be gradually cut off while keeping the high level of the test input signal at the high level at the end of the functional test. Prevent a through current from flowing through these CMOS circuits in the case where the device is based on a CMOS circuit, and in particular, when the device under test has a self-diagnosis function, all test output terminals simultaneously output a high level. It is possible to avoid such an abnormal condition. As a result, it is possible to prevent an abnormal current in the device under measurement when the reference is turned off, and to prevent device breakdown such as MOSFET whose breakdown voltage is lowered due to miniaturization.

[0010]

1 is a connection diagram of an embodiment of a semiconductor inspection apparatus TE to which the present invention is applied. 2 shows an input characteristic diagram of an embodiment of a logic integrated circuit device LSI which is a device under test of the semiconductor inspection device TE of FIG. 1, and FIG. 3 shows the input characteristic diagram of the semiconductor inspection device TE of FIG. A flow diagram of one embodiment of reference off is shown. Based on these figures, the configuration and reference-off procedure of the semiconductor inspection apparatus TE of this embodiment and its features will be described. The logic integrated circuit device LSI as the device to be measured is basically composed of a CMOS circuit, and these circuit elements constituting the logic integrated circuit device are known CMOs.
It is formed on one semiconductor substrate such as single crystal silicon by the manufacturing technology of the S integrated circuit.

In FIG. 1, the semiconductor inspection apparatus TE of this embodiment includes a power supply voltage control circuit POWC, a test signal output circuit OC, a test signal input circuit IC, and a reference off control memory ROCM. Among these, the semiconductor inspection device TE is connected to the input terminal of the power supply voltage control circuit POWC.
Power supply voltage VCCO of positive potential from the power supply circuit (not shown)
Is supplied, and its output terminal is coupled to the power supply voltage supply terminal TVCC of the logic integrated circuit device LSI which is the device under test. The test signal output circuit OC is coupled to the corresponding input terminal of the logic integrated circuit device LSI via the test input terminals TI11 to TI1k to TIj1 to TIjk, and the test signal input circuit IC is connected to the test output terminals TO11 to TI11.
It is coupled to the corresponding output terminal of the logic integrated circuit device LSI via TO1n to TOm1 to TOmn. The semiconductor inspection device TE is further coupled to the logic integrated circuit device LSI via the ground potential supply terminal TVSS.

The power supply voltage control circuit POWC forms a predetermined power supply voltage VCC based on the power supply voltage VCCO supplied from the power supply circuit and supplies it to the logic integrated circuit device LSI via the power supply voltage supply terminal TVCC. In this embodiment, the power supply voltage VC supplied to the logic integrated circuit device LSI
As will be described later, the potential of C is set to its specified value during normal operation, that is, +5 V (volt), and is stepped according to the power supply voltage control signal PCS of a predetermined bit supplied from the reference-off control memory ROCM during reference-off. Lower, that is, the absolute value is gradually reduced.

Next, the test signal output circuit OC receives a command from a test control circuit (not shown) of the semiconductor tester TE and receives predetermined test input signals TI11 to TI1k to TIj1.
~ TIjk are selectively formed and supplied to the logic integrated circuit device LSI via the corresponding test input terminal. In this embodiment, the test input signals TI11 to TI1k to TI.
As will be described later, the high level of j1 to TIjk is set to a potential such as + 3V that exceeds the specified value thereof, that is, the input high level voltage V _IH during normal operation, and the reference off control memory ROC is turned off during reference off.
Test input control signal TIC of predetermined bit supplied from M
According to S, the absolute value is gradually reduced, that is, the absolute value is gradually reduced. The low level of the test input signals TI11 to TI1k to TIj1 to TIjk is set to the ground potential of the circuit.

The logic integrated circuit device LSI is a logic integrated circuit device such as a single chip microcomputer having a self-diagnosis function, and is a power supply voltage VCC supplied from the semiconductor inspection device TE via a power supply voltage supply terminal TVCC. And the ground potential of the circuit supplied through the ground potential supply terminal TVSS are used as its operating power supply. The logic integrated circuit device LSI has test input signals TI11 to TI supplied from the semiconductor inspection device TE via corresponding test input terminals.
Predetermined logical operation processing is executed according to 1k to TIj1 to TIjk to selectively form test output signals TO11 to TO1n to TOm1 to TOmn. These test output signals are supplied to the test signal input circuit IC of the semiconductor inspection device TE via the corresponding test output terminals.

Test signal input circuit I of semiconductor inspection equipment TE
C is a test output signal TO11 to TO1n output from the logic integrated circuit device LSI via the corresponding test output terminal.
To TOmn are determined, the normality thereof is confirmed, and the confirmation result is reported to a test control circuit (not shown).

The reference-off control memory ROCM is
The reference-off procedure created based on the input characteristics of the logic integrated circuit device LSI as the device under test is stored, and the power supply voltage control signal PCS and the test input control signal TICS are selectively formed according to the reference-off procedure. , The power supply voltage control circuit POWC and the test signal input circuit IC, respectively.

The reference-off procedure of the semiconductor inspection apparatus TE of this embodiment will be described with reference to FIGS. 2 and 3. As shown in FIG. 2, the logic integrated circuit device LSI, which is the device under test of the semiconductor inspection device TE, is
The lower limit, that is, the minimum value of the input high-level voltage is the specified value for the normal operation of the power supply voltage VCC, namely + 5V
Is + 2.0V, and the power supply voltage VCC is +
When it is set to 2.0V, it is set to + 1.5V. Power supply voltage V
When CC is set to + 1.5V, the logic integrated circuit device LS
I is put into an inoperable state, and its logical operation operation is stopped. The input characteristic of the logic integrated circuit device LSI shown in FIG. 2 is obtained as a result of a simulation performed using a computer after the design is completed.
Reference-off control memory RO for each device under test
Written to CM.

At time T0, the power of the test system is turned on, and the logic integrated circuit device L by the semiconductor inspection device TE is turned on.
When the SI functional test is started, the logic integrated circuit device LS
As shown in FIG. 3, a prescribed value for normal operation, that is, a power supply voltage VCC of + 5V is supplied to I, and the test input signals TI11 to TI1 are combined in a predetermined combination.
k to TIj1 to TIjk are selectively supplied. At this time, the high level of these test input signals is +3.
The potential is set to a relatively high potential such as 0 V, and its low level is set to 0 V, that is, the ground potential of the circuit.

Next, when the function test of the logic integrated circuit device LSI by the semiconductor inspection device TE is completed and the reference off is started at the time T1, first, the test input signals TI11 to TI1 which are set to the high level at the end of the test.
The high level of k to TIj1 to TIjk is the power supply voltage V
The potential of the power supply voltage VCC is reduced to the potential V1 (first potential) close to the input high level minimum voltage when CC is + 5V, that is, + 2.0V, and the potential of the power supply voltage VCC is the potential V1 at the time T2 when a predetermined period has elapsed from the time T1. To be made smaller. Next, at time T3 when a predetermined period has elapsed, the test input signals TI11 to TI1k to TIj1 to TIjk.
Of the power supply voltage VCC is the potential V1 or +2.
The potential is reduced to a potential V2 (second potential) close to the input high-level minimum voltage + 1.5V when the voltage is V, and further, the potential of the power supply voltage VCC is reduced to the potential V2 at time T4 when a predetermined period has elapsed. Then, at time T5 when the predetermined period has elapsed, the test input signals TI11 to TI
The high level of 1k to TIj1 to TIjk is set to the ground potential of the circuit, that is, 0V, and the potential of the power supply voltage VCC is set to 0V at the time T6 when the predetermined period lastly passed.

That is, the semiconductor inspection apparatus TE of this embodiment
Reference off of the test input signals TI11 to TI1k to TIj1 to TIj is set to a high level at the end of the test by gradually reducing the potential of the power supply voltage VCC supplied as an operating power supply to the logic integrated circuit device LSI.
The test input signal is performed while the high level of k is gradually and alternately reduced to the minimum input high level voltage at each potential of the power supply voltage VCC, and the logic operation of the logic integrated circuit device LSI is normally performed. The high level of is retained. Therefore, the logic integrated circuit device LSI has a CMOS
Despite being constructed based on a circuit, these CMs
It is possible to prevent an abnormal shoot-through current through the OS circuit, and the logic integrated circuit device LSI has a self-diagnosis function, so that the test output signals TO11 to TO1n or TOm1 to TOmn are simultaneously set to a high level in a specific combination of test input signals. In spite of the function to operate, it is possible to avoid such an output state at the time of reference off and suppress the generation of inductive power supply noise.
As a result, the logic integrated circuit device LS to be the device under test is obtained.
It is possible to prevent an abnormal current at the time of reference off of I, and prevent the breakdown of elements such as MOSFET whose breakdown voltage is lowered due to miniaturization.

As shown in the above-mentioned embodiment, by applying the present invention to a semiconductor inspection apparatus using a logic integrated circuit device having a self-diagnosis function as a device under test, the following operational effects are obtained. To be That is, (1) Reference off of a semiconductor inspection device having a logic integrated circuit device or the like having a self-diagnosis function as a device under test is performed by first setting a high level of a test input signal, which is set to a high level at the end of the functional test, to a power supply voltage. The potential of the power supply voltage is reduced to the first potential after reducing it to the first potential close to the lower limit value of the input high level voltage when the potential is at the specified value, and then the high level of the test input signal is changed to the power supply voltage. Is reduced to the second potential close to the lower limit value of the input high level voltage when the potential of is the above-mentioned first potential, the potential of the power supply voltage is reduced to the second potential, and the same processing is repeated thereafter. In other words, by increasing the power supply voltage and the absolute value of the test input signal stepwise and alternately, the high level of the test input signal is set to the high level at the end of the functional test. The effect that the power supply voltage of the device under test can be gradually cut off while holding the bell is obtained.

(2) According to the above item (1), especially when the device under test is constructed based on a CMOS circuit, an abnormal shoot-through current through these CMOS circuits is prevented, and in particular, the device under test is self-diagnosed. In the case of having a function, it is possible to obtain an effect that an abnormal state in which a high level is simultaneously output from all test output terminals can be avoided. (3) According to the above items (1) and (2), it is possible to prevent the abnormal current of the device under measurement at the time of reference off and prevent the breakdown of the device such as MOSFET whose breakdown voltage is lowered due to miniaturization. To be

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the power supply voltage VCC and the ground potential of the circuit can be supplied via a plurality of power supply voltage supply terminals and ground potential supply terminals, respectively.
Can also be provided with other various control terminals and the like. Block configuration of semiconductor inspection device TE and logic integrated circuit device LS
The I terminal configuration is not limited by this embodiment.

In FIG. 2, the input characteristic of the logic integrated circuit device LSI can be obtained by, for example, an experiment, not as a simulation result by a computer, and its specific value does not limit the present invention. Figure 3
, The test input signals TI11-T at time T5
The final potential reduction of I1k to TIj1 to TIjk to 0V may be performed stepwise for each group as shown in FIG. Further, the power supply voltage VCC and the test input signals TI11 to TI when the reference is off
The potential reduction of 1k to TIj1 to TIjk can also be performed in three or more stages according to the input characteristics of the logic integrated circuit device LSI. When the logic integrated circuit device LSI uses a power supply voltage of negative potential as its operating power supply, the reference off procedure of FIG. 3 is mirror-symmetrical with respect to the low level potential of the test input signal and the ground potential of the circuit, that is, 0V. It may be carried out in any form. Logic integrated circuit device L
The SI may be constructed based on a circuit other than the CMOS circuit, that is, a bipolar circuit or a bipolar CMOS circuit, for example.

In the above description, the case where the invention made by the present inventor is mainly applied to a semiconductor inspection apparatus having a logic integrated circuit device having a self-diagnosis function as a device under test, which is the background field of application, will be described. However, the present invention is not limited to this, and can be applied to, for example, various semiconductor inspection apparatuses in which various integrated circuit devices having the same self-diagnosis function are used as the device under test. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor inspection apparatus in which a semiconductor device in which an abnormal current may flow in a specific combination of test input signals is a device under test.

[0026]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the reference-off of the semiconductor inspection device having a logic integrated circuit device or the like having a self-diagnosis function as a device under test is first defined by the potential of the power supply voltage that defines the high level of the test input signal that is set to the high level at the end of the functional test. Value to the first potential close to the lower limit of the input high-level voltage, the power supply voltage is reduced to the first potential, and then the high level of the test input signal is changed to the power supply potential. After reducing to a second potential close to the lower limit value of the input high level voltage at the first potential, the potential of the power supply voltage is reduced to a second potential,
The same process is repeated thereafter, that is, by gradually decreasing the absolute value of the power supply voltage and the test input signal in an alternating manner to maintain the high level of the test input signal that is set to the high level at the end of the functional test. At the same time, since the power supply voltage of the device under test can be gradually cut off, a shoot-through current through these CMOS circuits can be prevented, especially when the device under test is constructed based on CMOS circuits, and the device under test can perform self-diagnosis. When it has a function, it is possible to avoid a state in which a high level is simultaneously output from all the test output terminals. As a result, it is possible to prevent an abnormal current in the device under measurement when the reference is turned off, and to prevent device breakdown such as MOSFET whose breakdown voltage is lowered due to miniaturization.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of a semiconductor inspection device to which the present invention is applied.

FIG. 2 is an input characteristic diagram showing an embodiment of a logic integrated circuit device which is a device under test of the semiconductor inspection device of FIG.

FIG. 3 is a flowchart showing one embodiment of reference off of the semiconductor inspection device of FIG.

FIG. 4 is a flowchart showing an example of reference off of a conventional semiconductor inspection device.

[Explanation of symbols]

TE ... Semiconductor inspection device, LSI ... Logic integrated circuit device. OC ... Test signal output circuit, IC ... Test signal input circuit, POWC ... Power supply voltage control circuit, ROC
M ... Reference-off control memory.

Claims (4)

[Claims] 1. A semiconductor inspection apparatus characterized in that reference-off is performed while gradually reducing the absolute values of a predetermined power supply voltage and a test input signal for a device under test in a stepwise and alternating manner. 2. The test input signal is a test input signal which is brought to a high level when a predetermined functional test of the device under test is completed, and the reference off is a high level of the test input signal. Is reduced to a first potential close to the lower limit value of the input high level voltage when the potential of the power supply voltage is at a specified value for normal operation, and then the potential of the power supply voltage is reduced to the first potential. Then, after reducing the high level of the test input signal to a second potential close to the lower limit value of the input high level voltage when the potential of the power supply voltage is the first potential, the potential of the power supply voltage is changed. 2. The semiconductor inspection apparatus according to claim 1, wherein the semiconductor potential is reduced to the second potential and the same processing is repeated thereafter. 3. The device under test is a logic integrated circuit device having a self-diagnosis function, and the lower limit value of the input high level voltage when the power supply voltage is set to each potential is:
3. The obtained result as a simulation result of the device under test.
Semiconductor inspection equipment. 4. The semiconductor inspection apparatus comprises a reference-off control memory for setting the potentials of the power supply voltage and the test input signal at each stage based on the simulation result of the device under test. The semiconductor inspection device according to claim 1, claim 2, or claim 3.