JPH06175157A - Active matrix type liquid crystal display - Google Patents

Active matrix type liquid crystal display

Info

Publication number
JPH06175157A
JPH06175157A JP32962292A JP32962292A JPH06175157A JP H06175157 A JPH06175157 A JP H06175157A JP 32962292 A JP32962292 A JP 32962292A JP 32962292 A JP32962292 A JP 32962292A JP H06175157 A JPH06175157 A JP H06175157A
Authority
JP
Japan
Prior art keywords
liquid crystal
crystal display
active matrix
matrix type
type liquid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32962292A
Other languages
Japanese (ja)
Other versions
JP3244552B2 (en
Inventor
Masao Muraide
正夫 村出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP32962292A priority Critical patent/JP3244552B2/en
Publication of JPH06175157A publication Critical patent/JPH06175157A/en
Priority to JP2000149710A priority patent/JP3760082B2/en
Application granted granted Critical
Publication of JP3244552B2 publication Critical patent/JP3244552B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To make an allowance in aligning precision when a liquid crystal display device is built up into a television, a video movie, a projector, etc., to simplify the packaging and to reduce a cost by forming the parting of the peripheral part of an image display region on a TFT substrate. CONSTITUTION:By forming a light shielding layer 1 on the peripheral part of the pixel region on the substrate side of a TFT (thin film transistor) in an active matrix type liquid crystal display, a parting is formed on the peripheral part of an image display region and the image display region is defined. The active matrix type liquid crystal display also incorporates a driver for driving data line and a driver for driving gate line on the same substrate as that of the pixel. The data line transmits successively a video signal fetched into a sample holder to a pixel, a scanning signal is imparted to the gate line and a TFT 2 turned on by the scanning signal writes a video signal fetched into the data line in a liquid crystal cell 3. This liquid crystal is used as a dynamic memory.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、アクティブ・マトリッ
クス型液晶表示装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device.

【0002】[0002]

【従来の技術】従来、アクティブ・マトリックス型液晶
表示装置の画素スイッチ素子を構成するTFTは、図8
に示すように画素電極19とデータ線17が同層でTF
Tを形成していたため、データ線が最上層になり、デー
タ線間に遮光層を形成し画像表示領域外周部に見切りを
形成することができなかった。よって、図9に示すよう
に対向基板22上のカラーフィルター(以下、CFと称
す)23外周部に遮光層27で見切りを形成していた。
2. Description of the Related Art Conventionally, a TFT which constitutes a pixel switch element of an active matrix type liquid crystal display device is shown in FIG.
As shown in, the pixel electrode 19 and the data line 17 are in the same layer as TF.
Since T was formed, the data line was the uppermost layer, and it was not possible to form a light-shielding layer between the data lines and form a parting line in the outer peripheral portion of the image display area. Therefore, as shown in FIG. 9, a parting is formed by the light shielding layer 27 on the outer peripheral portion of the color filter (hereinafter referred to as CF) 23 on the counter substrate 22.

【0003】[0003]

【発明が解決しようとする課題】TFT基板26と対向
基板22を貼り合わせる方法として、紫外線照射により
シール剤22を硬化させているが、この際、画像表示領
域25に形成しているTFT素子を保護するために対向
基板側から紫外線光を照射する。対向基板上の遮光層2
7は紫外線光を通さないため、シール剤24を確実に硬
化させるためには、対向基板上のCF外周部遮光層27
から対向基板端までシール用の透明絶縁領域を設けなけ
ればならない。前記透明絶縁領域により、画像表示領域
外周部の見切りとなる遮光領域面積を拡大することがで
きないため、モジュールに組み込む際の合わせ精度が要
求され、実装の簡略化,低コスト化の妨げとなる問題点
を有する。また、TFT基板側の画像表示領域25の拡
大が図れず、画素数の増加や画像表示領域がバックライ
トの光を透過する割合である開口率を向上することがで
きないといった微細化の妨げとなる問題点をも有する。
As a method of bonding the TFT substrate 26 and the counter substrate 22 to each other, the sealing agent 22 is cured by irradiation of ultraviolet rays. At this time, the TFT element formed in the image display area 25 is Ultraviolet light is irradiated from the counter substrate side for protection. Light-shielding layer 2 on the counter substrate
Since 7 does not transmit ultraviolet light, in order to surely cure the sealant 24, the CF outer peripheral light shielding layer 27 on the counter substrate is required.
A transparent insulating area for sealing must be provided from to the edge of the counter substrate. Since the area of the light-shielding area which is a parting of the outer peripheral portion of the image display area cannot be enlarged by the transparent insulating area, alignment accuracy is required when incorporating the module into the module, which hinders simplification of mounting and cost reduction. Have a point. Further, the image display region 25 on the TFT substrate side cannot be enlarged, which hinders miniaturization such that the number of pixels is increased and the aperture ratio, which is a ratio of transmitting light of the backlight to the image display region, cannot be improved. There are also problems.

【0004】[0004]

【課題を解決するための手段】本発明の透明基板上にT
FT素子を有する画素をマトリックス状に構成するアア
クティブ・マトリックス型液晶表示装置は、TFT基板
上に遮光層を形成することにより、画像表示領域外周部
に見切りを有することを特徴とする。前記遮光層は金属
あるいは金属化合物あるいは黒色系有機薄膜を用いるこ
とを特徴とする。
T is formed on the transparent substrate of the present invention.
An active matrix type liquid crystal display device in which pixels having FT elements are arranged in a matrix is characterized in that a light-shielding layer is formed on a TFT substrate so that the peripheral portion of the image display region has a parting. The light shielding layer is made of a metal, a metal compound, or a black organic thin film.

【0005】[0005]

【実施例】本発明のアクティブ・マトリックス型液晶表
示装置のTFT基板の構成図を、図1に示す。本発明の
アクティブ・マトリックス型液晶表示装置のTFT基板
側画素領域外周部に遮光層1を形成することにより、画
像表示領域を明確化している。前記アクティブ・マトリ
ックス型液晶表示装置は、データ線駆動用ドライバとゲ
ート線駆動用ドライバを画素と同一基板上に内蔵してい
る。データ線は、サンプルホルダーに取り込んだビデオ
信号を画素に順次送信している。またゲート線には、走
査信号を印加している。走査信号によりONしたTFT
2は、データ線に取り込まれたビデオ信号を液晶セル3
に書き込む。液晶はここではダイナミックメモリーとし
て使われる。一般に液晶の時定数は100ms前後であ
るから、これより短い周期でリフレッシュすれば十分信
号を保持することができる。また、必要に応じて保持容
量を液晶容量と並列に付加すると保持特性はさらに向上
する。保持容量の構成の仕方としては、透明導電膜を画
素電極の下に設ける方法,前段のゲート線に画素電極を
重ねる方法,専用の容量線をゲート線または信号線と平
行に配置して作り込む方法等がある。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a constitutional view of a TFT substrate of an active matrix type liquid crystal display device of the present invention. The image display area is clarified by forming the light shielding layer 1 on the outer peripheral portion of the pixel area on the TFT substrate side of the active matrix type liquid crystal display device of the present invention. The active matrix type liquid crystal display device incorporates a data line driving driver and a gate line driving driver on the same substrate as the pixels. The data line sequentially transmits the video signal captured in the sample holder to the pixels. A scanning signal is applied to the gate line. TFT turned on by scanning signal
2 is the liquid crystal cell 3 for transmitting the video signal taken in the data line.
Write in. The liquid crystal is used here as a dynamic memory. Generally, the time constant of the liquid crystal is around 100 ms, so that it is possible to hold a sufficient signal by refreshing in a cycle shorter than this. Further, if a storage capacitor is added in parallel with the liquid crystal capacitor as needed, the storage characteristics will be further improved. The storage capacitor is constructed by providing a transparent conductive film under the pixel electrode, stacking the pixel electrode on the gate line in the previous stage, and arranging a dedicated capacitance line in parallel with the gate line or the signal line. There are ways.

【0006】次に、本発明のアクティブ・マトリックス
型液晶表示装置のTFT基板の工程プロセスについて詳
細に説明する。図2、図3は、本発明のアクティブ・マ
トリックス型液晶表示装置のTFT基板の工程断面図を
表している。
Next, the process of manufacturing the TFT substrate of the active matrix type liquid crystal display device of the present invention will be described in detail. 2 and 3 are process cross-sectional views of the TFT substrate of the active matrix type liquid crystal display device of the present invention.

【0007】透明絶縁性基板9上にチャネル導電膜10
を500〜1500Å成膜する。チャネル導電膜として
は、駆動用ドライバを内蔵するため、CMOS構造が形
成可能でTFTのON/0FF比が高い多結晶シリコン
を使用する。多結晶シリコン成膜方法としては、モノシ
ラン(以下、SiH4と称す)を550℃〜650℃の
温度で熱分解して堆積する減圧CVD(Chemica
l Vapor Deposition)法がある。ま
た、更にTFTのON電流を向上させるために、前駆膜
としてプラズマCVD装置や減圧CVD装置により非晶
質シリコンを堆積した後、550〜650℃で4時間以
上の熱アニールを施すことにより、シリコン結晶を1μ
m以上に大粒径化することができる。結晶を大粒径化す
るには、熱アニールの他にエキシマ・レーザやアルゴン
・レーザなどのレーザアニール等がある。次に、前記多
結晶シリコン膜をフォトリソグラフィ法により島状にパ
ターニングした後、ゲート絶縁膜11を形成する。ゲー
ト絶縁膜には透明絶縁性基板として石英基板を使用した
場合、MOS工程を流用した高温ドライ酸化により緻密
で信頼性の高い酸化膜を形成できる。また、窒化膜やH
TO(High Temperature CVD S
ilicon Dioxide Film)等を用いて
も良い。次にゲート線12を形成する。ゲート線材料と
しては、多結晶シリコンを使用する。しかし、多結晶シ
リコンはシート抵抗が20Ω以上と高いため、横方向の
画素数が増大するとゲート走査線遅延を生じ易くなる。
そこで、更に低抵抗なモリブデンシリサイド(以下、M
oSiXと称す)やタングステンシリサイド(以下、W
SiXと称す)などの金属化合物やクロム(以下、Cr
と称す)やモリブデン(以下、Moと称す),タングス
テン(以下、Wと称す)などの金属配線を使用する場合
もある。次に、ゲート線をマスクとして、イオン打ち込
みにより、自己整合的にソース領域13,ドレイン領域
14を形成する。次に、基板全面に第1の層間絶縁膜を
形成する。第1の層間絶縁膜は、常圧CVD法や、テト
ラエトキシシラン(以下、TEOSと称す)ガスを用い
てSiO2膜を成膜する。前記SiO2膜の他にプラズマ
CVD法を用いて窒化膜を成膜しても良い。次に、デー
タ線と多結晶シリコンで形成したチャネル導電層10を
導通させるためにソース領域13上に開孔部を開け、デ
ータ線17を形成する。データ線の材料としては、アル
ミニュウム(以下、Alと称す)やCr,Mo,Wなど
のメタル配線を行う。データ線と同層に画素電極19を
形成してもかまわないが、データ線が最上層にくるた
め、データ線間上に画像表示領域見切り用の遮光層1を
形成できない。また、画素が高精細化してくると、パタ
ーンルール上、データ線と画素電極間のライン・アンド
・スペースが厳しくなり、容量カップリングが大きくな
る。これにより、リーク電流が大きくなり、コントラス
ト不足による表示品質劣化の原因となる。そこで、本発
明ではデータ線を画素電極より下層に埋め込んだ。これ
により、画素電極とデータ線のスペースを考慮する必要
がなく、画素電極領域を広げることが可能となり、光を
透過させることができる開口部面積を稼ぐことができ
る。データ線をフォトリソグラフィ法によりパターニン
グした後、基板全面に第2層間絶縁膜を成膜する。第2
層間絶縁膜の成膜方法としては、データ線材料として使
用する金属薄膜の溶融温度以下の温度で処理しなければ
ならない。そこで、データ線にAlを使用する場合、4
50℃以下の低温で絶縁膜を形成する必要がある。そこ
で、プラズマTEOS装置やプラズマ・オゾンTEOS
装置,常圧オゾンTEOS装置などで低温に絶縁膜を形
成する。前記第2層間絶縁膜上に金属あるいは金属化合
物をスパッタ法等により堆積し、フォトリソグラフィ法
によりパターニングして遮光層1を形成する。前記遮光
層は、画像表示領域外周部の見切りだけでなく、図3
(c)のように画像表示領域中のデータ線やゲート線上
を遮光することも可能である。前記遮光層としては、A
l,Cr,Mo,W等の金属薄膜や、MoSiX,WS
X等の金属化合物薄膜の他に、黒色系の有機薄膜を用
いても良い。次に、ドレイン領域14上にウエット・エ
ッチングあるいはドライ・エッチングにより開孔し、画
素電極19でをスパッタ法により成膜し、フォトリソグ
ラフィ法によりパターニングする。画素電極としては、
透明導電膜であるインジュム・スズ酸化物(以下、IT
Oと称す)等を用いる。遮光層と画素電極の工程は逆で
も問題ない。以上の工程により、TFTを形成する。
A channel conductive film 10 is formed on the transparent insulating substrate 9.
To form a film of 500 to 1500Å. As the channel conductive film, since a driving driver is incorporated, a polycrystalline silicon capable of forming a CMOS structure and having a high ON / 0FF ratio of TFT is used. As a method for forming a polycrystalline silicon film, low pressure CVD (Chemica) in which monosilane (hereinafter referred to as SiH 4 ) is thermally decomposed and deposited at a temperature of 550 ° C. to 650 ° C.
1 Vapor Deposition) method. In order to further improve the ON current of the TFT, amorphous silicon is deposited as a precursor film by a plasma CVD apparatus or a low pressure CVD apparatus, and then thermal annealing is performed at 550 to 650 ° C. for 4 hours or more. Crystal 1μ
The particle size can be increased to m or more. In order to increase the crystal grain size, laser annealing such as excimer laser or argon laser may be used in addition to thermal annealing. Next, after the polycrystalline silicon film is patterned into an island shape by a photolithography method, a gate insulating film 11 is formed. When a quartz substrate is used as a transparent insulating substrate for the gate insulating film, a dense and highly reliable oxide film can be formed by high temperature dry oxidation using a MOS process. In addition, nitride film and H
TO (High Temperature CVD S
ilicon Dioxide Film) or the like may be used. Next, the gate line 12 is formed. Polycrystalline silicon is used as the gate line material. However, since the sheet resistance of polycrystalline silicon is as high as 20Ω or more, when the number of pixels in the horizontal direction increases, a gate scanning line delay easily occurs.
Therefore, molybdenum silicide (hereinafter referred to as M
oSi X ) and tungsten silicide (hereinafter W)
Metal compounds such as Si X ) and chromium (hereinafter Cr
In some cases, metal wiring such as (hereinafter, referred to as), molybdenum (hereinafter, referred to as Mo), tungsten (hereinafter, referred to as W), or the like is used. Next, the source region 13 and the drain region 14 are formed in a self-aligned manner by ion implantation using the gate line as a mask. Next, a first interlayer insulating film is formed on the entire surface of the substrate. As the first interlayer insulating film, a SiO 2 film is formed by using a normal pressure CVD method or a tetraethoxysilane (hereinafter referred to as TEOS) gas. Besides the SiO 2 film, a plasma CVD method may be used to form a nitride film. Next, an opening is formed in the source region 13 to electrically connect the data line and the channel conductive layer 10 formed of polycrystalline silicon, and the data line 17 is formed. As a material of the data line, metal wiring such as aluminum (hereinafter referred to as Al) or Cr, Mo, W is used. The pixel electrode 19 may be formed in the same layer as the data lines, but since the data lines are located at the uppermost layer, the light shielding layer 1 for dividing the image display area cannot be formed between the data lines. In addition, as the pixel becomes finer, the line and space between the data line and the pixel electrode becomes stricter due to the pattern rule, and the capacitive coupling becomes larger. As a result, the leak current becomes large, which causes deterioration of display quality due to insufficient contrast. Therefore, in the present invention, the data line is embedded below the pixel electrode. As a result, it is not necessary to consider the space between the pixel electrode and the data line, the pixel electrode region can be expanded, and the area of the opening for transmitting light can be increased. After patterning the data lines by photolithography, a second interlayer insulating film is formed on the entire surface of the substrate. Second
As a method for forming the interlayer insulating film, it is necessary to perform processing at a temperature equal to or lower than the melting temperature of the metal thin film used as the data line material. Therefore, when using Al for the data line, 4
It is necessary to form the insulating film at a low temperature of 50 ° C. or lower. Therefore, plasma TEOS device and plasma ozone TEOS
An insulating film is formed at a low temperature by using an apparatus, a TEOS apparatus using atmospheric pressure ozone, or the like. A metal or a metal compound is deposited on the second interlayer insulating film by a sputtering method or the like and patterned by a photolithography method to form the light shielding layer 1. The light-shielding layer is formed not only on the outer peripheral portion of the image display area but also on the outer peripheral portion of FIG.
As in (c), it is possible to shield the data lines and gate lines in the image display area from light. As the light shielding layer, A
Metal thin films such as 1, Cr, Mo, W, MoSi X , WS
In addition to a metal compound thin film such as i X , a black organic thin film may be used. Next, a hole is formed on the drain region 14 by wet etching or dry etching, and the pixel electrode 19 is formed into a film by a sputtering method and patterned by a photolithography method. As the pixel electrode,
Indium tin oxide, which is a transparent conductive film (hereinafter referred to as IT
(Referred to as O) or the like is used. There is no problem even if the steps of the light shielding layer and the pixel electrode are reversed. The TFT is formed by the above steps.

【0008】次に、画像表示領域外周部の構成を実施例
に基づいて説明する。最初に、データ線のサンプルホル
ダーと画素間に形成する遮光層について2種類の構造を
試みた。第1の構造の平面図及び断面図を図4に示す。
図4(b)は、図4(a)のA−A´線の断面を表して
いる。透明絶縁性基板上9に第1層間絶縁膜16が堆積
し、前記絶縁膜上にデータ配線17が通り、第2層間絶
縁膜18上に遮光膜が堆積される。前記遮光膜は金属あ
るいは金属化合物により形成するため、第2の層間絶縁
膜に欠陥がある場合、データ線同士が遮光膜を介してシ
ョートし、縦方向の線欠陥を生じる可能性がある。デー
タ線は、Al等の金属により配線するので、それ自体、
遮光層の役目を果たす。そこで、第2の構造として図5
に示すように隣あうデータ線間のみに遮光膜1をフォト
リソグラフィ法により島状に形成した。これにより、絶
縁膜不良によるデータ線同士がショートするのを大幅に
防ぐことが可能となり、表示不良を抑制できる。
Next, the structure of the outer peripheral portion of the image display area will be described based on an embodiment. First, two types of structures were tried for the light-shielding layer formed between the sample holder of the data line and the pixel. A plan view and a sectional view of the first structure are shown in FIG.
FIG. 4B shows a cross section taken along the line AA ′ of FIG. The first interlayer insulating film 16 is deposited on the transparent insulating substrate 9, the data wiring 17 passes through the insulating film, and the light shielding film is deposited on the second interlayer insulating film 18. Since the light-shielding film is formed of a metal or a metal compound, when there is a defect in the second interlayer insulating film, the data lines may be short-circuited via the light-shielding film and a vertical line defect may occur. Since the data line is made of metal such as Al,
Acts as a light shielding layer. Therefore, as a second structure, FIG.
As shown in, the light shielding film 1 was formed in an island shape only between the adjacent data lines by the photolithography method. As a result, it is possible to significantly prevent the data lines from being short-circuited due to a defective insulating film, and it is possible to suppress defective display.

【0009】次に、ゲート線駆動用ドライバと画素間に
形成する遮光層についても本実施例では、2種類の構造
を試みた。第1の構造の平面図及び断面図を図6に示
す。図6(b)は、図6(a)のC−C´線の断面図を
表している。透明絶縁性基板9上にゲート線12を形成
し、前記ゲート線上に第1層間絶縁膜16と第2層間絶
縁膜18を成膜し、最上層に遮光膜1を形成した構造を
している。また、ゲート線は最下層に埋め込まれている
ため、第1層間絶縁膜上にデータ線で使用する金属薄膜
を遮光膜1の代わりに形成しても良い(図示なし)。こ
の構造は、前記図4で示したデータ線の構造と同様に層
間絶縁膜に欠陥が生じた場合、ゲート配線同士でショー
トし、横方向の線欠陥になる可能性がある。そこで第2
の構造として図7に示すように隣あうゲート線間にフォ
トリソグラフィ法により島状にパターニングして遮光層
1を形成した。この際、ゲート線が多結晶シリコンなど
の透過性の材料を用いた場合は、図7(b)に示すよう
に第1層間絶縁膜16上に、ゲート線膜上12を覆うよ
うにデータ線17で使用した金属材料を島状に堆積す
る。これにより、見切り領域を遮光することが可能とな
り、第1層間絶縁膜及び第2層間絶縁膜不良による表示
不良を抑制できる。
Next, two types of structures were tried in this embodiment for the light-shielding layer formed between the gate line driving driver and the pixel. A plan view and a sectional view of the first structure are shown in FIG. FIG. 6B shows a cross-sectional view taken along the line CC ′ of FIG. The gate line 12 is formed on the transparent insulating substrate 9, the first interlayer insulating film 16 and the second interlayer insulating film 18 are formed on the gate line, and the light shielding film 1 is formed on the uppermost layer. . Further, since the gate line is buried in the lowermost layer, a metal thin film used for the data line may be formed on the first interlayer insulating film instead of the light shielding film 1 (not shown). Similar to the structure of the data line shown in FIG. 4, in this structure, when a defect occurs in the interlayer insulating film, there is a possibility that the gate wirings are short-circuited with each other and a lateral line defect occurs. So the second
As shown in FIG. 7, the light shielding layer 1 was formed by patterning between adjacent gate lines in an island shape by photolithography. At this time, when the gate line is made of a transparent material such as polycrystalline silicon, the data line is formed on the first interlayer insulating film 16 so as to cover the gate line film 12 as shown in FIG. 7B. The metal material used in 17 is deposited in an island shape. This makes it possible to shield the parting region from light and suppress display defects due to defects in the first interlayer insulating film and the second interlayer insulating film.

【0010】[0010]

【発明の効果】画像表示領域外周部の見切りをTFT基
板上に作り込むことにより、以下の効果が得られた。
[Effects of the Invention] The following effects were obtained by forming a parting of the outer peripheral portion of the image display area on the TFT substrate.

【0011】図10に示すように、従来のシール領域
に遮光領域を広げることができるため見切り幅が広くな
る。これにより、本発明の液晶表示装置をテレビやビデ
オムービー,プロジェクター等のモジュールに組み込む
際の合わせ精度に余裕ができるため、実装面での簡略
化,低コスト化が図れる。
As shown in FIG. 10, since the light-shielding region can be expanded to the conventional seal region, the parting width is widened. As a result, the liquid crystal display device of the present invention can be provided with sufficient alignment accuracy when it is incorporated in a module such as a television, a video movie, and a projector, so that the mounting can be simplified and the cost can be reduced.

【0012】図12に示すように、対向基板上の遮光
層27を形成せずに、TFT基板26上の遮光層1上部
にシール領域を形成できるため、TFT基板に形成した
画像表示領域25を広げることが可能となり、アクティ
ブ・マトリックス型液晶表示装置の外形サイズを拡大さ
せることなく、画素数の増加や開口率の向上を図れる。
As shown in FIG. 12, since the seal region can be formed on the light shielding layer 1 on the TFT substrate 26 without forming the light shielding layer 27 on the counter substrate, the image display region 25 formed on the TFT substrate can be formed. It is possible to increase the number of pixels and the aperture ratio without increasing the outer size of the active matrix type liquid crystal display device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示すアクティブ・マトリック
ス型液晶表示装置の平面構成図。
FIG. 1 is a plan configuration diagram of an active matrix type liquid crystal display device showing an embodiment of the present invention.

【図2】本発明の実施例を示すアクティブ・マトリック
ス型液晶表示装置の画素TFTのデータ線形成までの工
程断面図。
FIG. 2 is a process sectional view of forming a data line of a pixel TFT of an active matrix type liquid crystal display device showing an embodiment of the present invention.

【図3】本発明の実施例を示すアクティブマトリックス
型液晶表示装置の画素TFTの前記図2以降の工程断面
図。
3A and 3B are sectional views of the pixel TFT of the active matrix type liquid crystal display device showing the embodiment of the present invention, showing the step after FIG.

【図4】本発明の実施例を示すアクティブ・マトリック
ス型液晶表示装置のサンプルホルダーと画像表示領域間
の構成図。(a)は平面図。(b)はA−A´線上の断
面図。
FIG. 4 is a configuration diagram between a sample holder and an image display area of an active matrix type liquid crystal display device showing an embodiment of the present invention. (A) is a plan view. (B) is sectional drawing on the AA 'line.

【図5】本発明の実施例を示すアクティブ・マトリック
ス型液晶表示装置のサンプルホルダーと画像表示領域間
の構成図。(a)は平面図。(b)はB−B´線上の断
面図。
FIG. 5 is a configuration diagram between a sample holder and an image display area of an active matrix type liquid crystal display device showing an embodiment of the present invention. (A) is a plan view. (B) is sectional drawing on the BB 'line.

【図6】本発明の実施例を示すアクティブ・マトリック
ス型液晶表示装置のゲート線駆動用ドライバと画像表示
領域間の構成図。(a)は平面図。(b)はC−C´線
上の断面図。
FIG. 6 is a configuration diagram between a driver for driving a gate line and an image display region of an active matrix type liquid crystal display device showing an embodiment of the present invention. (A) is a plan view. (B) is sectional drawing on CC 'line.

【図7】本発明の実施例を示すアクティブ・マトリック
ス型液晶表示装置のゲート線駆動用ドライバと画像表示
領域間の構成図。(a)は平面図。(b)はD−D´線
上の断面図。
FIG. 7 is a configuration diagram between a driver for driving a gate line and an image display area of an active matrix type liquid crystal display device showing an embodiment of the present invention. (A) is a plan view. (B) is sectional drawing on the DD 'line.

【図8】従来のアクティブ・マトリックス型液晶表示装
置の画素TFTの断面図。
FIG. 8 is a cross-sectional view of a pixel TFT of a conventional active matrix type liquid crystal display device.

【図9】従来のアクティブ・マトリックス型液晶表示装
置の断面図。
FIG. 9 is a sectional view of a conventional active matrix type liquid crystal display device.

【図10】本発明の実施例を示すアクティブ・マトリッ
クス型液晶表示装置の断面図。
FIG. 10 is a sectional view of an active matrix type liquid crystal display device showing an embodiment of the present invention.

【図11】本発明の実施例を示すアクティブ・マトリッ
クス型液晶表示装置の断面図。
FIG. 11 is a sectional view of an active matrix type liquid crystal display device showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 遮光層 2 TFT素子 3 液晶セル 4 データ線駆動用クロック信号入力端子 5 データ線駆動用スタート信号入力端子 6 ビデオ信号入力端子 7 ゲート線駆動用クロック信号入力端子 8 ゲート線駆動用スタート信号入力端子 9 透明絶縁性基板 10 チャネル導電層 11 ゲート絶縁膜 12 ゲート線 13 ソース領域 14 ドレイン領域 15 イオン不純物 16 第1層間絶縁膜 17 データ線 18 第2層間絶縁膜 19 画素電極 20 液晶 21 偏向板 22 対向基板 23 カラーフィルター 24 シール剤 25 画像表示領域(画素) 26 TFT基板 27 対向基板側画像表示領域(カラーフィルタ
ー)外周遮光層
1 Light-shielding layer 2 TFT element 3 Liquid crystal cell 4 Data line driving clock signal input terminal 5 Data line driving start signal input terminal 6 Video signal input terminal 7 Gate line driving clock signal input terminal 8 Gate line driving start signal input terminal 9 transparent insulating substrate 10 channel conductive layer 11 gate insulating film 12 gate line 13 source region 14 drain region 15 ion impurity 16 first interlayer insulating film 17 data line 18 second interlayer insulating film 19 pixel electrode 20 liquid crystal 21 deflector 22 facing Substrate 23 Color filter 24 Sealant 25 Image display area (pixel) 26 TFT substrate 27 Counter substrate side image display area (color filter) Peripheral light-shielding layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】透明絶縁性基板上に、薄膜トランジスタ
(以下、TFTと称す)素子を有する画素をマトリック
ス状に構成するアクティブ・マトリックス型液晶表示装
置に於いて、TFT基板上に遮光層を形成することによ
り、画像表示領域外周部に見切りを有することを特徴と
するアクティブ・マトリックス型液晶表示装置。
1. A light-shielding layer is formed on a TFT substrate in an active matrix type liquid crystal display device in which pixels having thin film transistor (hereinafter referred to as TFT) elements are arranged in a matrix on a transparent insulating substrate. Thus, the active matrix type liquid crystal display device is characterized in that it has a parting in the outer peripheral portion of the image display area.
【請求項2】前記遮光層は、金属あるいは金属化合物あ
るいは黒色系有機薄膜を用いることを特徴とする請求項
1記載のアクティブ・マトリックス型液晶表示装置。
2. The active matrix type liquid crystal display device according to claim 1, wherein the light shielding layer is made of a metal, a metal compound or a black organic thin film.
JP32962292A 1992-12-09 1992-12-09 Active matrix type display device and manufacturing method thereof Expired - Lifetime JP3244552B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP32962292A JP3244552B2 (en) 1992-12-09 1992-12-09 Active matrix type display device and manufacturing method thereof
JP2000149710A JP3760082B2 (en) 1992-12-09 2000-05-22 Active matrix type liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32962292A JP3244552B2 (en) 1992-12-09 1992-12-09 Active matrix type display device and manufacturing method thereof

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2000149711A Division JP3733278B2 (en) 1992-12-09 2000-05-22 Active matrix type liquid crystal display device
JP2000149710A Division JP3760082B2 (en) 1992-12-09 2000-05-22 Active matrix type liquid crystal display device

Publications (2)

Publication Number Publication Date
JPH06175157A true JPH06175157A (en) 1994-06-24
JP3244552B2 JP3244552B2 (en) 2002-01-07

Family

ID=18223416

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Country Status (1)

Country Link
JP (1) JP3244552B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08328000A (en) * 1995-06-01 1996-12-13 Semiconductor Energy Lab Co Ltd Active matrix type liquid crystal display device
JPH10125931A (en) * 1996-08-27 1998-05-15 Seiko Epson Corp Transfer of thin film element, thin film element, thin film integrated circuit device, active materix substrate and liquid crystal display device
JPH10161157A (en) * 1996-12-03 1998-06-19 Sony Corp Semiconductor device for display
JP2003035909A (en) * 2001-07-24 2003-02-07 Toshiba Corp Method for manufacturing plane display element and plane display element
US6798474B2 (en) 1997-03-25 2004-09-28 Sharp Kabushiki Kaisha LCD with light shielding on same insulator as pixel and extending beyond sealant inner surface
US6897932B2 (en) 1997-12-19 2005-05-24 Seiko Epson Corporation Electro-optical device having a concave recess formed above a substrate in correspondence with a plurality of wirings and an electro-optical apparatus having same
USRE40601E1 (en) 1996-11-12 2008-12-09 Seiko Epson Corporation Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device
US7808586B2 (en) 2006-06-06 2010-10-05 Seiko Epson Corporation Electrooptic device and electronic device including the same
JP2013140367A (en) * 2013-01-16 2013-07-18 Semiconductor Energy Lab Co Ltd Liquid crystal display device
JP2017003855A (en) * 2015-06-12 2017-01-05 株式会社ジャパンディスプレイ Display device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08328000A (en) * 1995-06-01 1996-12-13 Semiconductor Energy Lab Co Ltd Active matrix type liquid crystal display device
JPH10125931A (en) * 1996-08-27 1998-05-15 Seiko Epson Corp Transfer of thin film element, thin film element, thin film integrated circuit device, active materix substrate and liquid crystal display device
USRE40601E1 (en) 1996-11-12 2008-12-09 Seiko Epson Corporation Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device
JPH10161157A (en) * 1996-12-03 1998-06-19 Sony Corp Semiconductor device for display
US6798474B2 (en) 1997-03-25 2004-09-28 Sharp Kabushiki Kaisha LCD with light shielding on same insulator as pixel and extending beyond sealant inner surface
US6897932B2 (en) 1997-12-19 2005-05-24 Seiko Epson Corporation Electro-optical device having a concave recess formed above a substrate in correspondence with a plurality of wirings and an electro-optical apparatus having same
JP2003035909A (en) * 2001-07-24 2003-02-07 Toshiba Corp Method for manufacturing plane display element and plane display element
US7808586B2 (en) 2006-06-06 2010-10-05 Seiko Epson Corporation Electrooptic device and electronic device including the same
JP2013140367A (en) * 2013-01-16 2013-07-18 Semiconductor Energy Lab Co Ltd Liquid crystal display device
JP2017003855A (en) * 2015-06-12 2017-01-05 株式会社ジャパンディスプレイ Display device

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