JPH06169433A - Driving signal generating circuit for solid image pickup device - Google Patents

Abstract

PURPOSE:To improve a reliability by outputting a reception permitting signal in an invalid video period, converting it into a pulse whose width is narrow by a differentiation circuit, and synthesizing it with the data of a register. CONSTITUTION:A communication between a controller and a solid image pickup device is operated in the invalid video period in which a noise is difficult to be superimposed on a picture. The discrimination of the valid video period from the invalid video period is operated by a driving circuit, and outputted as a reception permitting signal 26. The signal 26 is converted into the pulse whose width is narrow by a differentiation circuit 27, and inputted to a synthesizing circuit 9. And also, control data 21 are read in a reception shift register 1 by a shift clock 22. The read command of one word is divided into data to a mode register and a selection code signal, the selection code signal is synthesized with a control signal prepared from the clock 22 by a control signal generating circuit 12 by a decode circuit 3. The synthesized signal is decoded into writing signals to each mode register 4-8, and a prescribed state is established as necessary by an initialize 23. Thus, the reliability can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive signal generating circuit for a solid-state image pickup device, and more particularly to a circuit for transmitting mode register data or status data of another block without increasing interface signals and invalidating status reception. By performing it during the video period, it is possible to check the reception status of control data and know the status of other blocks without generating noise on the screen, and to improve the reliability of the solid-state imaging device only by changing the program of the controller. The present invention relates to a drive signal generation circuit that can be increased.

[0002]

2. Description of the Related Art Conventionally, a drive signal generating circuit of this type of solid-state image pickup device has a structure shown in FIG. The controller and the drive signal generating circuit of the solid-state image pickup device include a control data 21, a shift clock 22, and an initialization 2
3 and the reception permission signal 26 are connected. The control data 21 is read into the reception shift register 1 by the shift clock 22. The read 1-word command is divided into data for the mode register and a selection code signal, and the selection code signal is the control signal generation circuit 2
Then, the control signal generated from the shift clock 22 is combined with the decoder circuit 3 and decoded into a write signal to the mode registers 4 to 8. FIG. 5 shows the mode registers 4 to
8 shows a timing chart of setting mode register data to 8. The initialization 23 is a signal for establishing a certain state when the power is turned on and when necessary.
The reception permission signal 26 is a signal which is generated in another block and is effective in the vertical blanking period where the influence of noise on the solid-state imaging device is small.

[0003]

In the drive signal generation circuit of the conventional solid-state image pickup device, since the states of the mode register and other blocks cannot be known, communication error between the controller and the drive signal generation circuit and Even if the desired mode is not set due to a failure or the controller is malfunctioning, the controller has no means of knowing these states.Therefore, the initialization is sent to the drive signal generation circuit to confirm a certain state and return it to the normal state by feedback. There is a problem that the reliability of the image pickup device cannot be increased.

[0004]

A drive signal generation circuit for a solid-state image pickup device according to the present invention generates a control signal from a reception shift register for receiving control data from a controller and performing parallel-to-serial conversion, and a shift clock from the controller. A control signal generation circuit, a decoder circuit for generating a mode register selection write signal from a selection code signal from the reception shift register and a write signal from the control signal generation circuit, and a plurality of mode registers for storing various modes. A select circuit for selecting a part of the data of the plurality of mode registers or the state data of another block by a selection code signal from the reception shift register, and storing the data selected by the select circuit in parallel. Transmission shift register for direct conversion and the control data A differentiating circuit for converting a signal representative of whether to receive the narrow pulse, and a combining circuit for combining the data and output the transmit shift register of the differentiation circuit.

[0005]

1 is a block diagram of an embodiment of the present invention. The controller and the drive signal generation circuit of the solid-state imaging device are connected by a control data 21, a shift clock 22, an initialization 23, and a composite output 24.

Communication between the controller and the drive circuit of the solid-state image pickup device is performed during the invalid video period because noise is likely to be generated in the image when the communication is performed during the valid video period. The determination of the valid video period or the invalid video period is performed by another block of the drive circuit of the solid-state image pickup device, which is output as the reception permission signal 26, converted into a narrow pulse by the differentiating circuit 27, and combined by the combining circuit 9 to be combined. It is output as the output 24. The controller determines that the first falling edge of the combined output 24 after transmitting the control data is the reception permission signal and starts communication.

The flow of control data 21 is read into the reception shift register 1 by the shift clock 22. The read 1-word command is divided into data for the mode register and a selection code signal. The selection code signal is combined with the control signal generated from the shift clock 22 in the control signal generation circuit 12 in the decoder circuit 3, It is decoded into a write signal to the mode registers 4-8. The initialization 23 is a signal for establishing a certain state when the power is turned on and when necessary.

When it is desired to know the data in the mode registers 4 to 8, the control data 21 is set in the mode register 4
Send a command to send a set of data from ~ 8,
The shift clock 22 causes the reception shift register 1 to read it.

In FIG. 2, one word has a structure of 8 bits and 3
6 is a timing chart when bits are assigned to a mode register selection code and 5 bits are assigned to a period for reading the contents of the mode register. The select circuit 11 selects the data of the mode registers 4 to 8 designated by the mode register selection code from the reception register 1 and causes the transmission shift register 10 to read the data. The mode register data is
The transmission shift register 10 performs parallel-to-serial conversion in synchronization with the shift clock 22, and the synthesizing circuit 9 synthesizes it with the reception permission signal 26 and transmits it as a synthetic output 24. In FIG. 2, it can be seen from the read data that the drive signal generating circuit is malfunctioning, and when the drive signal generating circuit sends the initialization 23 to determine the drive signal generating circuit to a certain state and tries to restore the normal state. Shows.

FIG. 3 shows another embodiment of the present invention.
In this embodiment, the select function is further enhanced as compared with the previous embodiment, and the state 25 of other blocks can be selected by the select circuit 11. Other than this, it is the same as the previous embodiment.

[0011]

As described above, according to the present invention, the receiving shift register for receiving the control data from the controller and performing the parallel / serial conversion, the control signal generating circuit for generating the shift clock exposure control signal from the controller, and the receiving A decoder circuit for generating a mode register selection write signal from a selection code signal from a shift register and a write signal from the control signal generation circuit, a plurality of mode registers for storing various modes, and data of the plurality of mode registers A select circuit that selects one set of data or state data of another block by a selection code signal from the receive shift register; and a transmit shift register that stores the data selected by the select circuit and performs parallel-to-serial conversion. , A signal indicating whether or not the control data can be received By having a synthesizing circuit for synthesizing the data of the transmission shift register, it becomes possible to confirm the receiving state of the control data and to know the states of other blocks, and the solid-state image pickup device This has the effect of increasing the reliability.

[Brief description of drawings]

FIG. 1 is a drive signal generation circuit of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for reading the mode register data of the drive signal generation circuit of the present invention or the state of another block.

FIG. 3 is a drive signal generation circuit of a solid-state imaging device according to another embodiment of the present invention.

FIG. 4 is a drive signal generation circuit of a conventional solid-state imaging device.

FIG. 5 is a timing chart of setting in a mode register.

[Explanation of symbols]

 1 reception shift register 2 control signal generation circuit 3 decoder circuit 4-8 mode register 9 synthesis circuit 10 transmission shift register 11 select circuit 12 control signal generation circuit 21 control data 22 shift clock 23 initialization 24 synthesis output 25 state of other block 26 Reception permission signal 27 Differentiation circuit

Claims (1)

[Claims] 1. A reception shift register that receives control data from a controller and performs parallel-to-serial conversion, a control signal generation circuit that generates a control signal from a shift clock from the controller, a selection code signal from the reception shift register, and the A decoder circuit for generating a mode register selection write signal from the write signal from the control signal generation circuit, a plurality of mode registers for storing various modes, and a part of the data of the plurality of mode registers or other data. A select circuit that selects the block state data as a good selection code signal from the receive shift register, a transmit shift register that stores the selected data that is good in the select circuit, and performs parallel-to-serial conversion, and whether or not the control data can be received. A differentiating circuit that converts the signal representing A drive signal generating circuit for a solid-state imaging device, comprising: a combining circuit for combining the output of the differentiating circuit and the data of the transmission shift register.