JPH06168948A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06168948A JPH06168948A JP34541192A JP34541192A JPH06168948A JP H06168948 A JPH06168948 A JP H06168948A JP 34541192 A JP34541192 A JP 34541192A JP 34541192 A JP34541192 A JP 34541192A JP H06168948 A JPH06168948 A JP H06168948A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- connection
- parallelism
- substrate
- protrusions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、半導体素子の電極を
基板の配線部に直接接続するフェイスダウン方式の半導
体装置の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a face-down type semiconductor device in which electrodes of semiconductor elements are directly connected to wiring portions of a substrate.
【0002】[0002]
【従来の技術】半導体素子を基板上に搭載した半導体装
置としては、液晶モジュール、ELパネル等多くのもの
が開発されており、半導体素子の電極と基板上の配線部
との接続手段としては細いワイヤを用いるワイヤボンデ
ィング方式のほか、半導体素子の電極を基板の配線部に
直接接続するフェイスダウン方式も知られている(例え
ば、特公平2−7180号公報参照)。このフェイスダ
ウン方式は半導体素子の電極上に導電性の接続用突起を
形成し、対応した配線部をパターン形成した基板上に接
着材料を介在させて配置し、位置合わせして加圧した
後、この加圧状態で接着材料を硬化させるものであっ
て、接続用突起には金属、導電性ペースト、ゴムコネク
タ等が用いられ、また接着材料には光硬化性樹脂、熱硬
化性樹脂等が用いられており、接続用突起を微細にする
ことが容易であるので、配線ピッチが狭い高密度実装に
はワイヤボンディング方式よりも適している。2. Description of the Related Art As a semiconductor device in which a semiconductor element is mounted on a substrate, many ones such as a liquid crystal module and an EL panel have been developed, and the connecting means between the electrode of the semiconductor element and the wiring portion on the substrate is thin. In addition to a wire bonding method using a wire, a face-down method in which an electrode of a semiconductor element is directly connected to a wiring portion of a substrate is also known (for example, see Japanese Patent Publication No. 2-7180). In this face-down method, conductive connecting protrusions are formed on the electrodes of the semiconductor element, and the corresponding wiring portions are arranged on the patterned substrate with an adhesive material interposed between them. The adhesive material is cured under this pressure, and metal, conductive paste, rubber connector, etc. are used for the connection protrusions, and photo-curable resin, thermosetting resin, etc. are used for the adhesive material. Since it is easy to make the connecting projections fine, it is more suitable than the wire bonding method for high-density mounting with a narrow wiring pitch.
【0003】しかしながら、接続用突起を微細にするほ
ど、基板上に半導体素子を重ねて加圧する際の基板と半
導体素子との平行度が重要となり、平行度が悪いと荷重
の少なかった部分での接続不良が発生しやすくなるとい
う問題点がある。また基板と半導体素子が平行になって
いても、接続用突起の配置が半導体素子の中心に対して
対称的でない場合には加圧力の加わり方がアンバランス
となり、接続用突起の密度が高い部分では荷重が低下し
て接続不良が生じやすくなる。図4は接続不良が生じや
すい配置の一例であり、図のように半導体素子1の上下
と右側の側縁に沿って接続用突起2が形成され、左側の
側縁1aには接続用突起2が形成されていない場合に
は、加圧力が側縁1aに加わりやすいために上下側縁の
左側の接続用突起2は十分に加圧されるが、右側の接続
用突起2は加圧力が不足気味となって接続不良が生じや
すくなるのである。However, as the connecting projections are made finer, the parallelism between the substrate and the semiconductor element becomes more important when the semiconductor elements are stacked on the substrate and pressed, and when the parallelism is poor, the load is small in the portion. There is a problem that connection failure is likely to occur. Even if the substrate and the semiconductor element are parallel to each other, if the arrangement of the connecting protrusions is not symmetrical with respect to the center of the semiconductor element, the applied pressure will be unbalanced and the connecting protrusions will have a high density. In this case, the load is reduced and connection failure is likely to occur. FIG. 4 is an example of an arrangement in which connection failure is likely to occur. As shown in the figure, the connection protrusions 2 are formed along the upper and lower sides and the right side edge of the semiconductor element 1, and the connection protrusion 2 is formed on the left side edge 1a. When the protrusions are not formed, since the pressing force is easily applied to the side edge 1a, the connecting projections 2 on the left side of the upper and lower side edges are sufficiently pressed, but the connecting projections 2 on the right side are insufficient in pressing force. It tends to cause poor connection.
【0004】また、平行度は接続用突起の潰れ具合で確
認することができるのでこれによって平行度を調整する
ことができ、例えば基板と電極が透明な液晶モジュール
の場合には接続用突起の潰れ具合を目視観察することが
可能である。しかし、ITO等の透明な材料で電極を形
成した場合には、接触抵抗や配線抵抗を低くするために
その表面に金、銀、アルミニウム等の金属材料が積層さ
れるため、確認用として金属材料が積層されない部分を
残すようにしており、抵抗の高い部分が存在することに
よって液晶モジュールの表示性能に悪影響が出る可能性
があった。Further, since the parallelism can be confirmed by the degree of collapse of the connection projection, the parallelism can be adjusted by this. For example, in the case of a liquid crystal module having a transparent substrate and electrodes, the connection projection is collapsed. It is possible to visually observe the condition. However, when the electrode is formed of a transparent material such as ITO, a metal material such as gold, silver, or aluminum is laminated on the surface to reduce the contact resistance and the wiring resistance, and therefore the metal material is used for confirmation. However, there is a possibility that the display performance of the liquid crystal module may be adversely affected by the presence of the high resistance portion.
【0005】[0005]
【発明が解決しようとする課題】この発明はこの点に着
目し、平行度を出しやすくし、あるいはその確認を容易
に行えるようにすることを課題としてなされたものであ
る。SUMMARY OF THE INVENTION The present invention has been made in view of this point, and an object thereof is to make parallelism easy or to easily confirm the parallelism.
【0006】[0006]
【課題を解決するための手段】上述の課題を解決するた
めに、第1の発明では、半導体素子に形成される接続用
突起を半導体素子の中心に対して対称に配置するように
している。また第2の発明では、電極上に形成された導
電性の接続用突起とは別に半導体素子の外周部に平行度
確認用突起を設けるようにしている。In order to solve the above-mentioned problems, in the first invention, the connecting projections formed on the semiconductor element are arranged symmetrically with respect to the center of the semiconductor element. In the second aspect of the invention, the parallelism confirming protrusion is provided on the outer peripheral portion of the semiconductor element in addition to the conductive connecting protrusion formed on the electrode.
【0007】[0007]
【作用】第1の発明では、接続用突起が半導体素子の中
心に対して対称に配置されているので、平行度を保って
すべての接続用突起に均等に加圧力を加えることが容易
となる。また第2の発明では、平行度確認用突起が設け
られる部分は接触抵抗の問題がなく透明なままでよいの
で、その潰れ具合で平行度を目視確認して平行度を正し
く調整することができる。In the first aspect of the invention, since the connecting projections are arranged symmetrically with respect to the center of the semiconductor element, it is easy to apply parallel pressing force to all the connecting projections while maintaining parallelism. . Further, in the second aspect of the invention, since the portion provided with the parallelism confirmation projection does not have a problem of contact resistance and may remain transparent, the parallelism can be visually confirmed and the parallelism can be adjusted correctly depending on the collapsed state. .
【0008】[0008]
【実施例】次に、第1の発明をCOG方式の液晶モジュ
ールに実施した例を図1により説明する。図1の(a)は
半導体素子の接続用突起の配置を示す平面図、(b)は半
導体素子の電極と基板の配線部の関係を示す断面図であ
る。半導体素子1は液晶駆動用のIC素子であって、上
下左右の各側縁に沿って一定のピッチで形成されている
電極3上に金属の接続用突起2がそれぞれ形成されてお
り、これらの電極3と接続用突起2は半導体素子1の中
心Aに対して対称的な配置となっている。これに対応し
てガラス基板4にはITOからなる透明電極5が形成さ
れており、その表面には例えば金などの薄い金属層6が
めっき等によって形成されている。半導体素子1のガラ
ス基板4への接続は、(b)図のように両者を位置合わせ
して平行に配置した後、その間に光硬化性や熱硬化性等
の接着材料(図示せず)を介在させて加圧しながら、接
着材料を硬化させることによって行われる。EXAMPLE An example in which the first invention is applied to a COG type liquid crystal module will be described with reference to FIG. 1A is a plan view showing the arrangement of connection protrusions of a semiconductor element, and FIG. 1B is a sectional view showing the relationship between the electrodes of the semiconductor element and the wiring portions of the substrate. The semiconductor element 1 is an IC element for driving a liquid crystal, and metal connection protrusions 2 are formed on electrodes 3 formed at a constant pitch along the upper, lower, left, and right side edges, respectively. The electrodes 3 and the connection protrusions 2 are arranged symmetrically with respect to the center A of the semiconductor element 1. Corresponding to this, a transparent electrode 5 made of ITO is formed on the glass substrate 4, and a thin metal layer 6 such as gold is formed on the surface by plating or the like. The semiconductor element 1 is connected to the glass substrate 4 by aligning the two as shown in (b) and arranging them in parallel, and then applying an adhesive material (not shown) such as photocurable or thermosetting material therebetween. It is performed by curing the adhesive material while interposing and pressing.
【0009】この実施例は上述のような構成であり、接
続用突起2が対称的に配置されていて加圧力が均等に加
わるので平行度が良好に保たれる。従って、ガラス基板
4に品種の異なる複数の半導体素子1を搭載する場合で
も、品種変更の都度平行度を調整することなく連続的に
作業を行うことができ、試料を点検したところ接続用突
起2はすべて同程度に潰れており、接続不良も全く発生
しないという良好な結果を得ることができた。In this embodiment, the connection projections 2 are symmetrically arranged and the pressing force is evenly applied, so that the parallelism is kept good. Therefore, even when a plurality of semiconductor elements 1 of different types are mounted on the glass substrate 4, the work can be continuously performed without adjusting the parallelism each time the type is changed. All were crushed to the same degree, and good results were obtained in that no connection failure occurred at all.
【0010】図1では接続用突起2を側縁に沿って配置
しているが、中心に対して対称であれば他の配置であっ
てもよい。図2はその一例であり、周縁だけでなく内部
にも突起2が配置されている。Although the connecting projections 2 are arranged along the side edges in FIG. 1, other arrangements may be used as long as they are symmetrical with respect to the center. FIG. 2 is an example thereof, and the protrusions 2 are arranged not only on the periphery but also inside.
【0011】次に、第2の発明を同じくCOG方式の液
晶モジュールに実施した例について説明する。図3にお
いて、接続用突起2は図1と同様に例えば金属製のもの
で電極3上に形成されており、半導体素子1の側縁に沿
って配置されているが、4箇所のコーナ部分には接続用
突起2とは別に平行度確認用突起7が設けられている。
図3の(b)に示すように、平行度確認用突起7は電気的
な接続を目的としないので半導体素子1の本体上に直接
設けられており、またガラス基板4には各接続用突起2
に対応して金属層6を有する透明電極5がそれぞれ形成
され、更に平行度確認用突起7に対応して透明電極5の
無い接着部4aが設けられている。半導体素子1のガラ
ス基板4への接続は、両者を位置合わせして平行に配置
した後、その間に光硬化性や熱硬化性等の接着材料を介
在させて加圧し、その状態で接着材料を硬化させること
によって行われ、平行度確認用突起7は接着部4aに直
接接着される。Next, an example in which the second invention is similarly applied to a COG type liquid crystal module will be described. In FIG. 3, the connection protrusions 2 are made of, for example, metal and are formed on the electrodes 3 as in FIG. 1, and are arranged along the side edges of the semiconductor element 1, but at four corners. In addition to the connection protrusion 2, a parallelism confirmation protrusion 7 is provided.
As shown in FIG. 3B, the parallelism confirmation projections 7 are not provided for electrical connection and therefore are directly provided on the main body of the semiconductor element 1, and the glass substrate 4 is provided with the respective connection projections. Two
Transparent electrodes 5 each having a metal layer 6 are formed correspondingly to, and an adhesive portion 4a having no transparent electrode 5 corresponding to the parallelism confirmation projection 7 is provided. The semiconductor element 1 is connected to the glass substrate 4 by aligning the two and arranging them in parallel, and then applying an adhesive material such as a photocurable or thermosetting material between them and pressurizing the adhesive material in that state. It is performed by curing, and the parallelism confirmation projection 7 is directly bonded to the bonding portion 4a.
【0012】この実施例は上述のような構成であり、平
行度が良好に保たれた状態で接着された場合には各平行
度確認用突起7が全く同じ状態で潰れるので、ガラス基
板4を通して潰れ具合を観察することによって平行度の
良否を確認でき、その結果から平行度を調整することも
容易である。この実施例では、第1の発明によって接続
用突起2が対称的に配置されているので平行度が良好に
保たれ、しかも平行度の確認と調整が容易であるので、
ガラス基板4に品種の異なる複数の半導体素子1を搭載
する場合に、品種変更の都度平行度を調整することなく
連続的に作業を行うことができ、接続不良が全く発生し
ないという良好な結果が得られた。This embodiment has the above-mentioned structure, and when the parallelism confirming projections 7 are crushed in exactly the same state when bonded in a state where the parallelism is kept good, the glass substrate 4 is passed through. The quality of the parallelism can be confirmed by observing the degree of collapse, and the parallelism can be easily adjusted from the result. In this embodiment, since the connecting projections 2 are symmetrically arranged according to the first aspect of the invention, good parallelism is maintained, and it is easy to check and adjust the parallelism.
When a plurality of semiconductor elements 1 of different types are mounted on the glass substrate 4, it is possible to perform work continuously without adjusting the parallelism each time the type is changed, and there is a good result that connection failure does not occur at all. Was obtained.
【0013】なお、電気的な接続を目的としている接続
用突起2の部分は透明である必要がないので、すべてに
金属層6を設けて接触抵抗や配線抵抗の低い接続を行う
ことができることになる。また、平行度確認用突起7は
本来電気的な接続を目的としていないのでその材料は導
電性である必要はないが、実際には電気的接続を目的と
する接続用突起2の形成時に同じ材料で同時に形成する
ことができる。この場合には平行度確認用突起7が導電
性であるので電気的な接続を兼ねることもできるので、
その場合は突起7は電極3上に形成され、対応する接着
部4aには金属層6の無い透明電極5が形成されること
になる。Since the connecting projections 2 for electrical connection do not need to be transparent, the metal layer 6 can be provided on all of them for connection with low contact resistance and wiring resistance. Become. Further, since the parallelism confirmation projection 7 is not originally intended for electrical connection, its material does not need to be conductive, but in reality, the same material is used when the connection projection 2 is formed for electrical connection. Can be formed simultaneously. In this case, since the parallelism confirmation projection 7 is conductive, it can also serve as an electrical connection.
In that case, the protrusion 7 is formed on the electrode 3, and the transparent electrode 5 without the metal layer 6 is formed on the corresponding bonding portion 4a.
【0014】[0014]
【発明の効果】上述の実施例から明らかなように、第1
の発明は、半導体素子に形成される接続用突起を半導体
素子の中心に対して対称に配置するようにしたものであ
り、接続用突起が片押しされないで均等に加圧力が加わ
るようになるので、基板と半導体素子との平行度を保つ
ことが容易となり、フェイスダウン方式の半導体装置に
おける接続不良をなくして歩留まりを向上することがで
きる。また第2の発明は、電極上に形成された導電性の
接続用突起とは別に半導体素子の外周部に平行度確認用
突起を設けるようにしたものであり、平行度確認用突起
が設けられる部分を透明にできるのでその潰れ具合で平
行度を目視確認することが容易となり、平行度を維持し
てフェイスダウン方式の半導体装置における接続不良を
なくし、歩留まりを向上することができる。As is apparent from the above embodiment, the first
According to the invention, the connection projections formed on the semiconductor element are arranged symmetrically with respect to the center of the semiconductor element, so that the connection projections are not pushed and the pressure is evenly applied. Therefore, it becomes easy to maintain the parallelism between the substrate and the semiconductor element, and it is possible to eliminate the connection failure in the face-down type semiconductor device and improve the yield. In the second invention, a parallelism confirmation protrusion is provided on the outer peripheral portion of the semiconductor element in addition to the conductive connection protrusion formed on the electrode, and the parallelism confirmation protrusion is provided. Since the portion can be made transparent, it is easy to visually check the parallelism by the degree of the collapse, and it is possible to maintain the parallelism and eliminate the connection failure in the face-down type semiconductor device, thereby improving the yield.
【図1】第1の発明の一実施例の平面図及び断面図であ
る。FIG. 1 is a plan view and a sectional view of an embodiment of the first invention.
【図2】他の実施例の平面図である。FIG. 2 is a plan view of another embodiment.
【図3】第2の発明の一実施例の平面図及び断面図であ
る。FIG. 3 is a plan view and a sectional view of an embodiment of the second invention.
【図4】従来例の平面図である。FIG. 4 is a plan view of a conventional example.
1 半導体素子 2 接続用突起 3 電極 4 ガラス基板 5 透明電極 6 金属層 7 平行度確認用突起 A 半導体素子の中心 1 semiconductor element 2 connection protrusion 3 electrode 4 glass substrate 5 transparent electrode 6 metal layer 7 parallelism confirmation protrusion A center of semiconductor element
Claims (2)
した配線部を有する基板上に接着材料を介在させて配置
し、位置合わせして加圧すると共に、上記接着材料を硬
化させて基板に半導体素子を実装する構造の半導体装置
において、上記接続用突起が半導体素子の中心に対して
対称に配置されていることを特徴とする半導体装置。1. A semiconductor device having a connection protrusion formed thereon is arranged on a substrate having a corresponding wiring portion with an adhesive material interposed therebetween, aligned and pressed, and the adhesive material is cured to form a semiconductor on the substrate. A semiconductor device having a structure for mounting an element, wherein the connecting projections are arranged symmetrically with respect to the center of the semiconductor element.
した配線部を有する基板上に接着材料を介在させて配置
し、位置合わせして加圧すると共に、上記接着材料を硬
化させて基板に半導体素子を実装する構造の半導体装置
において、電極上に形成された導電性の接続用突起とは
別に半導体素子の外周部に平行度確認用突起が設けられ
ていることを特徴とする半導体装置。2. A semiconductor element having a connection protrusion formed thereon is arranged on a substrate having a corresponding wiring portion with an adhesive material interposed, aligned and pressed, and the adhesive material is cured to form a semiconductor on the substrate. A semiconductor device having a structure for mounting an element, characterized in that, in addition to a conductive connecting projection formed on an electrode, a parallelism confirming projection is provided on an outer peripheral portion of the semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34541192A JP3325317B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor device used for COG type liquid crystal module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34541192A JP3325317B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor device used for COG type liquid crystal module |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06168948A true JPH06168948A (en) | 1994-06-14 |
JP3325317B2 JP3325317B2 (en) | 2002-09-17 |
Family
ID=18376419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34541192A Expired - Fee Related JP3325317B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor device used for COG type liquid crystal module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3325317B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008069044A1 (en) * | 2006-12-04 | 2008-06-12 | Sharp Kabushiki Kaisha | Semiconductor device |
-
1992
- 1992-11-30 JP JP34541192A patent/JP3325317B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008069044A1 (en) * | 2006-12-04 | 2008-06-12 | Sharp Kabushiki Kaisha | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP3325317B2 (en) | 2002-09-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6940301B2 (en) | Test pad array for contact resistance measuring of ACF bonds on a liquid crystal display panel | |
WO2007039960A1 (en) | Wiring board and display device provided with same | |
JP3649042B2 (en) | IC chip connection method and liquid crystal device manufacturing method | |
JPH06168948A (en) | Semiconductor device | |
JPH03190238A (en) | Semiconductor chip and mounting structure using same chip | |
JP2893070B2 (en) | Liquid crystal electro-optical device | |
JP3193198B2 (en) | Semiconductor element mounting method | |
JP3810064B2 (en) | Liquid crystal display | |
JP3199408B2 (en) | Liquid crystal panel mounting method, liquid crystal panel mounting structure, and liquid crystal panel mounting structure manufacturing method | |
JPH08292443A (en) | Liquid crystal display device and its production | |
JPH06130408A (en) | Liquid crystal display device | |
JPH09127536A (en) | Liquid crystal display device | |
JP2995392B2 (en) | Liquid crystal electro-optical device | |
JP3032111B2 (en) | Display device mounting structure | |
JPH04115228A (en) | Liquid crystal display device | |
JPH02181119A (en) | Liquid crystal display element | |
JPH08286201A (en) | Liquid crystal display element of flip chip system and its production | |
JPH10319419A (en) | Liquid crystal display device | |
JPH0618910A (en) | Liquid crystal display device | |
JP2995390B2 (en) | Liquid crystal electro-optical device | |
JP2705693B2 (en) | Substrate connection structure and liquid crystal device | |
JPH0481723A (en) | Liquid crystal panel | |
JPH11249583A (en) | Display | |
JP2000068694A (en) | Mounting method of electronic part and pressure-bonding device | |
JP2504106B2 (en) | Liquid crystal display |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080705 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 6 Free format text: PAYMENT UNTIL: 20080705 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 7 Free format text: PAYMENT UNTIL: 20090705 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090705 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 8 Free format text: PAYMENT UNTIL: 20100705 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100705 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20110705 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20120705 |
|
LAPS | Cancellation because of no payment of annual fees |