JPH06168589A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To obtain a technique for reducing a bit line noise without lowering a memory access speed. CONSTITUTION:This storage is provided with plural memory mats MM mat divided and a bit line 2 capable of reading data in a memory cell 4. A complementary bit line pair is formed by the corresponding bit line 2 between the memory mats MM different from each other, and the same sense amplifier 1 is shared by the complementary bit line pair, and the memory cell 4 is arranged so that the bit line adjacent to the bit line activated in a read cycle becomes an inactive state in the same read cycle. Thus, cross talk between bit lines 2 each other are reduced, and the bit line noise is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a technique for improving noise resistance of bit lines in the semiconductor memory device, which is effective when applied to, for example, a DRAM (dynamic random access memory). Related technology.

[0002]

2. Description of the Related Art In a semiconductor memory, a large number of complementary bit line pairs coupled to input / output terminals of matrix-arranged memory cells are regularly arranged with a minimum interval, and an insulating film is provided between the bit lines. Intervened. Therefore, capacitive coupling occurs between the adjacent bit lines, and a negative desired capacitance component is parasitic. Up to the conventional 4MDRAM, the bit line pitch is 5 μm or more, and the coupling between bit lines has not been a particular problem. However, in 16M DRAM, the bit line pitch is reduced to 3 μm, and malfunctions and data destruction due to coupling noise between bit lines have become a problem. In the DRAM, when the word line is selected, the transfer MOS is turned on, and the charge in the charge storage section is transmitted to the bit line as a minute signal. This minute signal is about 140 mV, which is very small. At this time, this minute signal is inverted by the coupling noise between the bit lines, and the data is destroyed. Conventional techniques for preventing this include a bit line cross method and an SRL method.

In the bit line cross system, "H. Hide
ko et al. "Twisted Bit lin
e Architectures for Megab
itDRAM'S "IEEE T, S, S, C, Vo
l. 24 No. 1 P21 (1989) ", the complementary bit lines are crossed to equalize the coupling noise between the complementary bit lines. According to this, since the same amount / in-phase noise is put on the complementary bit lines, the difference in the signal amount of the complementary bit lines does not change.

Further, in the SRL system, "K.
ick et al. "The Stabilized
Reference-Line (SRL) Tec
Knique for Scaled DRAM "19
89 Symposium on VLSI Curcui
2 intersection DRA as described in ts P99 "
In M, the level of the reference bit line is set to a half voltage (1/1 of the power supply voltage Vcc for a predetermined time during word line driving).
2) By fixing the level, the coupling noise from the adjacent bit pair and the coupling between the same pairs are prevented.

[0005]

However, since the coupling noise between the complementary bit line pair, that is, the same pair bit line cannot be reduced in the above-mentioned bit line crossing method, it is expected that the semiconductor integrated circuit will be highly integrated and miniaturized in the future. There is a possibility that memory cell data will be destroyed as the number of memory cells increases.

Further, in the SRL system, it is possible to reduce the coupling noise from the adjacent pair bit lines and the coupling noise between the same pair bit lines, but since the reference bit line is fixed to the half voltage level after the word line is selected. Since it is necessary to release the bit line precharge by turning off the MOSFET of
Due to the FET operation control and timing control, the memory access speed is delayed accordingly.

An object of the present invention is to provide a technique for reducing bit line noise without reducing the memory access speed.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of memory mats each including a plurality of memory cells and a bit line for reading data from the memory cells are included, and complementary bit lines are provided by corresponding bit lines between different memory mats. When a pair is formed and the same sense amplifier is shared by the pair of complementary bit lines, the bit line adjacent to the bit line activated in the read cycle becomes inactive in the same read cycle. The memory cells are arranged in the memory cell. At this time, every other bit line of the same memory mat, the sense amplifiers corresponding to the bit line can be dispersedly arranged on both sides of the memory mat. In order to reduce the number of sense amplifiers, a plurality of adjacent bit lines of the same memory mat share the same sense amplifier, and the plurality of bit lines are selectively coupled to the sense amplifier. It is advisable to provide a selection circuit.

[0011]

According to the above means, deactivating the bit line adjacent to the active bit line acts so that the inactive bit line in the read cycle shields the active bit line. Achieves noise reduction on the bit line and reduces the noise on the inactive bit line by the conventional SRL
The memory access delay is eliminated by eliminating the need for operations such as releasing the bit line precharge and timing control as in the method.

[0012]

FIG. 4 shows a DRAM which is an embodiment of the present invention. Although not particularly limited, the DRAM shown in the figure is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

In FIG. 4, reference numeral 24 is a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction, and data terminals of the memory cells are connected in each column direction. Coupling to complementary data lines. Each complementary data line is commonly connected to the complementary common data line via a Y selection switch circuit 27 including a plurality of column selection switches which are coupled to the complementary data line in a one-to-one relationship.

Although not particularly limited, the DRAM of this embodiment adopts the address multiplex system, and the row and column address input signals are fetched from a common address terminal by shifting their timings. That is, the X address latch and X decoder 22
An address multiplexer 21 is arranged in front of the Y address latch and Y decoder 26, and an address signal taken in through the address buffer 20 is converted into an X address latch and X decoder 22 by the address multiplexer 21 and a Y address latch and It is distributed to the Y decoder 26. In order to smoothly perform such address input, two types of clock signals, RAS * (row address strobe) and CAS * (column address strobe), are applied from the outside. In addition, "*" means a low active signal.

Since only one read or write operation is possible during one memory cycle (one cycle of the RAS * clock), the row address is set at the falling point of the RAS * clock and the row address is set at the falling point of the CAS * clock. The column address is taken in by the internal circuit, and it is possible to judge whether the relevant cycle is a write cycle or a read cycle depending on the state of the write enable signal WE *. The control unit 25 performs such determination and operation control of each unit.

The word driver 23 drives the word line to the selection level based on the decoding of the X address latch and the X decoder arranged in the preceding stage. Then, the Y selection switch circuit 27 is driven based on the Y address latch and the decoded output of the Y decoder 26, thereby enabling data read or data write from the specified memory cell. In addition, the memory cell array 24
A sense amplifier 1 is coupled to the sense amplifier 1, and the memory cell data is amplified by the sense amplifier 1. In this case, the data input / output circuit 28 includes a main amplifier and the like, and the read data can be externally transmitted via the main amplifier.

FIG. 1 shows a detailed structure of a main part of the DRAM.

The memory cell array 24 has a plurality of memory mats MM divided into mats, one of which is shown in FIG. As shown in the figure, one memory mat MM includes a plurality of dynamic type memory cells 4. Reference numeral 3 in the drawing denotes a plurality of word lines, and the word line 3 is alternatively driven to the selected level by the word driver 23. A plurality of bit lines 2 are arranged so as to intersect the plurality of word lines 3, and the memory cells 4 are arranged at the intersections thereof. However, the memory cells 4 are not arranged at all the intersections of the word lines 3 and the bit lines 2, but the bit lines adjacent to the bit lines activated in the read cycle are
The memory cells 4 are arranged at every other intersection so that they are inactivated in the same read cycle. Incidentally, 10 is a dummy word line.

Further, a plurality of sense amplifiers 1 are provided corresponding to a plurality of bit lines 2, and in the present embodiment, the sense amplifiers 1 corresponding to every other bit line are dispersedly arranged on both sides of the memory mat MM. Has been done. That is, FIG.
In, a memory mat MM including a plurality of memory cells 4
The first sense amplifier group SA1 is arranged on the left side of the memory mat, and the second sense amplifier group S1 is arranged on the right side of the memory mat MM.
A2 is arranged.

Here, the first sense amplifier SA1 and the second sense amplifier SA1
The sense amplifier SA2 is operated in a complementary manner. That is, the sense amplifier group operated in one cycle is the first
Only one of the sense amplifier SA1 and the second sense amplifier SA2. Such control is performed by turning on the sense amplifier driving MOSFET included in the sense amplifier.
Enabled by off control. Multiple sense amplifiers 1
Has two terminals, one of which is coupled to a corresponding bit line 2 and the other of which is coupled to a corresponding bit line of an adjacent memory mat (not shown). That is,
In this embodiment, the sense amplifier 1 and the bit line 2 are coupled to each other by a so-called one-intersection method, and one sense amplifier 1 is connected.
The complementary input signal to the pair is not the pair of adjacent bit lines in FIG. 1 but one bit line shown in FIG. 1 and a corresponding bit line in an adjacent memory mat (not shown). That is, the complementary bit line pair is formed between different memory mats adjacent to each other. Therefore, in the memory mat MM, when one word line 3 is driven to the selection level, the bit line corresponding to the memory cell 4 coupled to the word line is activated. In other words, every other bit line is activated in the memory read cycle,
In the read cycle, the bit line adjacent to the activated bit line is always inactivated.

The half voltage generation circuit 6 is a circuit for generating a half voltage for precharging the bit line 2 to a potential half the power supply voltage VCC, and the voltage generated by the circuit 6 is: Multiple precharge MOS
It is adapted to be applied to the bit line 2 via the FETs 11A and 11B. Precharge MOSFET 11A
Is arranged on the first sense amplifier SA1 side, and the precharge MOSFET 11B is arranged on the second sense amplifier SA2 side. The precharge control signals 5A and 5A, respectively.
It is turned on when B is asserted, so that the corresponding bit line 2 is precharged. The precharge control signals 5A and 5B are generated by the control circuit 25. The bit line is always fixed to the half voltage during the inactive state. Since every other bit line is activated as described above, the bit line adjacent to the bit line activated by the same memory mat MM is always fixed to the half voltage in the memory read cycle.
As a result, the activated bit line is shielded by the inactive bit line.

FIG. 3 shows a detailed structure of a main part of the memory cell array 24.

In FIG. 3, reference numeral 15 is a capacitance storage node capable of holding data, 17 is a diffusion layer, and 18 is a plate. A contact hole 16 for connecting different wiring layers is provided, and the bit line 2 and the diffusion layer 17 are connected by this contact hole 16. The capacitance storage node 15 is formed at the intersection of the word line 3 and the bit line 2, and the memory cell 4 is formed thereby.

According to the above embodiment, the following operational effects can be obtained.

(1) In the conventional bit line cross method, the coupling noise between the same pair cannot be erased. Therefore, the memory cell data is destroyed as the degree of integration and miniaturization of the semiconductor integrated circuit progresses. On the other hand, according to the above-described embodiment, a plurality of memory mats M including a plurality of memory cells 4 are divided into mats.
M and a bit line 2 that allows the data in the memory cell 4 to be read, and a corresponding bit line 2 between different memory mats MM forms a complementary bit line pair and the complementary bit line pair has the same sense. By arranging the memory cell 4 so that the amplifier 1 is shared and the bit line adjacent to the bit line activated in the read cycle becomes inactive in the same read cycle, the inactive bit line The active bit line is shielded by, thereby reducing crosstalk between the bit lines 2 and suppressing noise generation.

(2) Further, in the conventional SRL method, after the word line is selected, the operation for turning off the MOSFET for fixing the reference bit line to the half voltage level and the timing control are required, which results in the memory access. Although the speed becomes slower, according to the above embodiment, since the inactive bit line acting as the shield is not operated in the read cycle, the bit line precharge is released after the word line is selected for the inactive bit line. No operation or timing control is required, and the memory access speed is not delayed in obtaining the effect of (1) above.

(3) Further, in the bit line cross system, the chip area is increased by the bit line cross, but in the case of this embodiment, the chip size is the same as that of the conventional DRAM, and the above (1), (2) There is no demerit in terms of chip area in obtaining the effect of.

FIG. 2 shows another embodiment of the present invention.

In FIG. 2, a MOSF for precharging a bit line is provided between the memory mat MM and the sense amplifier 1.
An ET group 11 and a selection circuit 12 are arranged. In the configuration of FIG. 2, in the memory mat MM, the same sense amplifier is shared by a pair of adjacent bit lines,
The selection circuit 12 selectively couples the set of bit lines to the sense amplifier 1. This selection circuit 1
2 is formed by a plurality of MOSFETs arranged corresponding to the bit line 2, as indicated by Q1 to Q6.

The MOSFETs Q1, Q3 and Q5 are also driven by the selection control signal 9A being asserted.
The SFETs Q2, Q4, Q6 are turned on by the selection control signal 9B being asserted, whereby the corresponding bit line 2 is selectively coupled to the sense amplifier 1. By sharing the sense amplifiers in this way, it suffices to arrange the sense amplifiers 1 at a ratio of one to two adjacent bit lines. As a result, the number of sense amplifiers 1 is larger than that in the above-described embodiment. It is set to 1/2.

As described above, the same sense amplifier is shared by a pair of bit lines adjacent to each other, and the selection circuit 12 for selectively coupling one set of bit lines to the sense amplifier 1 is a memory. In order to accurately precharge the bit line 2 when it is arranged between the mat MM and the sense amplifier 1, a MOSFET group 11 for precharge is arranged between the memory mat MM and the selection circuit 12, and the read operation is performed. In a cycle, the precharge MOSFET connected to the activated bit line is turned off before selecting one word line, and the corresponding bit line is electrically disconnected from the half voltage generation circuit 6. . On the other hand, the precharging MOSF coupled to the inactive bit line
The ET is kept in the ON state even during operation, so that the bit line is fixed to the half voltage level in the read cycle.

The structure and arrangement of the memory mat MM and the memory cells 4 included therein are the same as those in the above-described embodiment, and a plurality of bit lines adjacent to the bit line to be activated are inactivated. Since the bit line 2 is arranged, the active bit line is shielded by the inactive bit line, which reduces crosstalk between the bit lines 2 and suppresses noise generation. Since the inactive bit line acting as the shield is not operated in the cycle, a MOS for fixing the reference bit line to the half voltage level after selecting the word line as in the SRL system.
By turning off the FETs, operations such as releasing the bit line precharge and timing control are unnecessary,
No delay in memory access speed.

Further, in this embodiment, the same sense amplifier is shared by a pair of adjacent bit lines,
Since the pair of bit lines is selectively coupled to the sense amplifier 1 by the selection circuit 12, adjacent two
It suffices to arrange the sense amplifiers 1 at a ratio of one to one bit line, and as a result, the number of sense amplifiers 1 is halved as compared with the case of the above embodiment, and the number of sense amplifiers should be reduced. There is a unique effect that you can.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the DRAM adopting the address multiplex system has been described, but the row address and the column address may be taken in from separate input terminals. Further, the number of divisions of the memory mat, the number of word lines and bit lines, the number of memory cells, etc. can be appropriately changed.

In the above description, the invention made by the present inventor is the field of application behind the invention, which is the DRA.
Although the case where the present invention is applied to M has been described, the present invention is not limited thereto, and for example, a flash RAM, an E
It can be widely applied to various semiconductor memory devices such as PROM and EEPROM, and further to data processing devices including the same.

The present invention can be applied on the condition that at least a plurality of bit lines are included.

[0038]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of memory mats and a bit line for reading the data of the memory cell are included. Corresponding bit lines between different memory mats form a complementary bit line pair, and the complementary bit line pair is used. When the same sense amplifier is shared, the bit line adjacent to the bit line activated in the read cycle and the memory cell are arranged so as to be inactive in the same read cycle. Since the adjacent bit line is made inactive, the active bit line is shielded by the inactive bit line in the read cycle, and the noise of the bit line is reduced. Further, since the inactive bit line acting as a shield is not operated in the read cycle, it is not necessary to perform an operation or timing control such as releasing the bit line precharge after selecting the word line for the inactive bit line. In obtaining the noise reduction effect, the memory access speed is not delayed.

[Brief description of drawings]

FIG. 1 is an electrical connection diagram showing a configuration of a main part of a DRAM according to an embodiment of the present invention.

FIG. 2 is an electrical connection diagram showing a configuration of a main part of a DRAM according to another embodiment of the present invention.

FIG. 3 is a plan view of a main part of a memory cell array included in the DRAM.

FIG. 4 is an overall configuration block diagram of the DRAM.

[Explanation of symbols]

 1 Sense Amplifier 2 Bit Line 3 Word Line 4 Memory Cell 6 Half Voltage Generation Circuit 11 Precharge MOSFET 11A Precharge MOSFET 11B Precharge MOSFET 12 Selection Circuit 15 Capacitive Storage Node 16 Contact Hole 17 Diffusion Layer 18 Plate 20 Address Buffer 21 address multiplexer 22 X address latch and X decoder 23 word driver 24 memory cell array 25 control circuit 26 Y address latch and Y decoder 27 Y selection switch circuit 28 data input / output circuit

Claims (4)

[Claims] 1. A plurality of memory mats including a plurality of memory cells and formed by mat division, and a bit line capable of reading data of the memory cells, and complementary bits by corresponding bit lines between different memory mats. A pair of lines is formed and the same sense amplifier is shared by the pair of complementary bit lines, and a bit line adjacent to a bit line activated in a read cycle becomes inactive in the same read cycle. A semiconductor memory device characterized in that the memory cells are arranged as described above. 2. The semiconductor memory device according to claim 1, wherein every other bit line of the same memory mat, sense amplifiers corresponding to the bit line are dispersedly arranged on both sides of the memory mat. 3. The same sense amplifier is shared by a plurality of adjacent bit lines of the same memory mat, and a selection circuit for selectively coupling the plurality of bit lines to the sense amplifier is arranged. Item 2. The semiconductor memory device according to item 1. 4. The semiconductor memory device according to claim 1, wherein said bit line is fixed to a predetermined precharge level when inactive.