JPH06165117A - Reproducing device - Google Patents

Abstract

PURPOSE:To always obtain a fine reproduced picture independently of the status of a reproduced signal. CONSTITUTION:Memories 31, 32 are connected to memories 21, 22 in series. A frame identification(ID) signal and a track number are written in each signal. Data other than the ones disabled to be corrected by an error correcting circuit 6 are distributed based upon their frame ID signals and written in the memories 21, 22, the track numbers of the signals are detected, and when 2nd subsequent tracks are stored in the succeeding frame of one memory, the completion of data storage in the other memory is judged. Data of the memory 21 or 22 completing the storage are burst-like transferred to the memory 31 or 32. Data in the memory 31 or 32 are repeatedly read out, a synchronous signal is added to the data by a synchronous signal adding circuit 12, the signal is converted into an analog signal by a D/A conversion circuit 13, and the analog signal is outputted from an output terminal 14 to execute slow reproduction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a consumer digital V
The present invention relates to a reproducing device for a digital video signal in which one frame such as TR is divided into a plurality of tracks and recorded.

[0002]

2. Description of the Related Art For example, in a consumer digital VTR, a segment recording system is adopted, and one frame is divided into 10 tracks for recording. As such a consumer digital VTR reproducing device, for example, a device as shown in FIG. 5 is considered.

That is, in the figure, the reproduction RF data reproduced by the head 1 is amplified to a proper level by the reproduction amplifier 2 and then converted into a digital signal by the decoding circuit 3. The converted digital signal is supplied to the ID detection circuit 4, and the frame identification signal and the ID such as the track number in the signal are detected. The detected ID is stored in the first frame memory 5 as a reference of the write address. Written.

The frame memory 5 is equivalent to one frame (1
It has a capacity to store 0 tracks), and one of its roles is to make the read phase constant regardless of the phase of the digital signal to be written. This operation is executed by reading the digital signal written on the basis of the ID on the basis of the address of a fixed cycle synchronized with the subsequent stage.

The digital signal read from the frame memory 5 is written in the second frame memory 9 through the error correction circuit 6, the deframing circuit 7 and the inverse DCT conversion circuit 8. At this time, since writing to the frame memory 9 is synchronized with the frame after reading from the frame memory 5, writing is performed on the basis of an address of a fixed cycle. Further, the read is also performed on the basis of the address of the same fixed cycle. This also applies to the two sets of field memories 10 and 11 in the subsequent stage.

The frame memory 9 has a capacity for one frame, and its main role is to return the digital signal processed in the frame to the field. That is, the digital signal processed by the inverse DCT conversion circuit 8 is in a state in which it can be decomposed into odd and even fields.
Therefore, at the time of reading, it is divided into two systems of odd and even fields, and writing destinations are respectively field memories 10 and 11.
Return to the field by dividing into.

Further, the role of the field memories 10 and 11 is to return the shuffling. That is, the original image is returned to the original sequence by performing it at the time of writing and reading it in order. Then, a sync signal is added to the signals read from the field memories 10 and 11 by the sync addition circuit 12, converted into an analog signal by the D / A conversion circuit 13, and output from the output terminal 14. In this way, the reproduction of the digital video signal is performed.

By the way, in such a reproducing apparatus, so-called slow reproduction is being considered by setting the reproducing speed lower than that at the time of recording. In that case, in the above segment recording, the reproduced image cannot be output unless all 10 tracks are reproduced. Therefore, it is possible to perform slow reproduction by sequentially accumulating the extracted reproduction signals in a memory and reading them out in bursts when one frame is completed.

In that case, for example, the following method can be considered for determining the time point when the above-mentioned one frame is completed.
1) When the last data of the currently accumulated frame is taken out. 2) When the data of the frame next to the currently stored frame is taken out.

However, among these methods, for example, the method 1) may not be able to determine the time point when the last data is lost due to dropout or the like. In the method 2), the next frame may be taken out before the last data of the stored frame is taken out in good condition. Therefore, in these cases, there is a possibility that a good reproduced image cannot be obtained. This application is made in view of such a point.

[0011]

The problem to be solved is that in the conventional technique, it may not be possible to obtain a good reproduced image depending on the state of the reproduced signal.

[0012]

According to a first means of the present invention, in a reproducing apparatus for a digital video signal in which one frame is divided into a plurality of tracks and recorded, reproduction is performed at a reproduction speed lower than that at the time of recording. In this case, the reproduced signal is stored in the memories 21 and 22, and when the accumulation of one frame is completed, the next process is executed, and the frame identification signal and the track number in the reproduced signal are detected. The reproducing apparatus is characterized in that it is determined that the storage in the memory is completed when the second track and subsequent tracks of the next frame in the reproduction order are reproduced.

According to a second means of the present invention, the memory is provided with two sets (21, 22), each of which stores one frame and the next frame identified by the frame identification signal, The reproducing apparatus according to the first means is characterized in that when the second and subsequent tracks of the next frame are accumulated on one side, it is judged that the accumulation on the other side is completed.

According to the third means of the present invention, each of the two sets of memories 21 and 22 has a capacity of one field, and the odd and even fields in the reproduced signal are discriminated and predetermined. The second feature is that only the reproduction signal of the field of
It is a reproducing apparatus described in the means.

In the fourth means according to the present invention, the two sets of memories 21 and 22 are used by dividing one set of one frame memory 9 for use. Is.

[0016]

According to this, when the second and subsequent tracks of the next frame in the reproduction order are reproduced, it is judged that the accumulation of the previous frame in the memory is completed, and thus the state of the reproduction signal is irrelevant. Therefore, a good reproduced image can always be obtained.

[0017]

EXAMPLE In FIG. 1, two sets of memories 21 and 22 are provided in place of the above-mentioned memory 9. Furthermore these memories 2
The memories 31 and 32 corresponding to the above-mentioned memories 10 and 11 are directly arranged with respect to 1 and 22, respectively.

In this apparatus, the format of the signal taken out by the head 1 and read out from the first frame memory 5 is as shown in FIG. 2, for example. That is, the drawing corresponds to the recording format of one track. In this figure, 147 sync blocks are provided in one track, and a reproduced image of one frame can be obtained with 10 tracks = 1470 sync blocks. Each of these sync blocks is composed of a sync ID and data, and a frame identification signal and a track number are written in this sync ID.

Therefore, in the above-mentioned two sets of memories 21 and 22, data excluding those which cannot be corrected by the error correction circuit 6 is distributed by the frame identification signal and written. At the same time, the track number is detected, and, for example, when one memory 21 (22) stores the second and subsequent tracks of the next frame, the other memory 22 (21).
It is judged that the storage of data in the is completed.

Then, according to this judgment, the data in the memory 21 or 22 whose storage has been completed is transferred to the memory 31 or 32 in a burst manner. At this time, shuffling return processing is performed. After that, the data in the memory 31 or 32 is repeatedly read, and the sync addition circuit 1
A sync signal is added at 2 and converted into an analog signal by the D / A conversion circuit 13 and output from the output terminal 14, whereby slow reproduction is performed.

That is, in this apparatus, for example, when writing is performed from the memory 21 during forward slow reproduction, when the second and subsequent tracks of the memory 22 are written as shown in FIG. 21 to memory 31
The transfer is done in bursts. When writing is performed from the memory 22, burst transfer is performed from the memory 22 to the memory 32 when the second and subsequent tracks of the memory 21 are written as shown in B of FIG.

Alternatively, the memory 2 can be used during slow playback in the reverse direction.
When the writing is performed from 2, when the second and subsequent tracks from the bottom of the memory 21 are written as shown in FIG. 4A, the burst transfer from the memory 22 to the memory 32 is performed. In addition, when writing is performed from the memory 21, as shown in B of the same drawing, when the second track and later from the bottom of the memory 22 are written, burst transfer is performed from the memory 21 to the memory 31.

Therefore, in this device, even if the last data is lost due to a dropout or the like, the second frame of the next frame is lost.
Since the determination is made when the tracks after the track are accumulated, there is no fear that the determination cannot be made. Further, when the second and subsequent tracks of the next frame are accumulated, the last data of the previous accumulated frame has been taken out, and there is no fear that the next frame will be taken out before taking out in a good state. .

Thus, according to the above apparatus, when the second and subsequent tracks of the next frame in the reproduction order are reproduced, it is judged that the accumulation of the previous frame in the memory is completed, and the reproduction signal is reproduced. Regardless of the state, a good reproduced image can always be obtained.

In the above device, two sets of memories 2
Each of 1 and 22 may have a capacity of one field, and odd and even fields in the reproduction signal may be discriminated and only the reproduction signal of a predetermined field may be accumulated. In that case, the two sets of memories may be used by dividing one set of one frame memory.

[0026]

According to the present invention, when the second and subsequent tracks of the next frame in the reproduction order are reproduced, it is judged that the accumulation of the previous frame in the memory is completed, and the reproduction signal is reproduced. Regardless of the condition, it is now possible to always obtain good playback images.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a reproducing apparatus according to the present invention.

FIG. 2 is a diagram for explaining an example of the recording format.

FIG. 3 is a diagram for explaining an example of the operation of the memory.

FIG. 4 is a diagram for explaining another example of the operation of the memory.

FIG. 5 is a block diagram of a conventional playback device.

[Explanation of symbols]

 1 head 2 reproduction amplifier 3 decoding circuit 4 ID detection circuit 5 frame memory 6 error correction circuit 7 deframing circuit 8 inverse DCT conversion circuit 12 sync addition circuit 13 D / A conversion circuit 14 output terminal 21, 22 memory 31, 32 memory

Claims (4)

[Claims] 1. In a reproducing apparatus for a digital video signal in which one frame is divided into a plurality of tracks and recorded, when the reproduction speed is set lower than that at the time of recording, the reproduction signal is stored in a memory and When the accumulation of the frame is completed, the next process is executed, the frame identification signal and the track number in the reproduction signal are detected, and the second and subsequent tracks of the next frame are reproduced in the reproduction order. At this time, the reproducing apparatus is characterized in that it is determined that the storage of the memory is completed. 2. The memory is provided with two sets, each of which stores one frame and the next frame identified by the frame identification signal, and one of which stores the second and subsequent tracks of the next frame. The reproducing apparatus according to claim 1, wherein, when the reproduction is performed, it is determined that the other accumulation has been completed. 3. The two sets of memories each have a capacity of one field, and odd and even fields in the reproduction signal are discriminated and only the reproduction signal of a predetermined field is stored. The reproducing device according to claim 2, wherein 4. A reproducing apparatus according to claim 3, wherein said two sets of memories divide and use one set of one frame memory.