JPH06163914A - Ferroelectric memory element and driving method therefor - Google Patents

Abstract

PURPOSE:To provide a ferroelectric element excellent in durability and exhibiting stabilized operation while allowing high integration. CONSTITUTION:The ferroelectric memory element comprises a substrate 1 made of a bulk semiconductor material having one conductivity type, an impurity region 2 of the opposite conductivity type formed on the surface layer of the substrate, a dielectric film 3 formed on the impurity region 2, a lower electrode 4 formed on the dielectric film 3, a ferroelectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the ferroelectric film 5 wherein driving voltage is applied, respectively, to an integrated impurity region, i.e., a ferroelectric memory element, the lower electrode 4, and the upper electrode 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device and its driving method. More specifically, the present invention relates to a ferroelectric memory element that changes the amount of carrier movement in an impurity region through electrostatic induction by spontaneous polarization of a ferroelectric film, and a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory element used in a computer or the like, a ROM (Read O
nly Memory), PROM (Program
Able ROM), EPROM (Erasable)
PROM), EEPROM (Electrically)
EPROM) and the like, and in particular, EEPROM is promising because the stored contents can be electrically rewritten.

In this EEPROM, MIS (M
etal-Insulator-Semiconduc
(tor) A method is known in which a trap region in a gate insulating film of a field effect transistor or a floating gate is charged by charge injection from a silicon substrate and the surface conductivity of the substrate is modulated by the electrostatic induction.

On the other hand, a method utilizing spontaneous polarization of a ferroelectric substance has been considered as a non-volatile memory having a method completely different from that of the EEPROM. Ferroelectrics are PZT (lead zirconate titanate), PbTiO ₃ (lead titanate), Ba
Oxides such as TiO ₃ (barium titanate) are mainly used, and P is the most promising non-volatile memory material at present.
ZT is being actively researched. As the base electrode of the PZT thin film, a Pt (platinum) electrode is often used in consideration of oxidation resistance and lattice matching.

Further, there are two kinds of structures in the method using the ferroelectric film, which are a capacitor structure and an MF, respectively.
S (Metal-Ferroelectric-Sem
icon) -FET (Field-Eff)
It is called an ect-Transistor) structure.

The capacitor structure has a structure in which a ferroelectric film is sandwiched between electrodes, and information is read out by detecting the presence or absence of a reversal current due to polarization reversal of the spontaneous polarization of the ferroelectric. On the other hand, the MFS-FET structure is MIS-FE
The gate insulating film of T is a ferroelectric film, and the charge of the semiconductor surface is compensated by the electric charge induced on the semiconductor surface so as to compensate the spontaneous polarization according to the direction and the size of the spontaneous polarization of the ferroelectric material. Information is read by utilizing the fact that the electric conductivity is modulated.

[0007]

However, in a device utilizing the tunnel effect of electrons, a large electric field is required for charge injection from the silicon substrate, or traps are generated in the SiO ₂ insulating film. Then, there was a problem that the number of rewrites was limited. Further, in the capacitor structure, since the ferroelectric film is formed on the Pt electrode or the like, it is easy to obtain a relatively good film quality. Currently, vigorous development is underway toward commercialization. Since the stored information is destroyed, the information has to be rewritten again after reading. In the MFS-FET structure, non-destructive reading that does not destroy information at the time of reading is possible, but since the ferroelectric film is formed directly on the silicon semiconductor, the interface state density is difficult to determine, and an oxide film is formed on the semiconductor surface. There is also a problem that it is difficult to manufacture a stable element because of a problem that it is formed.

In order to solve such a problem, the MFS-
In the FET structure, a structure in which a dielectric thin film is formed between the lower electrode and the semiconductor surface has been proposed (JP-A-49-49).
131646). According to this structure, the lower electrode functions as a floating gate electrically insulated by the silicon substrate.

In this structure, however, a voltage is applied only to the upper electrode in order to invert the spontaneous polarization of the ferroelectric film, so that a voltage pulse of both positive and negative polarities of ± V _r is required when the inversion voltage is V _r. , The circuit configuration becomes complicated, the spontaneous polarization of the ferroelectric becomes unstable due to the electrically unstable floating gate, and the normal operation is impaired, and the voltage applied to the ferroelectric film is However, since the upper electrode and the lower electrode are asymmetric, there is a problem that the durability against repeated polarization inversion deteriorates.

Further, in the MFS-FET structure, in order to form a single cell, the source, drain, and gate regions must be formed separately from each other, so that there is a limit to the improvement in the degree of integration. there were.

[0011]

Thus, according to the present invention, a substrate made of a bulk semiconductor material of one conductivity type and a conductivity type opposite to the substrate formed on the surface layer of the substrate. An impurity region, a dielectric film formed on the impurity region, a lower electrode formed on the dielectric film,
A ferroelectric memory comprising a ferroelectric film formed on the lower electrode and an upper electrode formed on the ferroelectric film, wherein the impurity region is an integrated region. An element is provided. Further, according to the present invention, there is provided a method of driving a ferroelectric memory element, characterized in that a driving voltage is applied to each of the lower electrode and the upper electrode.

The ferroelectric memory element of the present invention will be described with reference to FIG. The substrate used is not particularly limited as long as it is a semiconductor material, but a silicon substrate or the like is preferable. Further, an impurity region 2 having a conductivity type opposite to that of the substrate is formed in the surface layer of the n-type or p-type conductivity type substrate.
As implantation ions for forming this impurity region 2,
When the p-type conductive region is used, for example, boron or the like is used,
When the n-type conductive layer is used, P, As, etc. may be mentioned. Such an ion is 40 to 80 KeV, 1 × 10 ¹³ to 1 ×
After implanting ions at a concentration of about 10 ¹⁵ ions / cm ^2, annealing is performed in a reducing atmosphere at 600 to 1300 ° C. for about 5 minutes to 1 hour to obtain a depth of 0.02 to 0.3.
The integrated impurity region 2 of μm can be formed. The impurity region 2 thus formed does not have a structure in which the source, drain and gate regions are separated from each other, unlike the conventional ferroelectric memory element, so that the manufacturing is simple and the yield can be improved.

The dielectric film 3 formed on the impurity region 2 can be formed using SiO ₂ , Si ₃ N ₄ or the like, and is preferably a SiO ₂ film. This SiO ₂ film can be formed by a known method, for example, thermal oxidation at 1000 to 1200 ° C., a CVD method, or an RF sputtering method, and its film thickness is about 0.1 to 10 μm.

Next, the lower electrode 4 is formed on the dielectric film 3. As a material used for the lower electrode 4, for example, Al, Pt, or another metal that is normally used as an electrode can be used. These metals are known in the art, for example, a sputtering method using a metal target, a CVD method, or It can be formed by a vapor deposition method or the like, and the film thickness thereof is preferably about 0.1 to 10 μm.

Further, a ferroelectric film 5 is formed on the lower electrode 4, and an upper electrode 6 is further formed on the ferroelectric film 5. As the ferroelectric film 5, lead zirconate titanate (PZT),
PLZT and the like can be mentioned. For this ferroelectric film 5, for example, when PZT is used, Pb (DPM) ₂ , Zr (DPM) ₄ and Ti (i-C ₃ ) are formed by MOCVD.
H ₇ ) ₄ or the like is preferably used to form a film having a thickness of 0.1 to 10 μm. Further, the upper electrode 6 can have the same configuration as the lower electrode 4.

The impurity region 2 and the back surface of the substrate are respectively provided with
Ohmic electrodes (9, 10 and 13) are formed. Oh
Ohmic electrodes (9, 10 and 13), lower electrode 6 and upper
Lead wires (11, 1, 1) are applied to the partial electrodes 4 as voltage applying means.
2, 14, 7 and 8) are connected. Further lead wire
The voltage V is applied to 11, 12, 7 and 8 respectively_D, V_S, V
_G1And V _G2Is applied.

The operation of this device is as follows. That is, while maintaining V _G2 at ground, add V _G1 to -V _CC
When V _G1 is floated after the application of the pulse of, the ferroelectric film 5 is polarized downward and the silicon oxide film 3 is also dielectrically polarized due to this electrostatic induction. When the electrodes 9 and 10 are electrically connected to each other and -V _CC is applied to V _D , the drain current I _D flows and the device is turned on.

Next, while maintaining V _G1 at ground, V _G2
When a pulse of V _CC is applied and then V _G1 is floated, the ferroelectric film 5 is polarized upward and the dielectric film 3 is also dielectrically polarized due to this electrostatic induction, and an inversion layer is formed in the impurity region 2. Although formed, the doping depth of the impurity region 2 is such that the inversion layer reaches the substrate. Therefore, the portion of the impurity region 2 covered with the silicon oxide film 3 is in a depleted state depleted of carriers. Therefore, the electrodes 9 and 10 are not electrically connected to each other, and even if -V _CC is applied to V _D , the drain current I _D
Does not flow and the device is in the "OFF" state. Since the dielectric polarization of this dielectric film 3 is maintained as long as the polarization of the ferroelectric film 5 is maintained, it can be operated as a non-destructive and readable nonvolatile memory. Further, according to this element structure, the source, drain, and gate regions are integrated and have the same conductivity type, so that high integration is possible.

[0019]

EXAMPLE A ferroelectric memory element of the present invention was manufactured as follows. On the front surface of the n-type silicon substrate 1 having the Al electrode 13 formed on the back surface by the sputtering method, 150 KeV,
By implanting B at 1 × 10 ¹⁶ ions / cm ² and annealing at 1000 ° C., a p ⁺ -type integrated impurity region 2 was formed. The depth of this impurity region 2 is 0.
It was 35 μm. Al electrodes 9 and 10 having a film thickness of 0.5 μm were formed on both ends of the impurity region 2 by a sputtering method.

Next, a silicon oxide film 3 having a film thickness of 100 nm is formed as a dielectric film on the surface of the impurity region 2 between the Al electrodes 9 and 10 by a thermal oxidation method at 1000 ° C., and the silicon oxide film 3 is formed. A Pt electrode 4 having a film thickness of 100 nm is formed on the Pt electrode 4 by sputtering, and Pt electrode 4 is formed on the Pt electrode 4.
b (DPM) ₂ , Zr (DPM) ₄ and Ti (i-C)
PZT (Pb) by MOCVD using ₃ H ₇ ) ₄
A (Zr _0.53 Ti _0.47 ) O ₃ , lead zirconate titanate) film 5 was formed with a thickness of 300 nm.

Next, an Al electrode 6 having a film thickness of 0.5 μm was formed as an upper electrode by the sputtering method. The area of the uppermost Al electrode 11 is 2 μm × 10 μm. Lead wires 7 and 8 are drawn out to the Pt electrode 4 and the Al electrode 6, respectively, so that voltages V _G1 and V _G2 can be applied thereto, respectively. Also lead wires 11 and 12 from Al wires 9 and 10
Are drawn out so that the voltages V _S and V _D can be applied respectively. In addition, 13 is an ohmic electrode with respect to the substrate, and 14 is a lead wire drawn from this ohmic electrode. In this way, the shape of FIG. 1 can be obtained.

FIG. 2 shows the relationship between the drain voltage V _D and the drain current I _D when the ferroelectric memory element according to the embodiment of the present invention is in the “ON” state and in the “OFF” state. It is a characteristic curve. Thus, in the "ON" state, the drain current peculiar to the field effect transistor flows, and in the "OFF" state, the drain current does not flow. This characteristic is very stable, indicating stable operation as an element.

In the above embodiment, it is possible to use a p-type silicon substrate instead of the n-type silicon substrate 1, in which case the p ⁺ -type impurity region 2 is n ^+.
It becomes an area.

[0024]

According to the ferroelectric memory element and its driving method of the present invention, since it can be driven by only positive or negative unipolar pulse, the driving circuit structure can be simplified and the potential of the lower electrode at the time of writing. Is also stable, the spontaneous polarization is stabilized, the operation of the element is also stabilized, and the yield of the element is remarkably improved, so that a stable element can be provided. Further, it is possible to apply a voltage with good symmetry to the ferroelectric film, and it is possible to improve the durability of repeated writing. Further, according to this element structure, since the source, drain and gate regions are integrated and have the same conductivity type, high integration of the element is possible, which is very useful in practice.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a ferroelectric memory element of the present invention.

FIG. 2 is a drain voltage V _{D of the} ferroelectric memory element of the present invention.
7 is a graph showing the relationship between the drain current I _D and the drain current I _D.

[Explanation of symbols]

 1 Silicon substrate 2 Impurity region 3 Silicon oxide film (dielectric film) 4 Pt electrode (lower electrode) 5 PZT ferroelectric film 6 Al electrode (upper electrode) 7 Lead wire 8 Lead wire 9 Al electrode (Ohmic electrode) 10 Al Electrode (Ohmic electrode) 11 Lead wire 12 Lead wire 13 Ohmic electrode of substrate 14 Lead wire

Claims (2)

[Claims] 1. A substrate made of a bulk semiconductor material of one conductivity type, an impurity region of a conductivity type opposite to the substrate formed in a surface layer of the substrate, and a dielectric formed on the impurity region. The impurity region comprises a body film, a lower electrode formed on the dielectric film, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. A ferroelectric memory element characterized by being an integrated region. 2. A substrate made of a bulk semiconductor material of one conductivity type, an impurity region of a conductivity type opposite to the substrate formed in a surface layer of the substrate, and a dielectric formed on the impurity region. The impurity region comprises a body film, a lower electrode formed on the dielectric film, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. 2. A method of driving a ferroelectric memory element, comprising applying a driving voltage to each of the lower electrode and the upper electrode in a ferroelectric memory element which is an integrated region.