JPH06151869A - Ferroelectric memory device - Google Patents

Abstract

PURPOSE:To stabilize an operation of a device and integrate the device in a ferroelectric nonvolatile memory capable of performing a non-destructive read. CONSTITUTION:A ferroelectric memory device comprises a substrate 1 made of a bulk semiconductor material of one conductive type, an impurity region 2 which is formed on the surface of the substrate 1 and has a conductive type opposite to the substrate 1, a dielectric film 3 formed on the impurity region 2, a first lower electrode 4 formed on the dielectric film 3, and an insulating protective film 5 formed so as to cover the impurity region 2, the dielectric film 3 and the first lower electrode 4. Further, the memory device comprises a second lower electrode 7 formed on the insulating protective film 5 in electrical contact with the first lower electrode 4 through a window formed in the insulating protective film 5 on the first lower electrode 4, a ferroelectric film 8 formed on the second lower electrode 7, and an upper electrode 11 formed on the ferroelectric film 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device. More specifically, it relates to a ferroelectric memory element that changes the electric resistance in an impurity region through electrostatic induction by spontaneous polarization of a ferroelectric film.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory element used in a computer or the like, a ROM (Read O
nly Memory), PROM (Program
Able ROM), EPROM (Erasable)
PROM), EEPROM (Electrically)
EPROM) and the like, and in particular, EEPROM is promising because the stored contents can be electrically rewritten.

In this EEPROM, MIS (M
etal-Insulator-Semiconduc
(tor) A method is known in which a trap region in a gate insulating film of a field effect transistor or a floating gate is charged by charge injection from a silicon substrate and the surface conductivity of the substrate is modulated by the electrostatic induction.

On the other hand, a method utilizing spontaneous polarization of a ferroelectric substance has been considered as a non-volatile memory having a method completely different from that of the EEPROM. Ferroelectrics are PZT (lead zirconate titanate), PbTiO ₃ (lead titanate), Ba
Oxides such as TiO ₃ (barium titanate) are mainly used, and P is the most promising non-volatile memory material at present.
ZT is being actively researched. As the base electrode of the PZT thin film, a Pt (platinum) electrode is often used in consideration of oxidation resistance and lattice matching.

Further, there are two kinds of structures in the method using the ferroelectric film, which are a capacitor structure and an MF, respectively.
S (Metal-Ferroelectric-Sem
icon) -FET (Field-Eff)
It is called an ect-Transistor) structure.
The capacitor structure has a structure in which a ferroelectric film is sandwiched between electrodes, and information is read out by detecting the presence or absence of a reversal current due to polarization reversal of the spontaneous polarization of the ferroelectric. On the other hand, in the MFS-FET structure, the gate insulating film of the MIS-FET is a ferroelectric film, and a semiconductor is used to compensate the spontaneous polarization according to the direction and size of the spontaneous polarization of the ferroelectric. Information is read out by utilizing the fact that the electric conductivity of the semiconductor surface is modulated by the electric charges induced on the surface.

[0006]

However, in a device utilizing the tunnel effect of electrons, a large electric field is required for charge injection from the silicon substrate, or traps are generated in the SiO ₂ insulating film. Then, there was a problem that the number of rewrites was limited. Further, in the capacitor structure, since the ferroelectric film is formed on the Pt electrode or the like, it is easy to obtain a relatively good film quality. Currently, vigorous development is underway toward commercialization. Since the stored information is destroyed, the information has to be rewritten again after reading. In the MFS-FET structure, non-destructive reading that does not destroy information at the time of reading is possible, but since the ferroelectric film is formed directly on the silicon semiconductor, the interface state density is difficult to determine, and an oxide film is formed on the semiconductor surface. There is also a problem that it is difficult to manufacture a stable element because of a problem that it is formed.

In order to solve such problems, the above MFS-
In the FET structure, a structure in which a dielectric thin film is formed between the lower electrode and the semiconductor surface has been proposed (JP-A-49-49).
131646). According to this structure, the lower electrode functions as a floating gate electrically insulated by the silicon substrate. However, in this structure, even if there is an electrode and a dielectric thin film between the ferroelectric film and the silicon substrate, these are very thin. Therefore, particularly in the case of a lead-based ferroelectric film such as PZT, metal raw materials such as Pb and Zr are used. Due to the poor purity, there has been a problem that the semiconductor film is contaminated by impurities such as Na from the ferroelectric film, which makes the operation of the semiconductor unstable.

Further, in order to form a single cell, the source, drain and gate must be formed separately from each other, so that there is a limit to the improvement of the degree of integration.

[0009]

Thus, according to the present invention, a substrate made of a bulk semiconductor material of one conductivity type and a conductivity type opposite to the substrate formed on the surface layer of the substrate. The impurity region, the dielectric film formed on the impurity region, the first lower electrode formed on the dielectric film, the impurity region, the dielectric film, and the first lower electrode are covered. An insulating protection film formed as described above and a window formed in the insulating protection film on the first lower electrode are electrically contacted with the first lower electrode to be formed on the insulating protection film. And a second lower electrode, a ferroelectric film formed on the second lower electrode, and an upper electrode formed on the ferroelectric film. Will be provided.

The ferroelectric memory element of the present invention will be described with reference to FIG. The substrate used is not particularly limited as long as it is a semiconductor material, but a silicon substrate or the like is preferable. Further, an impurity region 2 having a conductivity type opposite to that of the substrate is formed in the surface layer of the n-type or p-type conductivity type substrate.
As implantation ions for forming this impurity region 2,
When the p-type conductive region is used, for example, boron or the like is used,
When the n-type conductive layer is used, P, As, etc. may be mentioned. Such an ion is 40 to 80 KeV, 1 × 10 ¹³ to 1 ×
Impurity regions 2 can be formed by implanting ions at a concentration of about 10 ¹⁵ ions / cm ² and then performing annealing treatment at 600 to 1300 ° C. for about 5 minutes to 1 hour in a reducing atmosphere. The depth of the impurity region 2 thus formed is 0.02 to 0.2 μm.

The dielectric film 3 formed on the impurity region 2 can be formed using SiO ₂ , Si ₃ N ₄ or the like, and is preferably a SiO ₂ film. This SiO ₂ film can be formed by a known method, for example, thermal oxidation at 1000 to 1200 ° C., a CVD method, or an RF sputtering method, and its film thickness is about 0.1 to 10 μm. next,
The first lower electrode 4 is formed on the dielectric film 3. This first
As the material used for the lower electrode 4 of Al, for example, Al,
Metals that are usually used as electrodes such as Pt can be used, and these metals can be formed by a known method, for example, a sputtering method using a metal target, a CVD method, an evaporation method, or the like, and the film thickness thereof is 0.
It is preferably about 1 to 10 μm.

Further, an insulating protective film 5 is formed on the dielectric film 3 and the first lower electrode 4, and SiO ₂ , Si ₃ N ₄ or the like can be used as this material. It is preferably a SiO ₂ film. The thickness of this insulating protective film 5 is
It is a film thickness capable of preventing contamination by impurities from the ferroelectric film 8, and a film thickness of about 0.3 to 20 μm is preferable. next,
A window is formed in the insulating protective film 5 on the impurity region 2 and the first lower electrode 4 by a known method, for example, a wet etching method using HF, and a wiring layer (9, 10) is formed for further electrical contact. And 6) are formed.

A second lower electrode 7 is formed on the wiring layer 6 connected to the first lower electrode 4, a ferroelectric film 8 is formed on the second lower electrode 7, and then a ferroelectric film is formed. The upper electrode 11 is formed on the body film 8. The material and forming method used for the second lower electrode 7 and the upper electrode 11 are the same as those of the first lower electrode 4.
The film thickness is preferably about 0.1 to 10 μm and 0.1 to 10 μm, respectively.

Further, examples of the ferroelectric film 8 formed between the second lower electrode 7 and the upper electrode 11 include lead zirconate titanate (PZT), PLZT and the like. The ferroelectric film 8 is Known methods, for example, when using PZT, MOC
Pb (C ₂ H ₅ ) ₄ , Zr (DPM) ₄ and T by VD method
It is preferable to use i (i-C ₃ H ₇ ) ₄ or the like to form a film having a thickness of 0.1 to 10 μm.

On the wiring of the impurity region 2 and the back surface of the substrate,
Ohmic electrodes (12, 13 and 17) are formed respectively. The ohmic electrodes (12, 13 and 17) and the upper electrode 11 are provided with lead wires (15, 1) as voltage applying means.
6, 18 and 14) are connected. Further lead wire 1
5, 16 and 14 have voltages V _D , V _S and V _G , respectively.
Is applied.

The operation of this device is as follows. That is, when a pulse of + V _CC is applied to V _G as a drive voltage, the ferroelectric film 8 is polarized downward and the silicon oxide film 3 is also dielectrically polarized due to this electrostatic induction, so that the impurity regions 2 become carriers. Therefore, carriers can move between the electrode 9 and the electrode 10, and when + V _CC is applied to V _D , the drain current I _D flows and the device is turned on.

Then, when a pulse of -V _CC is applied to V _G , the ferroelectric film 8 is polarized upward and the dielectric film 3 is also dielectrically polarized due to this electrostatic induction. Since the depth of the impurity region 2 is such that the inversion layer reaches the substrate,
The portion of the impurity region 2 covered with the silicon oxide film 3 is in a depleted state in which carriers are depleted, and even if -V _CC is applied to V _D , the drain current I _D does not flow and the element is in the "OFF" state. Since the dielectric polarization of this dielectric film 3 is maintained as long as the polarization of the ferroelectric film 8 is maintained, it can be operated as a non-destructive and readable non-volatile memory. Further, according to this element structure, the source, drain, and gate regions are integrated and have the same conductivity type, so that high integration is possible.

[0018]

EXAMPLE A ferroelectric memory element of the present invention was manufactured as follows. On the front surface of the n-type silicon substrate 1 having the Al electrode 17 formed on the back surface by the sputtering method, 150 KeV,
Inject As at 1 × 10 ¹⁶ ions / cm ² and 1000 ° C.
P ⁺ type impurity region 2 by annealing at
Was formed. The depth of this impurity region 2 was 0.08 μm.

Next, a silicon oxide film 3 having a thickness of 100 nm is formed as a dielectric film on the surface of the impurity region 2 by 1000 times.
The silicon oxide film 3 is formed by a thermal oxidation method at a temperature of 100 ° C., an Al electrode 4 having a film thickness of 100 nm is formed on the silicon oxide film 3 by a sputtering method, and a silicon oxide film 5 having a film thickness of 1 μm is formed as an insulating protective film on the substrate by 300 μm. It was formed by the CVD method at ˜400 ° C. The source gas used at this time is SiH
₄ was used.

A window is formed in the silicon oxide film 5 on the Al electrode 4 and the impurity region 2 by reactive ion etching. Further, Al wires 6, 9 and 10 which are wiring layers were formed in this window by a vapor deposition method for electrical connection. Then Al
A Pt electrode 7 having a thickness of 100 nm is formed on the line 6 by the sputtering method.
On the Pt electrode 7, Pb (C ₂ H ₅ ) ₄ , Zr
MOCVD using (DPM) ₄ and Ti (i-C ₃ H ₇ ) ₄
A PZT (Pb (Zr _0.53 Ti _0.47 ) O ₃ , lead zirconate titanate) thin film 8 was formed to a thickness of 300 nm by the method.

Next, an Al electrode having a film thickness of 0.5 μm was formed as an upper electrode by the sputtering method. Top A
The area of the 1-electrode 11 is 2 μm × 10 μm. A lead wire 14 is drawn out from the Al electrode 11 so that a voltage V _G can be applied. Al electrodes 12 and 13 which are ohmic electrodes are respectively formed on the Al wires 9 and 10 by a sputtering method, and lead wires 15 and 16 are also drawn out from these Al electrodes 12 and 13, and voltages V _D and V are applied to them, respectively. _S can be applied. In addition,
Reference numeral 17 is an ohmic electrode with respect to the substrate, and 18 is a lead wire drawn from this ohmic electrode. In this way, the shape of FIG. 1 can be obtained.

FIG. 2 shows the relationship between the drain voltage V _D and the drain current I _D when the ferroelectric memory element according to the embodiment of the present invention is in the “ON” state and in the “OFF” state. It is a characteristic curve. Thus, in the "ON" state, the drain current peculiar to the field effect transistor flows, and in the "OFF" state, the drain current does not flow. This characteristic is very stable, indicating stable operation as an element.

In the above embodiment, it is possible to use a p-type silicon substrate instead of the n-type silicon substrate 1, in which case the p ⁺ -type impurity region 2 is n ^+.
It becomes an area.

[0024]

According to the ferroelectric memory element of the present invention, by providing the insulating protection film, it is possible to prevent the diffusion of impurities from the ferroelectric film to the semiconductor surface, so that the operation of the element becomes stable, It is possible to significantly improve the yield of the device and provide a stable device. Further, according to this element structure, the source, drain, and gate regions are integrated and have the same conductivity type, which is advantageous for integration of the element and is very useful in practice.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a ferroelectric memory element of the present invention.

FIG. 2 is a drain voltage V _{D of the} ferroelectric memory element of the present invention.
7 is a graph showing the relationship between the drain current I _D and the drain current I _D.

[Explanation of symbols]

 1 Silicon substrate 2 Impurity region 3 Silicon oxide film (dielectric film) 4 Al electrode (first lower electrode) 5 Silicon oxide film (insulating protective film) 6 Al line 7 Pt electrode (second lower electrode) 8 PZT strong Dielectric film 9 Al line 10 Al line 11 Al electrode (upper electrode) 12 Al electrode (ohmic electrode) 13 Al electrode (ohmic electrode) 14 lead wire 15 lead wire 16 lead wire 17 substrate ohmic electrode 18 lead wire

Claims (1)

[Claims] 1. A substrate made of a bulk semiconductor material of one conductivity type, an impurity region of a conductivity type opposite to the substrate formed in a surface layer of the substrate, and a dielectric formed on the impurity region. A body film, a first lower electrode formed on the dielectric film, the impurity region, the dielectric film, and the first
An insulating protection film formed so as to cover the lower electrode of the first lower electrode and a window formed in the insulating protection film on the first lower electrode to electrically contact the first lower electrode to protect the insulation. A second lower electrode formed on the film, a ferroelectric film formed on the second lower electrode, and an upper electrode formed on the ferroelectric film. Ferroelectric storage element.