JPH06163822A - Integrated circuit chip and composite semiconductor device - Google Patents
Integrated circuit chip and composite semiconductor deviceInfo
- Publication number
- JPH06163822A JPH06163822A JP43A JP31862992A JPH06163822A JP H06163822 A JPH06163822 A JP H06163822A JP 43 A JP43 A JP 43A JP 31862992 A JP31862992 A JP 31862992A JP H06163822 A JPH06163822 A JP H06163822A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- chip
- integrated circuit
- semiconductor device
- composite semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は集積回路チップおよび
複合半導体装置に関する。特に、ＬＳＩ(大規模集積回
路)チップの電源配線パターンに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuit chips and composite semiconductor devices. In particular, it relates to a power supply wiring pattern of an LSI (Large Scale Integrated Circuit) chip.
【０００２】[0002]
【従来の技術】図６に示すように、従来のＬＳＩチップ
では、内部の電源配線パターンは、信号線(図示せず)の
配線パターンと同様に、電源用電極パッド１１２a,１１
２bと電源供給を受けるべき部分１１３a,１１３bとを線
状の配線(電源線)１１０a,１１０bで結んだものとなっ
ている(１１３a,１１３bは電源線１１０a,１１０bの間
に分布している。)。なお、１１１a,１１１b,…は、上
記信号線につながる信号用電極パッドを示している。2. Description of the Related Art As shown in FIG. 6, in a conventional LSI chip, the internal power supply wiring pattern is the same as the wiring pattern of a signal line (not shown).
2b and the portions 113a, 113b to be supplied with power are connected by linear wirings (power supply lines) 110a, 110b (113a, 113b are distributed between the power supply lines 110a, 110b). ). Note that reference numerals 111a, 111b, ... Show signal electrode pads connected to the signal lines.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、近年の
ＬＳＩチップの高周波化に伴って、ＬＳＩチップ内部で
上記線状の電流路１００a,１００bによる電源ノイズが
問題になっている。つまり、線状の電流路１００a,１０
０bは交流電流に対して必ずインダクタンスを持ち、ま
た、近接する電流路の間には相互誘導が生じる。このイ
ンダクタンス成分や相互誘導によって生じる起電力が電
源ノイズとなる。However, power supply noise due to the linear current paths 100a and 100b in the LSI chip has become a problem with the recent increase in the frequency of LSI chips. That is, the linear current paths 100a, 10
0b always has an inductance with respect to an alternating current, and mutual induction occurs between adjacent current paths. The electromotive force generated by this inductance component and mutual induction becomes power source noise.
【０００４】例えば、図５に示すように、ＬＳＩチップ
の内部で、インバータ２０１,２０２の出力が否定論理
積回路(ＮＡＮＤ)２０３の入力に接続されている場合を
考える。まず、インバータ２０１の出力信号電流Ｉ１が
点Ｐ１から点Ｐ２に至る経路を流れたとする。すると、
電荷量保存則から、流れ出た電荷量はインバータ２０１
につながる上下２本の電源配線３０１,３０２,(３０３,
３０４)のうちいずれかの配線を通って帰ってくる。す
べて下側の配線３０２,(３０４)を通って帰ってくるも
のとすると、ＮＡＮＤ２０３から点Ｐ３,Ｐ４,Ｐ５,Ｐ
６Ｐ７,Ｐ８を経てインバータ２０１に還流する(電流Ｉ
２)。このとき、途中の点Ｐ７,Ｐ４に接続されているイ
ンバータ２０４やインバータ２０５が、電流Ｉ２によっ
て配線３０２,３０４のインダクタンス成分や相互誘導
を介して電源ノイズ(起電力)を受ける。For example, as shown in FIG. 5, consider a case where the outputs of the inverters 201 and 202 are connected to the inputs of a NAND circuit (NAND) 203 inside the LSI chip. First, it is assumed that the output signal current I1 of the inverter 201 flows through the path from the point P1 to the point P2. Then,
According to the law of conservation of electric charge, the amount of electric charge flowing out is
Power lines 301, 302, (303, (303,
It returns through one of the wiring 304). Assuming that all come back through the lower wirings 302, (304), the NAND 203 points P3, P4, P5, P
6P7, P8 to return to the inverter 201 (current I
2). At this time, the inverter 204 or the inverter 205 connected to the points P7 and P4 on the way receives the power source noise (electromotive force) due to the current I2 via the inductance components of the wirings 302 and 304 and mutual induction.
【０００５】この電源ノイズ(起電力)は、知られている
ように、電流の時間変化に比例し、動作周波数が高くな
れば大きくなる。このため、ＬＳＩチップが高周波化す
るにつれて、次第に無視できなくなっている。As is known, this power supply noise (electromotive force) is proportional to the time change of the current, and increases as the operating frequency increases. Therefore, as the frequency of the LSI chip increases, it cannot be ignored.
【０００６】この事情は、２つのＬＳＩチップの表面を
互いに対向させ、上記両チップ表面の間をバンプ電極で
接続してなる複合半導体装置(シリコン・オン・シリコ
ン方式と呼ばれる)においても同様である。This situation also applies to a composite semiconductor device (called a silicon-on-silicon system) in which the surfaces of two LSI chips are opposed to each other and the surfaces of the two chips are connected by bump electrodes. .
【０００７】なお、図５中に示すインバータ２０２とＮ
ＡＮＤ２０３との間のように、信号線３０５と電源線３
０３,３０４とを平行に配置した場合、電源ノイズは相
殺されて若干改善される。しかし、そうすれば概して電
源線が長くなり、インダクタンス成分が比例して増大す
るため、好ましいものではない。また、回路素子の信号
線,電源線をすべて平行に配置することができない場合
も多い。The inverter 202 and N shown in FIG.
Signal line 305 and power supply line 3 such as between AND 203
When 03 and 304 are arranged in parallel, the power supply noise is canceled out and slightly improved. However, doing so is generally not preferable because the power supply line becomes long and the inductance component increases in proportion. In many cases, it is not possible to arrange the signal lines and power lines of the circuit elements in parallel.
【０００８】そこで、この発明の目的は、電源ノイズを
低減できる集積回路チップおよび複合半導体装置を提供
することにある。Therefore, an object of the present invention is to provide an integrated circuit chip and a composite semiconductor device capable of reducing power source noise.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するた
め、この発明の集積回路チップは、チップ表面に、信号
用電極パッドを除いた略全域を覆う面状の電源配線パタ
ーンを有することを特徴としている。In order to achieve the above object, the integrated circuit chip of the present invention has a planar power supply wiring pattern on the surface of the chip, covering substantially the entire area except for the signal electrode pads. I am trying.
【００１０】また、この発明の複合半導体装置は、接地
側電源および電力供給側電源の供給を受ける２つの集積
回路チップの表面を互いに対向させ、上記両チップ表面
の間をバンプ電極で接続してなる複合半導体装置におい
て、上記集積回路チップのうち一方は接地側電源に面状
の電源配線パターンを有し、上記集積回路チップのうち
他方は電力供給側電源に面状の電源配線パターンを有す
ることを特徴としている。Also, in the composite semiconductor device of the present invention, the surfaces of two integrated circuit chips which are supplied with the ground-side power supply and the power supply-side power supply are opposed to each other, and the surfaces of the two chips are connected by bump electrodes. In the composite semiconductor device, one of the integrated circuit chips has a planar power supply wiring pattern on the ground side power supply, and the other of the integrated circuit chips has a planar power supply wiring pattern on the power supply side power supply. Is characterized by.
【００１１】[0011]
【作用】この発明の集積回路チップでは、面状の電源配
線パターン(以下、「電源面」という。)から直下の回路素
子に直接電源が供給され、信号電流の還流は、上記電源
面内で最短距離で行なわれる。したがって、従来に比し
てインダクタンス成分や相互誘導が減少して、電源ノイ
ズが低減される。In the integrated circuit chip of the present invention, power is directly supplied from the planar power supply wiring pattern (hereinafter referred to as "power supply surface") to the circuit element immediately below, and the signal current is circulated within the power supply surface. It is done in the shortest distance. Therefore, the inductance component and mutual induction are reduced as compared with the conventional case, and the power supply noise is reduced.
【００１２】また、多くのＬＳＩ、例えばＣＭＯＳ(相
補型ＭＯＳＦＥＴ集積回路)は、接地側電源と電力供給
側電源(いわゆるグランドとＶcc)との２種類を用いる。
１つのチップ表面でグランドとＶccの両方の配線パター
ンをいずれも電源面とした場合、２つの電源面間にピン
ホールによる短絡などが起こって、ＬＳＩチップの歩留
が低下する恐れがある。そこで、２つのＬＳＩチップの
表面(主面)を互いに対向させ、上記両チップ表面の間を
バンプ電極で接続してなる複合半導体装置では、上記１
つのチップにそれぞれ１つずつの電源面を設ける。すな
わち、１つのチップではグランド側を電源面,Ｖcc側を
通常の電源線とし、もう１つのチップではグランド側を
通常の電源線,Ｖcc側を電源面とする。これにより、２
つのチップにグランドおよびＶccが供給される上、歩留
低下を招くことなく電源ノイズが低減される。Further, many LSIs, for example, CMOS (complementary MOSFET integrated circuits) use two types of a power source on the ground side and a power source on the power supply side (so-called ground and Vcc).
If both the ground and Vcc wiring patterns are used as power supply planes on the surface of one chip, a short circuit due to pinholes may occur between the two power supply planes, which may reduce the yield of LSI chips. Therefore, in the composite semiconductor device in which the surfaces (main surfaces) of two LSI chips are opposed to each other and the surfaces of both chips are connected by bump electrodes,
Each chip has one power supply surface. That is, in one chip, the ground side is the power supply surface, the Vcc side is the normal power supply line, and in the other chip, the ground side is the normal power supply line and the Vcc side is the power supply surface. This gives 2
The ground and Vcc are supplied to one chip, and the power supply noise is reduced without lowering the yield.
【００１３】[0013]
【実施例】以下、この発明の集積回路チップおよび複合
半導体装置を実施例により詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The integrated circuit chip and composite semiconductor device of the present invention will be described in detail below with reference to embodiments.
【００１４】図１はこの発明の一実施例のＬＳＩチップ
の表面(主面)を示している。FIG. 1 shows the surface (principal surface) of an LSI chip according to an embodiment of the present invention.
【００１５】このＬＳＩチップ１は、チップ表面に、信
号用電極パッド１１を除いた略全域を覆う電源面１２を
有している。１２aはチップ１外から電源面１２に電源
を供給するための端子を示している。このＬＳＩチップ
１の回路素子部分は、すべて上記電源面１２によって覆
われており、電源面１２は、適宜コンタクトホール(図
示せず)を介して、直下の回路素子に接続されている。
したがって、電源面１２から直下の回路素子に直接電源
が供給され、信号電流の還流は、上記電源面１２内で最
短距離で行なわれる。したがって、従来に比してインダ
クタンス成分や相互誘導を減少でき、電源ノイズを低減
することができる。The LSI chip 1 has a power supply surface 12 which covers almost the entire area of the chip surface except the signal electrode pads 11. Reference numeral 12a indicates a terminal for supplying power to the power supply surface 12 from outside the chip 1. The circuit element portion of the LSI chip 1 is entirely covered with the power supply surface 12, and the power supply surface 12 is connected to the circuit element immediately below through a contact hole (not shown) as appropriate.
Therefore, the power is directly supplied from the power surface 12 to the circuit element immediately below, and the signal current is circulated in the power surface 12 at the shortest distance. Therefore, the inductance component and mutual induction can be reduced as compared with the conventional case, and the power supply noise can be reduced.
【００１６】ＮＭＯＳ(Ｎチャネル型ＭＯＳＦＥＴ集積
回路)など、接地側電源,電力供給側電源のうち一方を基
準として動作している回路方式では、この例のように、
基準となる側の電源だけを電源面１２とするだけでも、
電源ノイズに対しては有効である。In a circuit system such as an NMOS (N-channel type MOSFET integrated circuit) which operates based on one of the ground side power source and the power supply side power source, as in this example,
Even if only the power supply on the reference side is the power supply surface 12,
It is effective against power supply noise.
【００１７】図４はこの発明の他の実施例の複合半導体
装置を示している。FIG. 4 shows a composite semiconductor device according to another embodiment of the present invention.
【００１８】この複合半導体装置(以下、単に「装置」と
いう。)は、図２に示すＣＭＯＳ型ＬＳＩチップ２を裏
返しにして、バンプ電極を介して図３に示すＣＭＯＳ型
ＬＳＩチップ３の上に接続したものである(フリップチ
ップ・ボンディング)。This composite semiconductor device (hereinafter simply referred to as "device") has the CMOS type LSI chip 2 shown in FIG. 2 turned upside down and is placed on the CMOS type LSI chip 3 shown in FIG. 3 via bump electrodes. Connected (flip chip bonding).
【００１９】図２に示すように、ＬＳＩチップ２の表面
(主面)には、周辺部を除いた略全域を覆う電源面２２が
設けられている。電源面２２は、その周囲に、装置の外
部から(実際にはＬＳＩチップ３を介して)電力供給側電
源(Ｖcc)の供給を受けるための電極２２cと、ＬＳＩチ
ップ３へ上記Ｖccを供給するための電極２２a,２２bを
有している。チップ表面の周辺部には、装置外部(ＬＳ
Ｉチップ３を介して)との信号入出力用の電極２１aと、
ＬＳＩチップ３から接地側電源(グランド)の供給を受け
るための電極２３a,２３bが設けられている。このＬＳ
Ｉチップ２の回路素子部分は、すべて上記電源面２２に
よって覆われており、電源面２２は、適宜コンタクトホ
ール(図示せず)を介して、直下の回路素子に接続されて
いる。また、グランド側の電極２３a,２３bは図示しな
い通常の電源線によって回路素子に接続されている。As shown in FIG. 2, the surface of the LSI chip 2
The (main surface) is provided with a power supply surface 22 that covers substantially the entire area except the peripheral portion. The power supply surface 22 supplies an electrode 22c around the power supply surface 22 for receiving a power supply side power supply (Vcc) from the outside of the device (actually via the LSI chip 3) and the Vcc to the LSI chip 3. It has electrodes 22a and 22b for. The outside of the device (LS
An electrode 21a for signal input / output with (via the I-chip 3),
Electrodes 23a and 23b for receiving the ground side power supply (ground) from the LSI chip 3 are provided. This LS
The circuit element portion of the I-chip 2 is entirely covered with the power supply surface 22, and the power supply surface 22 is connected to the circuit element immediately below through a contact hole (not shown) as appropriate. The electrodes 23a and 23b on the ground side are connected to the circuit element by a normal power line (not shown).
【００２０】一方、図３に示すように、ＬＳＩチップ３
の表面(主面)には、チップ表面の周辺部を除く略全域を
覆う電源面３３が設けられている。電源面３３は、周囲
に、装置外部から接地側電源(グランド)の供給を受ける
ための電極３３cと、ＬＳＩチップ２へ上記グランドを
供給するための電極３３a,３３bを有している。チップ
表面の周辺部には、装置外部との信号入出力用の電極３
１cと、ＬＳＩチップ２との信号入出力用の電極３１a
と、装置外部とＬＳＩチップ２との間の信号入出力を中
継するための電極３１bが設けられている。さらに、装
置外部から電力供給側電源(Ｖcc)の供給を受けるととも
にＬＳＩチップ２へ上記Ｖccを供給するための電極３２
cと、ＬＳＩチップ２の電源面２２からＶccの供給を受
ける電極３２aが設けられている。このＬＳＩチップ３
の回路素子部分は、すべて上記電源面３３によって覆わ
れており、電源面３３は、適宜コンクトホール(図示せ
ず)を介して、直下の回路素子に接続されている。ま
た、Ｖcc側の電極３２a,３２cは図示しない通常の電源
線によって回路素子に接続されている。On the other hand, as shown in FIG.
A power supply surface 33 is provided on the surface (main surface) of the chip, covering substantially the entire area of the chip surface except the peripheral portion. The power supply surface 33 has, on the periphery thereof, an electrode 33c for receiving a ground side power supply (ground) from the outside of the device and electrodes 33a, 33b for supplying the ground to the LSI chip 2. Electrodes 3 for inputting and outputting signals to and from the outside of the device are provided on the periphery of the chip surface
Electrode 31a for signal input / output between 1c and LSI chip 2
And an electrode 31b for relaying signal input / output between the outside of the device and the LSI chip 2. Further, an electrode 32 for receiving the power supply side power supply (Vcc) from the outside of the device and for supplying the Vcc to the LSI chip 2
c and an electrode 32a which receives Vcc from the power supply surface 22 of the LSI chip 2 are provided. This LSI chip 3
All the circuit element portions of are covered by the power supply surface 33, and the power supply surface 33 is connected to the circuit element immediately below through a contact hole (not shown) as appropriate. The electrodes 32a and 32c on the Vcc side are connected to the circuit element by a normal power supply line (not shown).
【００２１】図４に示すように、ＬＳＩチップ２とＬＳ
Ｉチップ３とをフリップチップ・ボンディングした状態
では、電極２２cと電極３２c、電極２３bと電極３３b、
電極２１aと電極３１a、電極２２aと電極３２aがそれぞ
れバンプ電極４０,４１,…によって接続される(簡単の
ため、要部を模式的に示している。)。As shown in FIG. 4, the LSI chip 2 and the LS
In the state where the I-chip 3 is flip-chip bonded, the electrodes 22c and 32c, the electrodes 23b and 33b,
The electrode 21a and the electrode 31a, and the electrode 22a and the electrode 32a are connected by bump electrodes 40, 41, ... (The main part is schematically shown for simplification).
【００２２】装置外部から電極３２cにＶccが供給さ
れ、バンプ電極４０,電極２２cを通して電源面２２はＶ
ccの供給を受ける。したがって、ＬＳＩチップ２内の回
路素子には電源面２２から直接Ｖccが供給される。ま
た、ＬＳＩチップ３内の回路素子には電極３２cと電極
３２a(電極２２a,バンプ電極４３を通して)から電源線
を通してＶccが供給される。一方、装置外部から電極３
３cを通して電源面３３にグランドが供給される。した
がって、ＬＳＩチップ３内の回路素子には電源面３３か
ら直接グランドが供給される。また、ＬＳＩチップ２内
の回路素子には、電極３３b(および３３a)からバンプ電
極４１,電極２３b,電源線を通してグランドが供給され
る。なお、ＬＳＩチップ２とＬＳＩチップ３との間の信
号の入出力は、電極２１a,バンプ電極４２および電極３
１aを通して行なわれる。Vcc is supplied from the outside of the device to the electrode 32c, and the power supply surface 22 is supplied with Vcc through the bump electrode 40 and the electrode 22c.
Receive cc supply. Therefore, Vcc is directly supplied to the circuit elements in the LSI chip 2 from the power supply surface 22. Further, Vcc is supplied to the circuit element in the LSI chip 3 from the electrode 32c and the electrode 32a (through the electrode 22a and the bump electrode 43) through the power supply line. On the other hand, the electrode 3 from the outside of the device
The ground is supplied to the power supply surface 33 through 3c. Therefore, the ground is directly supplied to the circuit elements in the LSI chip 3 from the power supply surface 33. Further, the circuit element in the LSI chip 2 is supplied with ground from the electrode 33b (and 33a) through the bump electrode 41, the electrode 23b, and the power supply line. Input / output of signals between the LSI chip 2 and the LSI chip 3 is performed by the electrodes 21a, the bump electrodes 42, and the electrodes 3a.
It is done through 1a.
【００２３】このように、この複合半導体装置では、Ｌ
ＳＩチップ３ではグランド側を電源面３３,Ｖcc側を通
常の電源線とし、ＬＳＩチップ２ではグランド側を通常
の電源線,Ｖcc側を電源面２２としている。これによ
り、２つのチップにグランドおよびＶccが供給すること
ができる。その上、１つのチップに電源面を２層設ける
場合と異なり、電源面間のピンホールなどによる歩留低
下を招くことなく、電源ノイズを低減することができ
る。As described above, in this composite semiconductor device, L
In the SI chip 3, the ground side is the power supply surface 33 and the Vcc side is the normal power supply line, and in the LSI chip 2, the ground side is the normal power supply line and the Vcc side is the power supply surface 22. As a result, the ground and Vcc can be supplied to the two chips. In addition, unlike the case where two power supply layers are provided on one chip, power supply noise can be reduced without lowering the yield due to pinholes between the power supply surfaces.
【００２４】なお、当然ながら、各ＬＳＩチップ２,３
の電源面と電源線とを入れ換えても良い。つまり、ＬＳ
Ｉチップ２のグランド側を電源面,Ｖcc側を通常の電源
線とし、ＬＳＩチップ３のグランド側を通常の電源線,
Ｖcc側を電源面２２としても良い。Of course, each LSI chip 2, 3
The power supply surface and the power supply line may be interchanged. That is, LS
The ground side of the I chip 2 is the power supply side, the Vcc side is the normal power supply line, and the ground side of the LSI chip 3 is the normal power supply line,
The Vcc side may be used as the power supply surface 22.
【００２５】[0025]
【発明の効果】以上より明らかなように、この発明の集
積回路チップは、チップ表面に、信号用電極パッドを除
いた略全域を覆う電源面を有しているので、この電源面
から直下の回路素子に直接電源供給を行うことができ
る。したがって、信号電流の還流経路を最短にしてイン
ダクタンス成分や相互誘導を減少させ、電源ノイズを低
減することができる。As is apparent from the above, the integrated circuit chip of the present invention has a power supply surface covering almost the entire area excluding the signal electrode pads on the chip surface. Power can be directly supplied to the circuit elements. Therefore, it is possible to reduce the inductance component and mutual induction by shortening the return path of the signal current and reduce the power supply noise.
【００２６】また、この発明は、接地側電源および電力
供給側電源の供給を受ける２つの集積回路チップの表面
を互いに対向させ、上記両チップ表面の間をバンプ電極
で接続してなる複合半導体装置において、上記集積回路
チップのうち一方には接地側に電源面を設け、他方には
電力供給側に電源面を設けている。すなわち２つのチッ
プに１つずつ電源面を設けている。したがって、２つの
チップに接地側電源および電力供給側電源を供給でき、
しかも、電源面間のピンホールなどによって歩留を低下
させることなく、電源ノイズを低減することができる。The present invention is also a composite semiconductor device in which the surfaces of two integrated circuit chips which are supplied with a power supply on the ground side and a power supply on the power supply side are opposed to each other and bump surfaces are connected between the two chip surfaces. In one of the above integrated circuit chips, a power supply surface is provided on the ground side and the other is provided with a power supply surface on the power supply side. That is, one power supply surface is provided for each of the two chips. Therefore, the ground side power supply and the power supply side power supply can be supplied to the two chips,
Moreover, the power supply noise can be reduced without lowering the yield due to pinholes between the power supply surfaces.
【図１】 この発明の一実施例のＬＳＩチップの電源配
線パターンを示す図である。FIG. 1 is a diagram showing a power supply wiring pattern of an LSI chip according to an embodiment of the present invention.
【図２】 この発明の別の実施例の複合半導体装置を構
成する一方のＬＳＩチップの電源配線パターンを示す図
である。FIG. 2 is a diagram showing a power supply wiring pattern of one LSI chip constituting a composite semiconductor device of another embodiment of the present invention.
【図３】 上記複合半導体装置を構成する他方のＬＳＩ
チップの電源配線パターンを示す図である。FIG. 3 is another LSI forming the above composite semiconductor device
It is a figure which shows the power supply wiring pattern of a chip.
【図４】 上記複合半導体装置の全体構成を模式的に示
す図である。FIG. 4 is a diagram schematically showing an overall configuration of the composite semiconductor device.
【図５】 従来のＬＳＩチップの内部での信号の流れを
説明する図である。FIG. 5 is a diagram for explaining a signal flow inside a conventional LSI chip.
【図６】 従来のＬＳＩチップの電源配線パターンを示
す図である。FIG. 6 is a diagram showing a power supply wiring pattern of a conventional LSI chip.
１ ＬＳＩチップ ２,３ ＣＭＯＳ型ＬＳＩチップ １２,２２,３３ 電源面 1 LSI chip 2,3 CMOS type LSI chip 12,22,33 Power plane
Claims (2)
た略全域を覆う面状の電源配線パターンを有することを
特徴とする集積回路チップ。1. An integrated circuit chip having a planar power supply wiring pattern covering substantially the entire area excluding signal electrode pads on the surface of the chip.
を受ける２つの集積回路チップの表面を互いに対向さ
せ、上記両チップ表面の間をバンプ電極で接続してなる
複合半導体装置において、 上記集積回路チップのうち一方は接地側電源に面状の電
源配線パターンを有し、上記集積回路チップのうち他方
は電力供給側電源に面状の電源配線パターンを有するこ
とを特徴とする複合半導体装置。2. A composite semiconductor device in which the surfaces of two integrated circuit chips which are supplied with a ground-side power supply and a power supply-side power supply are opposed to each other and bump surfaces are connected between the two chip surfaces. A composite semiconductor device, wherein one of the circuit chips has a planar power supply wiring pattern on a ground side power supply, and the other of the integrated circuit chips has a planar power supply wiring pattern on a power supply side power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31862992A JP3171495B2 (en) | 1992-11-27 | 1992-11-27 | Composite semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31862992A JP3171495B2 (en) | 1992-11-27 | 1992-11-27 | Composite semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06163822A true JPH06163822A (en) | 1994-06-10 |
| JP3171495B2 JP3171495B2 (en) | 2001-05-28 |
Family
ID=18101274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31862992A Expired - Lifetime JP3171495B2 (en) | 1992-11-27 | 1992-11-27 | Composite semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3171495B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211576B1 (en) | 1998-09-18 | 2001-04-03 | Hitachi, Ltd. | Semiconductor device |
| JP2002134685A (en) * | 2000-10-26 | 2002-05-10 | Rohm Co Ltd | Integrated circuit device |
| US7804573B2 (en) | 1996-09-20 | 2010-09-28 | Renesas Technology Corp. | Liquid crystal display device, method for fabricating the same, and portable telephone using the same |
-
1992
- 1992-11-27 JP JP31862992A patent/JP3171495B2/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7804573B2 (en) | 1996-09-20 | 2010-09-28 | Renesas Technology Corp. | Liquid crystal display device, method for fabricating the same, and portable telephone using the same |
| US7876414B2 (en) | 1996-09-20 | 2011-01-25 | Renesas Electronics Corporation | Liquid crystal display device, method for fabricating the same, and portable telephone using the same |
| US8009259B2 (en) | 1996-09-20 | 2011-08-30 | Renesas Electronics Corporation | Liquid crystal display device, method for fabricating the same, and portable telephone using the same |
| US6211576B1 (en) | 1998-09-18 | 2001-04-03 | Hitachi, Ltd. | Semiconductor device |
| US6326699B2 (en) | 1998-09-18 | 2001-12-04 | Hitachi, Ltd. | Semiconductor device |
| US6531785B2 (en) | 1998-09-18 | 2003-03-11 | Hitachi, Ltd. | Semiconductor device |
| US6784533B2 (en) | 1998-09-18 | 2004-08-31 | Renesas Technology Corp. | Semiconductor device |
| US6882039B2 (en) | 1998-09-18 | 2005-04-19 | Renesas Technology Corp. | Semiconductor device |
| US7030478B2 (en) | 1998-09-18 | 2006-04-18 | Renesas Technology Corp. | Semiconductor device |
| US7119446B2 (en) | 1998-09-18 | 2006-10-10 | Hitachi, Ltd. | Semiconductor device |
| JP2002134685A (en) * | 2000-10-26 | 2002-05-10 | Rohm Co Ltd | Integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3171495B2 (en) | 2001-05-28 |
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