JPH06163736A - Package for housing semiconductor element - Google Patents

Package for housing semiconductor element

Info

Publication number
JPH06163736A
JPH06163736A JP4309154A JP30915492A JPH06163736A JP H06163736 A JPH06163736 A JP H06163736A JP 4309154 A JP4309154 A JP 4309154A JP 30915492 A JP30915492 A JP 30915492A JP H06163736 A JPH06163736 A JP H06163736A
Authority
JP
Japan
Prior art keywords
semiconductor element
metal
metal member
kovar
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4309154A
Other languages
Japanese (ja)
Inventor
Satoshi Oike
智 大池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4309154A priority Critical patent/JPH06163736A/en
Publication of JPH06163736A publication Critical patent/JPH06163736A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To provide a package for housing semiconductor elements that can normally and stably operate a semiconductor element for a long period by effectively absorbing and removing the heat generating by the semiconductor element and preventing an insulating container from generating cracks and breakage absolutely. CONSTITUTION:On the outer surface of an insulation substrate 1 including a semiconductor element 3, a metallic member 9 containing Kovar or invar is bonded and fixed by means of a bonding material 10 that will be melted or thermoset under a temperature lower than the displacement point of Kovar or invar.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子、特に半導体
集積回路素子を収容するための半導体素子収納用パッケ
ージの改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement of a semiconductor device housing package for housing a semiconductor integrated circuit device.

【0002】[0002]

【従来技術】近時、情報処理装置の高性能化、高速度化
に伴い、それを構成する半導体素子も高密度、高集積化
が急激に進んでいる。そのため半導体素子の単位面積、
単位体積当たりの発熱量が増大し、半導体素子を正常、
且つ安定に作動させるためにはその熱をいかに効率的に
除去するかが課題となっている。
2. Description of the Related Art In recent years, as the performance and speed of information processing apparatuses have increased, the density and integration of semiconductor elements forming the information processing apparatuses have rapidly increased. Therefore, the unit area of the semiconductor element,
The amount of heat generated per unit volume increases, and the semiconductor element is
In addition, how to efficiently remove the heat is a problem for stable operation.

【0003】従来、半導体素子が発生する熱の除去方法
としては半導体素子を、酸化アルミニウム質焼結体から
成る絶縁容器の外表面にメタライズ金属層を被着形成す
るとともに該メタライズ金属層に銅等の金属から成る金
属部材を銀ロウ等のロウ材を介し取着した構造の半導体
素子収納用パッケージに収容し、半導体素子から発生さ
れる熱を金属部材に吸収させるとともに該吸収した熱を
大気中に放散させることによって行われている。
Conventionally, as a method of removing the heat generated by a semiconductor element, the semiconductor element is formed by depositing a metallized metal layer on the outer surface of an insulating container made of an aluminum oxide sintered body, and copper or the like is formed on the metallized metal layer. The metal member made of the above metal is housed in a semiconductor element housing package having a structure in which a brazing material such as silver wax is attached, and the heat generated from the semiconductor element is absorbed by the metal member and the absorbed heat is stored in the atmosphere. It is done by dissipating it.

【0004】しかしながら、この従来の半導体素子収納
用パッケージは絶縁容器が酸化アルミニウム質焼結体か
ら成り、その熱膨張係数が6.5 〜7.5 ×10-6/ ℃である
のに対し、金属部材を構成する銅の熱膨張係数は14.0〜
20.0×10-6/ ℃であり、両者大きく相違するため絶縁容
器と金属部材に、例えば半導体素子が作動時に発した熱
等が繰り返し印加されると絶縁容器と金属部材との取着
部に両者の熱膨張係数の相違に起因する大きな熱応力が
発生し、該熱応力によって絶縁容器にクラックや割れが
発生してしまうという欠点を有していた。そのためこの
従来の半導体素子収納用パッケージでは内部に収容する
半導体素子の気密封止が短時間で破れ、半導体素子を長
期間にわたり正常、且つ安定に作動させることができな
かった。
However, in the conventional package for accommodating semiconductor elements, the insulating container is made of an aluminum oxide sintered body and has a coefficient of thermal expansion of 6.5 to 7.5 × 10 −6 / ° C., whereas a metal member is formed. The thermal expansion coefficient of copper is 14.0-
20.0 × 10 -6 / ℃, which is a big difference between the insulating container and the metal member, for example, when the heat generated during the operation of the semiconductor element is repeatedly applied, both the insulating container and the metal member attachment portion There is a drawback that a large thermal stress is generated due to the difference in the coefficient of thermal expansion, and the thermal stress causes cracks and breaks in the insulating container. Therefore, in this conventional package for housing a semiconductor element, the hermetic sealing of the semiconductor element housed inside is broken in a short time, and the semiconductor element cannot be operated normally and stably for a long period of time.

【0005】そこで上記欠点を解消するために金属部材
を銅に変えて絶縁容器を構成する酸化アルミニウム質焼
結体と熱膨張係数が近似するコバール金属やインバー合
金を含む金属材で形成することが考えられる。
In order to solve the above-mentioned drawbacks, therefore, the metal member may be changed to copper and the aluminum oxide sintered body forming the insulating container may be made of a metal material having a thermal expansion coefficient similar to that of Kovar metal or Invar alloy. Conceivable.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、コバー
ル金属やインバー合金はその変移点( 約430 ℃) 以下の
温度においては酸化アルミニウム質焼結体に近似した熱
膨張係数を有するものの変移点を越える温度ではその熱
膨張係数が急激に大きくなって酸化アルミニウム質焼結
体の熱膨張係数と合わなくなる。そのため金属部材をコ
バール金属やインバー合金を含む金属材で形成した場
合、金属部材を絶縁容器の外表面に設けたメタライズ金
属層に銀ロウを介して取着する際、銀ロウ材の溶融温度
が約900 ℃とコバール金属やインバー合金の変移点( 約
430 ℃) を越える温度であるため絶縁容器と金属部材と
の取着部に両者の熱膨張係数の相違に起因する大きな熱
応力が発生し、該熱応力によって絶縁容器にクラックや
割れが発生してしまう。
However, a Kovar metal or Invar alloy has a coefficient of thermal expansion similar to that of an aluminum oxide sintered body at a temperature below its transition point (about 430 ° C.), but a temperature exceeding the transition point. Then, the thermal expansion coefficient of the aluminum oxide sintered body becomes so large that it does not match the thermal expansion coefficient of the aluminum oxide sintered body. Therefore, when the metal member is formed of a metal material containing Kovar metal or Invar alloy, when the metal member is attached to the metallized metal layer provided on the outer surface of the insulating container via the silver solder, the melting temperature of the silver brazing material is About 900 ℃ and the transition point of Kovar metal and Invar alloy (about
Since the temperature exceeds 430 ℃), a large thermal stress is generated in the attachment part between the insulating container and the metal member due to the difference in thermal expansion coefficient between the two, and the thermal stress causes cracks or cracks in the insulating container. Will end up.

【0007】従って、金属部材をコバール金属やインバ
ー合金を含む金属材で形成したとしても絶縁容器には依
然としてクラックや割れが発生し、内部に収容する半導
体素子を長期間にわたり正常、且つ安定に作動させるこ
とができないという課題を有する。
Therefore, even if the metal member is formed of a metal material containing Kovar metal or Invar alloy, the insulating container is still cracked or broken, and the semiconductor element housed therein can be operated normally and stably for a long period of time. There is a problem that it cannot be done.

【0008】[0008]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は半導体素子が発生する熱を良好に吸収除
去するとともに絶縁容器にクラックや割れが発生するの
を皆無として収容する半導体素子を長期間にわたり正
常、且つ安定に作動させることができる半導体素子収納
用パッケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to absorb and remove the heat generated by a semiconductor element well and to accommodate the occurrence of no cracks or breaks in the insulating container. It is an object of the present invention to provide a package for accommodating a semiconductor element, which can operate the semiconductor element normally and stably for a long period of time.

【0009】[0009]

【課題を解決するための手段】本発明の半導体素子収納
用パッケージは半導体素子を収容する絶縁容器の外表面
にコバール金属もしくはインバー合金を含む金属部材
を、該コバール金属もしくはインバー合金の変移点以下
の温度で溶融もしくは熱硬化する接合材を介して接合取
着させたことを特徴とするものである。
According to the present invention, there is provided a package for accommodating a semiconductor element, wherein a metal member containing Kovar metal or Invar alloy is provided on the outer surface of an insulating container for accommodating a semiconductor element, the transition point of the Kovar metal or Invar alloy being below It is characterized in that it is joined and attached via a joining material that melts or thermosets at the temperature of.

【0010】[0010]

【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁容器の外表面にコバール金属もしくはインバー
合金を含む金属部材を、該コバール金属もしくはインバ
ー合金の変移点以下の温度で溶融もしくは熱硬化する接
合材を介して取着させることから取着時、絶縁容器と金
属部材との間には大きな熱応力が発生することはなく、
絶縁容器にクラックや割れ等が発生するのを皆無として
絶縁容器に金属部材を強固に取着することが可能とな
る。
According to the package for housing a semiconductor device of the present invention, a metal member containing Kovar metal or Invar alloy on the outer surface of an insulating container is melted or thermoset at a temperature below the transition point of the Kovar metal or Invar alloy. Since it is attached via the bonding material, during attachment, a large thermal stress does not occur between the insulating container and the metal member,
It is possible to firmly attach the metal member to the insulating container without causing cracks or breaks in the insulating container.

【0011】[0011]

【実施例】次に本発明を実施例に基づき詳細に説明す
る。図1 及び図2 は本発明の半導体素子収納用パッケー
ジの一実施例を示し、1 は電気絶縁材料から成る絶縁基
体であり、2 は蓋体である。この絶縁基体1 と蓋体2 と
で半導体素子3 を収容するための容器4 が構成される。
EXAMPLES Next, the present invention will be described in detail based on examples. 1 and 2 show one embodiment of a package for housing a semiconductor device of the present invention, 1 is an insulating base made of an electrically insulating material, and 2 is a lid. The insulating base 1 and the lid 2 form a container 4 for housing the semiconductor element 3.

【0012】前記絶縁基体1はその上面に半導体素子3
を収容するための凹部1aを有し、該凹部1a底面には半導
体素子3 がガラス、樹脂、ロウ材等の接着剤を介して接
着固定される。
The insulating substrate 1 has a semiconductor element 3 on its upper surface.
The semiconductor element 3 is bonded and fixed to the bottom surface of the recess 1a through an adhesive such as glass, resin, or brazing material.

【0013】前記絶縁基体1 は酸化アルミニウム質焼結
体から成り、例えばアルミナ(Al 2O 3 ) 、シリカ(SiO
2 ) 、カルシア(CaO) 、マグネシア(MgO) 等に適当な有
機溶剤、溶媒を添加混合して泥漿状となすとともにこれ
を従来周知のドクターブレード法やカレンダーロール法
を採用することによってセラミックグリーンシート(セ
ラミック生シート) を形成し、しかる後、前記セラミッ
クグリーンシートに適当な打ち抜き加工を施すとともに
複数枚積層し、高温( 約1600℃) で焼成することによっ
て製作される。
The insulating substrate 1 is made of an aluminum oxide sintered body, such as alumina (Al 2 O 3 ) or silica (SiO 2 ).
2 ), calcia (CaO), magnesia (MgO), etc., by adding and mixing an appropriate organic solvent and solvent to form a slurry, and by adopting the conventionally known doctor blade method or calendar roll method, a ceramic green sheet (Ceramic green sheet) is formed, and thereafter, the ceramic green sheet is appropriately punched, laminated with a plurality of sheets, and fired at a high temperature (about 1600 ° C.).

【0014】また前記絶縁基体1 には凹部1a周辺部から
容器4 の外部にかけて導出する複数個のメタライズ配線
層5 が形成されており、該メタライズ配線層5 の凹部1a
周辺部側には半導体素子3 の各電極がボンディングワイ
ヤ6 を介して電気的に接続され、また容器4 の外部に導
出された部位には外部電気回路と接続される外部リード
端子7 が銀ロウ等のロウ材を介し取着されている。
A plurality of metallized wiring layers 5 extending from the periphery of the recess 1a to the outside of the container 4 are formed on the insulating base 1, and the recesses 1a of the metallized wiring layer 5 are formed.
Electrodes of the semiconductor element 3 are electrically connected to the peripheral side via bonding wires 6, and external lead terminals 7 connected to an external electric circuit are connected to an external electrical circuit at a portion led out of the container 4 with silver solder. It is attached through a brazing material such as.

【0015】前記メタライズ配線層5 は半導体素子3 の
各電極を外部リード端子7 に電気的に接続させる作用を
為し、タングステン、モリブデン、マンガン等の高融点
金属粉末から成り、該高融点金属粉末に適当な有機溶
剤、溶媒を添加混合して得た金属ペーストを従来周知の
スクリーン印刷法等の厚膜手法を採用し、絶縁基体1 と
成るセラミックグリーンシートに予め印刷塗布しておく
ことによって絶縁基体1の凹部1a周辺部から容器4 の外
部にかけて導出するよう被着形成される。
The metallized wiring layer 5 serves to electrically connect the electrodes of the semiconductor element 3 to the external lead terminals 7 and is made of a refractory metal powder such as tungsten, molybdenum, or manganese. Insulation is performed by applying a suitable organic solvent, a metal paste obtained by adding and mixing the solvent to a ceramic green sheet that becomes the insulating substrate 1 in advance by applying a thick film method such as the well-known screen printing method. It is formed so as to be led out from the periphery of the recess 1a of the base 1 to the outside of the container 4.

【0016】尚、前記メタライズ配線層5 はその露出す
る表面にニッケル、金等の耐蝕性に優れ、且つロウ材と
の濡れ性が良い金属を1.0 乃至20.0μm の厚みにメッキ
法により層着させておくと、メタライズ配線層5 の酸化
腐食を有効に防止することができるとともにメタライズ
配線層5 への外部リード端子7 のロウ付けを強固となす
ことができる。従って、前記メタライズ配線層5 にはそ
の露出する表面にニッケル、金等を1.0 乃至20.0μm の
厚みに層着させておくことが好ましい。
The metallized wiring layer 5 is formed by depositing a metal such as nickel or gold, which has excellent corrosion resistance and wettability with a brazing material, to a thickness of 1.0 to 20.0 μm on the exposed surface by a plating method. This makes it possible to effectively prevent oxidative corrosion of the metallized wiring layer 5 and to firmly braze the external lead terminals 7 to the metallized wiring layer 5. Therefore, it is preferable to deposit nickel, gold or the like on the exposed surface of the metallized wiring layer 5 to a thickness of 1.0 to 20.0 μm.

【0017】また前記絶縁基体1 はその下面にメタライ
ズ金属層8 が被着されており、該メタライズ金属層8 に
は金属部材9 が接合材10を介して取着されている。
A metallized metal layer 8 is attached to the lower surface of the insulating substrate 1, and a metal member 9 is attached to the metallized metal layer 8 via a bonding material 10.

【0018】前記メタライズ金属層8 は金属部材9 を絶
縁基体1 に取着するための下地金属層として作用し、タ
ングステン、モリブデン、マンガン等の高融点金属粉末
により形成されている。
The metallized metal layer 8 acts as a base metal layer for attaching the metal member 9 to the insulating substrate 1, and is made of a refractory metal powder such as tungsten, molybdenum or manganese.

【0019】前記メタライズ金属層8 はメタライズ配線
層4 と同様の方法、具体的にはタングステン等の粉末に
適当な有機溶剤、溶媒を添加混合して得た金属ペースト
を従来周知のスクリーン印刷法等の厚膜手法を採用し、
絶縁基体1 と成るセラミックグリーンシートに予め印刷
塗布しておくことによって絶縁基体1 の下面に被着形成
される。
The metallized metal layer 8 is formed by the same method as that for the metallized wiring layer 4, specifically, a metal paste obtained by adding an appropriate organic solvent to a powder of tungsten or the like and mixing the solvent with a conventionally known screen printing method or the like. Adopting the thick film method of
The ceramic green sheet to be the insulating substrate 1 is printed and applied in advance to be adhered and formed on the lower surface of the insulating substrate 1.

【0020】また前記メタライズ金属層8 に取着される
金属部材9 はコバール金属やインバー合金等を含む金属
材によって形成されており、該金属部材9 は半導体素子
3 の発する熱膨張係数を良好に吸収するとともに大気中
に放散し、半導体素子3 が熱破壊したり、特性に変化を
来し誤動作したりするのを防止する作用を為す。
The metal member 9 attached to the metallized metal layer 8 is formed of a metal material containing Kovar metal, Invar alloy, or the like, and the metal member 9 is a semiconductor element.
The thermal expansion coefficient generated by 3 is satisfactorily absorbed and is diffused into the atmosphere to prevent the semiconductor element 3 from being thermally destroyed or having its characteristics changed and malfunctioning.

【0021】前記金属部材9 は例えば図2(a)に示す如
く、コバール金属もしくはインバー合金から成る板材9a
を2 枚の銅板9bで上下から挟んだ構造のもの、或いは図
2(b)に示す如く、コバール金属もしくはインバー合金か
ら成り、複数個の貫通孔を有する2 枚の金属板9c、9c間
に銅部材9dをその一部が前記金属板9cに設けた貫通孔内
に圧入された状態で挟持された構造のものが好適に使用
される。
The metal member 9 is, for example, as shown in FIG. 2A, a plate member 9a made of Kovar metal or Invar alloy.
With two copper plates 9b sandwiched from above and below, or
As shown in 2 (b), two metal plates 9c, 9c made of Kovar metal or Invar alloy and having a plurality of through holes, a copper member 9d is partially provided in the metal plate 9c. A structure having a structure in which it is sandwiched while being press-fitted therein is preferably used.

【0022】尚、前記図2(a)に示される金属部材9 は例
えば、鉄54.0重量%、ニッケル29.0重量%、コバルト17
重量%の合金からなるコバール金属9aの上下に銅板9bを
載置するとともにこれを圧延ローラにかけ、両板を150K
g/cm2 以上の圧力で押圧することによって製作され、ま
た図2(b)に示される金属部材9 は例えば、銅部材9dの上
下に複数個の貫通孔を有するコバール金属板9cを配し、
しかる後、これを150Kg/cm2 以上の圧力で圧延し、銅部
材9dの一部をコバール金属板9cの貫通孔内に圧入させる
ことによって製作される。
The metal member 9 shown in FIG. 2 (a) is, for example, iron 54.0% by weight, nickel 29.0% by weight, cobalt 17
A copper plate 9b is placed on the top and bottom of a Kovar metal 9a made of a weight% alloy, and this is put on a rolling roller.
The metal member 9 shown in FIG. 2 (b) is manufactured by pressing with a pressure of g / cm 2 or more.For example, a Kovar metal plate 9c having a plurality of through holes is arranged above and below a copper member 9d. ,
After that, this is rolled at a pressure of 150 Kg / cm 2 or more, and a part of the copper member 9d is press-fitted into the through hole of the Kovar metal plate 9c to manufacture.

【0023】また前記金属部材9 はコバール金属やイン
バー合金等を含む金属材によって形成されていることか
らその熱膨張係数が5.6 〜7.6 ×10-6/ ℃となり、絶縁
基体1 を構成する酸化アルミニウム質焼結体の熱膨張係
数に近似する。そのため絶縁基体1 と金属部材9 に半導
体素子3 が作動時に発生する熱が印加されたとしても両
者の取着部には大きな熱応力が発生することはなく、絶
縁基体1 にクラックや割れ等が発生することもない。
Further, since the metal member 9 is formed of a metal material containing Kovar metal, Invar alloy, etc., its coefficient of thermal expansion is 5.6 to 7.6 × 10 −6 / ° C., and the aluminum oxide forming the insulating substrate 1 is formed. It is close to the coefficient of thermal expansion of the quality sintered body. Therefore, even if heat generated during the operation of the semiconductor element 3 is applied to the insulating base 1 and the metal member 9, no large thermal stress is generated in the attachment portion between the two, and the insulating base 1 is not cracked or broken. It does not occur.

【0024】更に前記金属部材9 は絶縁基体1 の下面に
被着させたメタライズ金属層8 に接合材10を介して取着
され、これによって金属部材9 は絶縁基体1 に取着され
ることとなる。
Further, the metal member 9 is attached to the metallized metal layer 8 adhered to the lower surface of the insulating substrate 1 via the bonding material 10, whereby the metal member 9 is attached to the insulating substrate 1. Become.

【0025】前記金属部材9 を絶縁基体1 のメタライズ
金属層8 に取着させる接合材10としては金ースズロウ材
やアルミニウムーシリコンロウ材等が好適に使用され、
該金ースズロウ材やアルミニウムーシリコンロウ材はそ
の溶融温度が金属部材9 に含まれているコバール金属や
インバー合金の変移点より低い温度であるため金属部材
9 を絶縁基体1 に被着させたメタライズ金属層8 に接合
材10を介して取着させる際、金属部材9 が絶縁基体1 に
比較して大きく熱膨張することはなく、その結果、両者
の取着部に大きな熱応力が発生することはなく、絶縁基
体1 にクラックや割れ等が発生するのを皆無として金属
部材9 を絶縁基体1 に極めて強固に取着させることが可
能となる。
As the bonding material 10 for attaching the metal member 9 to the metallized metal layer 8 of the insulating substrate 1, a gold-based solder material or an aluminum-silicon solder material is preferably used.
Since the melting temperature of the gold-based solder material and the aluminum-silicon solder material is lower than the transition point of the Kovar metal or Invar alloy contained in the metal member 9,
When 9 is attached to the metallized metal layer 8 adhered to the insulating base 1 via the bonding material 10, the metal member 9 does not undergo a large thermal expansion as compared with the insulating base 1, and as a result, both No large thermal stress is generated in the attachment portion, and it is possible to attach the metal member 9 to the insulating substrate 1 extremely firmly without any cracks or fractures in the insulating substrate 1.

【0026】尚、前記接合材10は上述の金ースズロウ材
やアルミニウムーシリコンロウ材に限定されるものでは
なく、溶融温度が金属部材9 に含まれているコバール金
属やインバー合金の変移点より低い温度であればいかな
る材質のロウ材であってもよく、またエポキシ樹脂やガ
ラスポリイミド等の熱硬化温度が金属部材9 に含まれて
いるコバール金属やインバー合金の変移点より低い温度
の樹脂接着材であってもよい。接合材10がエポキシ樹脂
等の樹脂接着材から成る場合には絶縁基体1 にメタライ
ズ金属層8 を予め被着させておく必要はなく、絶縁基体
1 の下面に金属部材9 を直接接合材10を介して取着すれ
ばよい。
The joining material 10 is not limited to the above-described gold-based brazing material or aluminum-silicon brazing material, and its melting temperature is lower than the transition point of the Kovar metal or Invar alloy contained in the metal member 9. Any brazing material may be used as long as it has a temperature, and a resin adhesive having a thermosetting temperature of epoxy resin, glass polyimide or the like lower than the transition point of the Kovar metal or Invar alloy contained in the metal member 9. May be When the bonding material 10 is made of a resin adhesive such as epoxy resin, it is not necessary to deposit the metallized metal layer 8 on the insulating base 1 in advance.
The metal member 9 may be directly attached to the lower surface of 1 via the bonding material 10.

【0027】かくして上述の半導体素子収納用パッケー
ジは絶縁基体1 の凹部1a底面に半導体素子3 をガラス、
樹脂、ロウ材等の接着剤を介して接着固定するとともに
半導体素子3 の各電極をメタライズ配線層5 にボンディ
ングワイヤ6 を介して接続し、しかる後、絶縁基体1 の
上面に蓋体2 をガラス、樹脂、ロウ材等の封止材を介し
て接合さて、絶縁基体1 と蓋体2 とから成る容器4 内部
に半導体素子3 を気密に収容することによって製品とし
てき半導体装置となる。
Thus, in the above-mentioned package for accommodating semiconductor elements, the semiconductor element 3 is made of glass on the bottom surface of the concave portion 1a of the insulating substrate 1.
The electrodes of the semiconductor element 3 are connected to the metallized wiring layer 5 via the bonding wires 6 while being adhered and fixed via an adhesive such as resin or brazing material, and then the lid 2 is attached to the upper surface of the insulating substrate 1 by glass. The semiconductor element 3 is joined by a sealing material such as resin or a brazing material, and the semiconductor element 3 is hermetically housed in the container 4 including the insulating base 1 and the lid 2.

【0028】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.

【0029】[0029]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁容器の外表面にコバール金属もしくはイン
バー合金を含む金属部材を、該コバール金属もしくはイ
ンバー合金の変移点以下の温度で溶融もしくは熱硬化す
る接合材を介して取着させたことから絶縁容器と金属部
材との間には大きな熱応力が発生することはなく、絶縁
容器にクラックや割れ等が発生するのを皆無として絶縁
容器に金属部材を強固に取着することが可能となる。従
って、本発明の半導体素子収納用パッケージは内部に収
容する半導体素子の気密封止が完全となり、半導体素子
を長期間にわたり正常、且つ安定に作動させることが可
能となる。
According to the package for housing a semiconductor device of the present invention, a metal member containing Kovar metal or Invar alloy is melted or heated at a temperature below the transition point of the Kovar metal or Invar alloy on the outer surface of the insulating container. Since it is attached via a hardening bonding material, no large thermal stress is generated between the insulating container and the metal member, and there is no crack or breakage in the insulating container. It becomes possible to firmly attach the metal member. Therefore, in the semiconductor element housing package of the present invention, the semiconductor element housed inside is completely hermetically sealed, and the semiconductor element can be operated normally and stably for a long period of time.

【0030】また絶縁容器に金属部材が強固に取着され
ているため半導体素子が作動時に多量の熱を発したとし
ても該熱は金属部材を介して大気中に良好に放散され、
その結果、半導体素子は常に低温となり、これによって
も半導体素子を長期間にわたり正常、且つ安定に作動さ
せることが可能となる。
Further, since the metal member is firmly attached to the insulating container, even if a large amount of heat is generated during operation of the semiconductor element, the heat is well dissipated into the atmosphere through the metal member,
As a result, the semiconductor element is always at a low temperature, which also allows the semiconductor element to operate normally and stably for a long period of time.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【図2】(a)(b)は図1に示すパッケージに使用される金
属部材を説明するための部分斜視図である。
2A and 2B are partial perspective views for explaining a metal member used in the package shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 2・・・・・蓋体 3・・・・・半導体素子 4・・・・・容器 9・・・・・金属部材 10・・・・・接合材 1 ... Insulating substrate 2 ... Lid 3 ... Semiconductor element 4 ... Container 9 ... Metal member 10 ... Bonding material

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体素子を収容する絶縁容器の外表面に
コバール金属もしくはインバー合金を含む金属部材を、
該コバール金属もしくはインバー合金の変移点以下の温
度で溶融もしくは熱硬化する接合材を介して接合取着さ
せたことを特徴とする半導体素子収納用パッケージ。
1. A metal member containing Kovar metal or Invar alloy on the outer surface of an insulating container for housing a semiconductor element,
A package for accommodating a semiconductor device, characterized in that the semiconductor device is bonded and attached through a bonding material that melts or thermosets at a temperature below the transition point of the Kovar metal or Invar alloy.
JP4309154A 1992-11-19 1992-11-19 Package for housing semiconductor element Pending JPH06163736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4309154A JPH06163736A (en) 1992-11-19 1992-11-19 Package for housing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4309154A JPH06163736A (en) 1992-11-19 1992-11-19 Package for housing semiconductor element

Publications (1)

Publication Number Publication Date
JPH06163736A true JPH06163736A (en) 1994-06-10

Family

ID=17989574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4309154A Pending JPH06163736A (en) 1992-11-19 1992-11-19 Package for housing semiconductor element

Country Status (1)

Country Link
JP (1) JPH06163736A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58101446A (en) * 1981-12-11 1983-06-16 Hitachi Ltd Semiconductor device
JPH0247054B2 (en) * 1981-05-21 1990-10-18 Energy Support Corp
JPH0471256A (en) * 1990-07-11 1992-03-05 Kyocera Corp Preparation of heat sink

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0247054B2 (en) * 1981-05-21 1990-10-18 Energy Support Corp
JPS58101446A (en) * 1981-12-11 1983-06-16 Hitachi Ltd Semiconductor device
JPH0471256A (en) * 1990-07-11 1992-03-05 Kyocera Corp Preparation of heat sink

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