JPH0616228B2 - Display controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention is equipped with a plasma display unit as a standard, for example, a personal computer, a personal workstation, etc. to which a color display unit can be arbitrarily connected. The present invention relates to a display control device suitable for use in constructing the computer system of FIG.

(Prior Art) Conventionally, in a computer system such as a personal computer or a personal workstation in which a plasma display unit is standard equipment and a color display unit can be arbitrarily connected, when the data to be handled has a color element, the plasma It was impossible to express data by color in the display by the display unit.

Further, conventionally, when performing gradation display in a plasma display, display information is provided with gradation by thinning out display dots, blinking, etc. However, such a so-called pseudo gradation display means is used in a color display. There is a problem that it is not possible to make a clear divisional display such as a color-coded display.

(Problems to be Solved by the Invention) As described above, in the conventional system in which the plasma display unit is provided as standard equipment and the color display unit can be arbitrarily connected, the data displayed in different colors on the color display is plasma-displayed. There is a problem in that it is not possible to clearly display on the display.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display control device capable of displaying data having color-specific display elements handled by a color display in gray scale on the plasma display in association with colors.

Further, the present invention provides a display control device in which a color display and a plasma display that performs gradation display corresponding to a display color on the display are realized by using a single display control and a palette in common. With the goal.

[Structure of the Invention] (Means and Actions for Solving Problems) The present invention relates to a plasma display unit and a display control device for arbitrarily controlling the display drive of a color display unit. Alternatively, a single CRT controller in which the display timing parameter of either plasma display device is set, and a single CRT controller in which the display color conversion palette data of the CRT display device or the gradation display palette data of the plasma display device are set. One palette,
Means for selecting one of the CRT display device and the plasma display device as a display drive target, and the CR according to the selected display drive target
The display timing parameter of the T controller and a means for rewriting the palette data on the palette are provided, and the display drive control of the CRT display device and the plasma display device is performed by a single CRT controller and the palette. As a result, a single display controller and pallet are commonly used for the display drives of the above-mentioned displays, effective use of the hardware is achieved, and a color display element handled by the color display is provided by a simple and inexpensive hardware configuration. Data can be displayed in gradation on the plasma display in correspondence with colors.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, 11 and 12 are palette data buffers that store palette data under the control of the CPU that controls the system. Of these, 11 is a palette data buffer for color CRT displays (hereinafter referred to as the palette data buffer stored in the main memory). Reference numeral 12 is a CRT palette data buffer, and reference numeral 12 is a plasma display palette data buffer (hereinafter referred to as PDP palette data buffer) also placed on the main memory.

Reference numeral 13 is a palette in which palette data corresponding to the display currently in use is set under the control of the CPU, and color conversion or color-to-gradation conversion is performed according to the palette data. The color CRT display is a drive target. When the plasma display is driven, the palette data stored in the PDP palette data buffer 12 is set and the bullet data stored in the CRT palette data buffer 11 is set. When palette data is set, color conversion of [16 colors → 64 colors] is performed. When palette data for PDP is set [16 colors → 4 gradations] colors →
Performs gradation conversion.

14 is a video RAM for storing display data (hereinafter referred to as V-RAM
Is called), and has a 4-plane (16 colors) structure here.

15 is the default value of CRT palette (D / CRT),
And a PROM pallet default value (D PDP).

A color C 20 receives the display data in 6-bit units color-converted by the palette 13 and displays 64 colors.
An RT display device (hereinafter simply referred to as a CRT) 30 is a plasma display device (hereinafter simply referred to as a gray scale display device) that receives display data in units of 2 bits, which are color-gradated by the palette 13, and performs gradation display of 4 gradations. (Referred to as PDP)
Is.

Reference numeral 30A is a PDPD interface circuit that generates display data matching the input interface of the PDP 30, and a specific configuration example thereof is shown in FIG.

40 is C according to the display timing signal generation parameter (PD) set in the internal display timing register 40R.
C for selectively controlling display drive of RT20 and PDP30
An RT controller (hereinafter referred to as CRTC). Reference numeral 50 is a timing parameter setting control circuit for setting a display timing signal generation parameter (PD) in the CRTC 40 under the control of the CPU, and a specific configuration example thereof is shown in FIG.

FIG. 2 shows the palette data buffers 11, 12 and V- mentioned above.
It is a figure which shows the memory map by address allocation in a system, such as RAM14 and BIOS * ROM15.

FIG. 3 shows the structure of the pallet 13 described above, which is a CRT.
6-bit display data (R, G, B, S sent to 20
R, SG, SB), SR, SG, SB are R, G,
B auxiliary bit. Here, of the 6-bit display data (R, G, B, SR, SG, SB), R
Two bits of (RED) and G (GREEN) are introduced to the PDP interface circuit 30A shown in FIG. 4 as PDP display data.

FIG. 4 is a circuit block diagram showing a circuit configuration of the PDP interface circuit 30A. R (RED) and G (GREE) input from the palette 13 shown in FIG.
N) 2-bit display data for PDP is serial-parallel conversion circuits (S → P) 31 and 32, and 4-bit data (for four consecutive pixels) (PH1 to PH4, PL).
1 to PL4), and the display panel (PDP main body) is supplied as 8-bit 4-gradation display data via a 4-gradation display drive circuit (not shown).

FIG. 5 is a circuit block diagram showing the configuration of the timing parameter setting control circuit 50 for setting the display timing parameter in the CRTC 40. When the display timing setting signal (A = “1”) is supplied from the CPU, the CRTC 40 takes in the display timing signal generation parameter (PD) for the display mode to be newly set via the bus 41 to display the internal display timing. Set in register 40R and display timing signal (D
The display data is sent to the PDP 30 by the timing control according to D). At this time, the flip-flop 42 sends the CPU data (E / D; “1” = enable,
"0" = disabled) is latched in synchronization with the latch timing signal C. Further, the AND gate 43 flips the flip-flop 42 when the flip-flop 42 is in the reset state (Q = "0"), that is, the CPU data (E / D) "0".
When 42 holds, display timing setting signal (A =
The output of "1") is prohibited, and when the flip-flop 42 is in the set state ("1"), the prohibition is released.

FIG. 6 is a flowchart showing the display processing flow of the above embodiment.

The operation of the embodiment will now be described with reference to FIGS.

When the system starts up when the power is turned on, first the CP
Under the control of U. PD stored in ROM15
Default value of P pallet and CRT pallet (D
(CRT, D.PDP) are loaded into the CRT palette data buffer 11 and the PDP palette data buffer 12 in the main memory (step S1 in FIG. 6).

Here, when no selection designation command for the display is input or when a new selection designation command for the PDP 30 is input, the palette data stored in the PDP palette data buffer 12 is loaded into the palette 13. The display data stored in the V-RAM 14 is subjected to color conversion of [16 colors → 4 gradations] → gradation by the same palette data and then supplied to the PDP 30 for display (step S2 in FIG. 6). S3).

At this time, as the data is loaded into the pallet 13, the CP
Control circuit 50 for timing parameter setting under the control of U
The corresponding display target (here, PD
P30) display timing signal generation parameter (PD)
Is set in the display timing register 40R of the CRTC 40. That is, the CRTC 40 is the AND gate 43 shown in FIG.
When the display timing setting signal (A = "1") sent from the CPU is received via the bus, the display timing signal generation parameter (PD) for the display mode to be newly set is set to the bus 41.
The display data is read in from the V-RAM 14 by the timing control according to the display timing signal (DD) generated by the same parameter (PD) and sent to the PDP 30.
At this time, the flip-flop 42 that controls the opening and closing of the AND gate 43 causes the CPU data (E / E) sent from the CPU.
D; “1” = enable, “0” = disable) in synchronization with the latch timing signal C. In the AND gate 43, the flip-flop 42 is in the reset state (Q =
"0"), that is, CPU data (E / D)
When the flip-flop 42 holds “0”, the output of the display timing setting signal (A = “1”) is monitored, and when the flip-flop 42 is in the set state (“1”), the above-mentioned prohibition is performed. To release.

Thus, the timing control of the timing parameter setting control circuit 50 under the control of the CPU in accordance with the data loading to the pallet 13 (and the switching of the display target to be described later) allows the corresponding display target (PDP30 / CRT20) to be displayed. The display timing signal generation parameter (PD) is set in the display timing register 40R of the CRTC 40, and the display data is read from the V-RAM 14 by the timing control according to the display timing signal (DD) generated by the parameter (PD).

Here, R (RED) shown in FIG. 3 which is read from the V-RAM 14 and converted by the palette 13 [16 colors → 4 gradations]
2-bit PDP display data of G and G (GREEN) is the interface circuit 30A of the PDP 30 shown in FIG.
To the serial-parallel conversion circuit (S
→ P) 4 bits for 31 and 32 (4 consecutive pixel units)
Data (PH1 to PH4, PL1 to PL4) and is supplied to the display panel (PDP main body) as a display data of a total of 8 bits of 4 pixels and 4 gradations through a 4 gradation display drive circuit (not shown). . Here, when the 2-bit PDP display data (R, G) output from the palette 13 is "0, 0", the Y electrode drive 1H
The discharge pulse width for the period is set to the lowest with a duty ratio of 10%, followed by 40% when "0, 1" and when "1, 0"
70%, 100% when "1,1".

In the display mode using the PDP 30, when a command and palette data for changing the correspondence between color and gradation are input by the user, the contents of the palette 13 are controlled under the control of the CPU. The data is rewritten according to the input data, and thereafter, the [16 colors → 4 gradations] color → gradation conversion is performed according to the rewritten PDP palette data (6th color).
(Steps S4, S5).

When a command for switching the display device to be used from the PDP 30 to the CRT 20 is input by the user's designation, the CPT palette data buffer 11 is read-accessed under the control of the CPU, and the contents of the palette 13 are changed. It is rewritten according to the CRT palette data read from the palette data buffer 11, and thereafter, V-RAM 14
The display data read by the CRT is the rewritten CRT.
[16 colors → 94 colors] is color-converted according to the palette data for display, and then displayed on the CRT 20 (step S6 in FIG. 6).
S8) At this time, the display target is switched (in accordance with PDP30 → CRT20, the corresponding display target (here, CRT20) is displayed by the timing control of the timing parameter setting control circuit 50 under the control of the CPU as described above. The timing signal generation parameter (PD) is set in the display timing register of the CRTC 40, and the display data is read from the V-RAM 14 by the timing control according to the display timing signal (DD) generated by the parameter (PD).

In the display mode by the CRT 20, when a palette color change instruction command and palette selection designation information for changing the color correspondence relationship of [16 colors → 64 colors] are input by the user, the CPU Under the control, the rewriting process of the palette 13 is executed by the application software, and thereafter, the color conversion of [16 colors → 64 colors] is performed according to the palette color of the rewritten CRT palette data (step in FIG. 6). S9, S10).

Here, when a command to switch the display device to be used from the CRT 20 to the PDP 30 is input by the user's designation, the PDP palette data buffer 12 is read-accessed under the control of the CPU, and the contents of the palette 13 are read. Is read from the pallet data buffer 12 and the PDP
Is rewritten according to the pallet data for V-RAM
Display data read from 14, the rewritten PD
The color of [16 colors → 4 gradations] → gradation conversion is performed according to the P palette data and then displayed on the PDP 30 (steps S11, S2, S3, ... In FIG. 6).

At this time, the display timing of the corresponding display target (here, PDP30) is also controlled by the timing control of the timing parameter setting control circuit 50 under the control of the CPU as described above in accordance with the switching of the display target (CRT20 → PDP30). The signal generation parameter (PD) is set in the display timing register 40R of the CRTC 40, and the display data is read from the V-RAM 14 by the timing control according to the display timing signal (DD) generated by the parameter (PD).

In this way, the pallet 1 common to the CRT 20 and the PDP 30
Using 3 and the CRTC 40, information displayed by color on the CRT 20 can be displayed on the PDP 30 in multiple gradations in correspondence with any color → gradation.

In the above embodiment, the example of color conversion of [16 colors → 4 gradations] → gradation is shown, but other colors such as [16 colors → 8 gradations], [64 colors → 16 gradations], etc. Even in the case of gradation conversion, display data having color-specific display elements handled by the color CRT display unit can be displayed in gradation on the plasma display (PDP) in association with the colors. In addition, in the above-mentioned embodiment, the case where the CRT display and the plasma display are used as the display device has been described, but it goes without saying that the present invention can be applied to any flat panel display such as a liquid crystal display instead of the plasma display.

[Effects of the Invention] As described in detail above, according to the present invention, in the display control device for selectively controlling the display drive of the plasma display unit and the color display unit, either the CRT display device or the plasma display device. A single CRT controller in which one of the display timing parameters is set; a single palette in which display color conversion palette data of the CRT display device or gradation display palette data of the plasma display device is set; Means for selecting either the CRT display device or the plasma display device as a display drive target, and a means for rewriting the display timing parameter of the CRT controller and the palette data on the palette according to the selected display drive target Since the display drive control of the CRT display device and the plasma display device is performed by a single CRT controller and palette, the display drive of each display of the single display controller and palette is common. It is possible to display the gradation of the data having the display element for each color handled by the color display in association with the color on the plasma display with a simple and inexpensive hardware configuration by effectively using the hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a memory map on the system in the above embodiment, and FIG. 3 is a configuration of the pallet in the above embodiment. FIG. 4 is a block diagram showing the configuration of the PDP interface circuit in the above embodiment, and FIG. 5 is a circuit block diagram showing the configuration of the CRTC timing parameter setting control circuit in the above embodiment. FIG. 6 is a flow chart showing the display processing flow in the above embodiment. 11 …… CRT palette data buffer, 12 …… PDP
Palette data buffer, 13 ... Palette, 14 ... Video RAM (V-RAM), 15 ... BIOS / ROM,
20 ... Color CRT display device (CRT), 30 ...
… Plasma display device (PDP), 30A …… PD
P interface circuit, 31, 32 ... Serial-parallel conversion circuit (S → P), 40 ... Display controller (CR
TC), 40R ... display timing register, 41 ... bus, 42 ... flip-flop, 43 ... AND gate, 50
... Control circuit for timing parameter setting, D / PDP
...... Default value of PDP pallet, D / CRT ……
Default value of CRT palette, PD ... Display timing signal generation parameter, A ... Display timing setting signal, DD ... Display timing signal, E / D ... CPU data, C ... Latch timing signal.

Claims (1)

[Claims] 1. A flat panel display device is provided,
A display control method in a computer system capable of selectively connecting a CRT display device, comprising: pallet means for setting pallet data for the flat panel display device or pallet data for the CRT display device; According to a means for selecting one of a display device and a CRT display device, a means for setting palette data corresponding to the display device selected by the selecting means in the palette means, and a palette data set in the palette means. , The flat panel display device or CRT
And a control means for displaying display data on the display device.