JPH06161741A - Simplified instruction cache structuring method - Google Patents

Abstract

PURPOSE:To improve the speed of the whole microprocessor by structuring an instruction cache as a fast buffer memory which prereads a program. CONSTITUTION:When a cache counter address does not match a CPU address, the CPU address is set as the serial port head address of a VRAM 3 and the CPU address is set in a cache counter 5. After access by a CPU 1, a next instruction is prepared on a VRAM serial port on the side of a VRAM controller 4 and further a next cache address is prepared in the cache counter 5 on the side of a cache controller 9. If the cache address does not match the CPU address at the time of next instruction access, the CPU address is repeatedly set and when the cache address matches the CPU address, previous data in the VRAM 3 are regarded as the program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for constructing an instruction cache as a high speed buffer memory for prefetching a program in order to increase the overall processing speed of a microprocessor.

[0002]

2. Description of the Related Art Microprocessors sequentially read and execute programs stored in a memory. Generally, a large-capacity memory is slower than the microprocessor can read the program, and the program execution speed is reduced. I am A cache memory is used as a method for compensating for this. The cache memory method is a method of prefetching a part of a program being executed in a high-speed memory.

In the conventional method, in the case of mis-caching (when there is no execution program in the cache memory), a circuit for replacing the program in the cache memory and a cache hit (cache address and processor address) The circuit for detecting (when and match) was very complicated.

On the other hand, a program has continuity and is generally an instruction group arranged at consecutive addresses on a memory. Therefore, if there is no instruction branch, the instruction next to the one just read is: It should be located at the address next to the current instruction address.

As a characteristic of VRAM (video ram), V
RAM is a DRAM having ports for serial access and random access. This serial access port can sequentially output the data on the continuous memory from this address once the address is set.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to construct an instruction cache as a high-speed buffer memory for prefetching a program in order to increase the overall processing speed of a microprocessor, thereby increasing the overall speed of the microprocessor.

[0007]

Based on the above object, the present invention is a combination of program continuity and VRAM serial access port characteristics, and can be realized in a small-scale circuit without using an expensive high-speed memory. When the cash counter address and the CPU address do not match, the CP is added to the VRAM serial port start address.
The U address is set, and the CPU address is set as the cache counter address. After the access by the CPU, the VRAM controller prepares the next instruction in the VRAM serial port, and the cache controller prepares the next cache address in the cache counter. If the next instruction is at the next address as described in the continuity of the program, the CPU address and the cache address match, so the instruction of the VRAM serial port is immediately read. After that, it is done again. If the next command does not match, it will be reset. This is a method for constructing a simple instruction cache including the steps described above, thereby increasing the overall processing speed of the microprocessor.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the overall system configuration.
The CPU 1 is a microprocessor that can be asynchronously accessed and can know whether it is program access or not, for example, MC68030, and is connected to the VRAM 3, the DRAM controller 4, the cache counter 5, and the address comparator 6 by the CPU address bus 2. .

The VRAM 3 is called a video RAM, has a port S (I / O) for serially inputting / outputting data and a port P (I / O) for random access, and is connected to the CPU 1 by a data bus 7. Therefore, data access can be performed by the DRAM controller 4. The address comparator 6 and the cash counter 5 are connected by a cash address bus 8. The cache controller 9 connected to the address comparator 6 controls the VRAM 3, the DRAM controller 4, and the cash counter 5.

Random access port P of VRAM 3
Is the same as a normal memory, except that the serial port S
Is a port that can sequentially output data if a head address is designated, and enables high-speed operation in synchronization with a clock signal. However, the length of data that can be serially output is limited.

FIG. 2 shows the structure of the program.
The program is a group of serially consecutive instructions, and if one instruction A is not a branch instruction, the next instruction B is
Is stored at the address (n + 3) next to the address (n + 2). Therefore, the instruction B is executed next to the instruction A.

FIG. 3 shows a flowchart of the cashing operation in the above system. After the program access in the CPU 1 is started, first, the address comparator 6
Cash address from cash counter 5 and CPU 1
The CPU addresses from the above are compared to confirm their inconsistent states. Here, the DRAM controller 4
Sets the CPU address to the VRAM serial port start address. The cash controller 9 also sets the CPU address in the cash counter 5.

After the CPU access is completed, the DRAM controller 4 prepares the next address data on the VRAM serial access port. In addition, the cash counter 5 is instructed by the cash controller 9 to
The next cash address is prepared in the cash counter 5.

During this time, the CPU 1 executes program instructions. After the instruction is completed, when the CPU makes the next access,
The address comparator 6 compares the cache address with the CPU address, returns to the previous step for matching when they do not match, and sets the CPU address in the VRAM serial port start address and the cache counter. In the comparison process, if the addresses of both parties match, C
PU1 uses the data in the VRAM in advance as a program.

[0015]

According to the present invention, the instruction cache is used as a high-speed buffer memory for prefetching a program in order to increase the speed of the entire microprocessor.
It is possible to construct an instruction cache with an inexpensive and simple circuit, and a short recovery time when the cache counter is missed.

[Brief description of drawings]

FIG. 1 is a block diagram of a system for implementing a simplified instruction cache building method.

FIG. 2 is an explanatory diagram of a program.

FIG. 3 is a flowchart of the operation of the simple cash.

[Explanation of symbols]

 1 CPU 2 CPU address bus 3 VRAM 4 DRAM controller 5 cash counter 6 address comparator 7 data bus 8 cash address bus 9 cash controller

Claims (1)

[Claims] 1. A method of combining program continuity and VRAM serial access port characteristics, which is a method that can be realized by a small-scale circuit without using an expensive high-speed memory. When the address does not match, CP is added to the VRAM serial port start address.
The U address is set, and the CPU address is set as the cache counter address. After the CPU access, the VRAM controller side prepares the next instruction in the VRAM serial port, and the cache controller side prepares the next cache address in the cache counter. If the next instruction is at the next address as described in the continuity of the program, the CPU address and the cache address match, so the instruction of the VRAM serial port is immediately read. After that, it is done again. If the next command does not match, it will be reset. A method for constructing a simplified instruction cache, comprising the above steps.