JPH06161709A - Device and method for key extraction, sorting processor, and data base processor - Google Patents

Abstract

PURPOSE:To obtain the key extracting device which can take a key out of data at a high speed. CONSTITUTION:The device is equipped with a main storage device 1, the data input part 2 of the key extracting device, a data writing control circuit 3 which generates a timing signal for writing data in a data memory 5, and the data memory 5 wherein the data writing timing signal 4 and data on the main storage device 1 are written. Further, the device is equipped with a processor 6 which performs the movement of data, a sorting process, etc., a key memory 7 wherein a key part is extracted from a record written in the data memory 5 and written, and a key writing control circuit 8 which generates a key writing timing signal 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sort processing device for performing sort processing using a key, for example.

[0002]

2. Description of the Related Art FIG. 16 is a block diagram showing a conventional key extracting device. The conventional key extraction device is the main storage device 1.
And a data input unit 2. The data write control circuit 3 generates a timing signal 4 for writing data in the data memory 5. The data memory 5 writes the data in the main memory 1. The processor 6 executes data movement, sort processing, and the like. The key memory 7 extracts and writes the key portion from the record written in the data memory 5.

Next, the operation will be described. Main memory 1
Above, a plurality of fixed-length records including a key portion are arranged in order at the same position. In FIG. 16, one record is 7
It shows a fixed length record composed of words.
Also, in each record, the key portion is shown as an example in which it is located at the same location from the second word to the fourth word. Each record is input from the main storage device 1 to the data input unit 2 of the key extracting device. The data write control circuit 3 generates the data write timing signal 4. The input records are sequentially written in the data memory 5 at the timing of the data write timing signal 4. When the writing of one record to the data memory 5 is completed, the processor 6 extracts the key portion from the content of the record written to the data memory 5 and reads it. And processor 6
Writes the read key portion in the key memory 7. After that, the processor 6 uses the contents of the key memory 7 to execute a sort process.

[0004]

The conventional key take-out device is constructed as described above. Therefore, the processor must be used to extract the key from the data memory. Therefore, the time required to extract the key is processor overhead. Due to this overhead, there is a problem that the processing speed is lowered.

The present invention has been made to solve the above problems. An object of the present invention is to obtain a key extracting device that can extract a key from data at high speed. Another object of the present invention is to obtain a key extracting method which can extract a key from data at high speed. Another object of the present invention is to obtain a sort processing device and a database processing device that can retrieve keys at high speed.

[0006]

A key extracting device according to the present invention has data input means for inputting records one by one and transferring the records to a storage location of the records. Further, it has a key storage means for storing only the key portion existing in the one record. In addition, in parallel with the input of one record by the data input means, there is provided a key writing means for taking out a key portion existing in the one record and writing it in the key storage means.

Further, the key extracting method according to the present invention has a data input step of sequentially inputting data. There is a determining step of determining whether or not the data sequentially input in the data input step is a key portion when the data input in the data input step is input. There is an extraction step of extracting the data determined to be the key portion based on the determination result of the determination step when the data is input in the data input step.

The sort processing apparatus and the database processing apparatus according to the present invention are processing apparatuses that utilize the above-mentioned key retrieval apparatus to retrieve keys and data at high speed.

[0009]

In the key extracting device according to the present invention, data is input record by record by the data input means. Further, the key storing means stores the key portion existing in one record. Further, in parallel with the input of one record by the data inputting means by the key writing means, only the key portion existing in the one record is taken out by the key writing means and written in the key storage means. The key extracting device according to the present invention can extract the key portion from the record at high speed by these means.

In the key extracting method according to the present invention, the determining step determines at the same time as inputting whether or not each data sequentially input in the data inputting step is a key portion. Therefore, the extraction process can extract the key portion at the same time as inputting the data.

Further, since the sort processing apparatus and the database processing apparatus according to the present invention retrieve the key and the data by utilizing the key retrieval apparatus, high speed processing can be performed.

[0012]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the data input section of the key extracting device of the present invention. In the figure, a key write control circuit 8 generates a key write timing signal 9. Other parts are the same as those in the above-mentioned example.

FIG. 2 is a diagram showing an internal circuit of the key write control circuit 8. In the figure, the record length register 81
Holds the length of one record. The key head relative address register 82 holds the value of the key head address as a relative address from the head of the record. The key end relative address register 83 holds the end address of the key as a relative address from the beginning of the record. The in-record data relative address counter 84 counts the address of the in-record data as a data relative address from the beginning of the record. The in-record data relative address counter 84 has an initial value of 0, and is incremented each time the data input from the main storage device 1 is written in the data memory, and is initialized to 0 each time the transfer of data for one record is completed. Become.

The comparator 85 has a key head address held in the key head relative address register 82, and
The data relative address held in the in-record data relative address counter 84 is compared. The comparator 85 sends out a coincidence signal when the comparison results coincide. The flip-flop 86 holds the coincidence signal output from the comparator 85 until the end of the processing of one record. The comparator 87 compares the key end address held in the key end relative address register 83 with
The data relative address held in the in-record data relative address counter 84 is compared. The comparator 87 sends a match signal when the comparison results match.
The flip-flop 88 holds the coincidence signal output from the comparator 87 until the end of the processing of one record.

The AND gate 89 generates the key write timing signal 9. The key write timing signal 9 is output in synchronization with the timing of writing the data from the beginning of the key to the end of the key in the data memory 5.

The comparator 90 includes the contents of the record length register 81 and the in-record data relative address counter 8
Compare with the contents of 4. The comparator 90 detects the end of one record based on the comparison result and outputs a reset signal 91 to the relative address counter 84.

Further, the key position storage unit 8a includes a key start relative address register 82 and a key end relative address register 8
3 and stores the key position. The counting unit 8b counts the data position of the input record by the in-record data relative address counter 84. Comparison unit 8c
Is a comparator 85, 87 for comparing the key position stored in the key position storage unit with the data position counted by the counting unit.
And a flip-flop 8 for holding the comparison result of the comparator
Based on the comparison result held in the flip-flops 86, 88 of the comparison unit, the signal unit 8d has a timing signal for instructing the key memory 7 to write data at the data input timing. Output. The reset unit stores the record length in the record length register 81, and resets the key write control circuit 8 when the data position by the count unit reaches the record length.

Next, the operation will be described with reference to FIG. FIG. 3 is a timing chart of the key write control circuit 8. This timing chart shows a timing chart when the data of the record as shown in FIG. 1 is input.

A record length, a key start relative address, and a key end relative address are written in advance in the record length register 81, the key start relative address register 82, and the key end relative address register 83, respectively. For example, in the case of FIG. 1, the record length is 7 words. When the start address of the record is 0, the end address of the record is 6. The keys existing in the record are from the second word to the third word in length.
The key start address is 1, and the key end address is 3.

Therefore, at the start of the operation, the value of the record length register 81 becomes 7. Further, the value of the key head relative address register 82 becomes 1. Further, the value of the key end relative address register 83 becomes 3.

Data is input from the main storage device 1 to the input unit 2 of the key extracting device. The data write control circuit 3 generates the data write timing signal 4. The input data is sequentially written in the data memory 5 at the timing of the data write timing signal 4. Further, the data write timing signal 4 is input to the key write control circuit 8. The data write timing signal 4 increments the in-record data relative address counter 84 every time data is written to the data memory 5.

By time t1, data one word before the head data of the key (in FIG. 1, REC0 indicates "D0
0 ”is written in the data memory 5. After time t1, the comparator 85 outputs a coincidence signal of the contents of the in-record data relative address counter 84 and the contents of the key head relative address register 82. Therefore, at time t2, the flip-flop 86 is set to ON. During the period from t2 to t3, the next data, which is the first data of the key (“K00” in REC0), is written in the data memory 5. During this period from t2 to t3, the AND gate 89 causes the data write timing signal 4
At the same time, the key write timing signal 9 is output.
By the key writing timing signal 9, the head data of the key is written in the key memory 7.

After that, the end of the key (in REC0, "K0
2)) is detected, the keys are continuously written to the data memory 5 and the key memory 7 simultaneously.

During the period from t6 to t7, the end data of the key is written in the data memory 5. During this period of t6 to t7,
The comparator 87 outputs a coincidence signal between the contents of the in-record data relative address counter 84 and the contents of the key end relative address register 83. Therefore, at time t7, the flip-flop 88 is set to ON. Then, after the next data transfer (“D01” in REC0), the key write timing signal 9 is not output until the data transfer for one record is completed.

When the last data of one record (“D03” in REC0) is transferred by time t10,
At time t10, the contents of the record length register 81 and the contents of the in-record data relative address counter 84 match. Therefore, the reset signal 91 is transmitted through the comparator 90. The reset signal 91 resets the relative address counter 84 and the flip-flops 86 and 88. Thus, the key writing control circuit 8
Is initialized. When writing the data of the next record to the data memory 5, the same operation as described above is performed. As a result, only the key part in the data is always extracted in the key memory 7.

Example 2. In the first embodiment, the key head relative address register 82 that holds the value of the key head address as a relative address from the head of the record, and the key that holds the end address of the key as a relative address from the head of the record Although the end relative address register 83 is included, these registers may be configured as a memory. In the case of the memory structure, a plurality of key parts can be set in one record. An example of this case is shown in FIGS.

In FIG. 4, each record of data on the main memory 1 is composed of 7 words. One key exists in the second and third words in one record. And there is one key in the 6th word. That is, there are a total of two keys in one record.

As shown in FIG. 5, a multi-key head relative address memory 96 and a multi-key end relative address memory 97 are provided to hold the head relative addresses and end relative addresses of a plurality of keys. When processing a record such as REC0 in FIG. 4, the contents of the plural key head relative address memory 96 are AS0 = 1 and AS1 = 5. AS
The other memories of 2 to ASN are unused. Further, the contents of the plural key end relative address memory 97 are AL0 =
2, AL1 = 5. The memories of AL2 to ALN are unused. The comparator 87 outputs a coincidence signal 92 indicating the end of the key. The coincidence signal 92 is input to the key address counter circuit 93. Key address counter circuit 93
Generates a timing for incrementing the addresses of the plural-key head relative address memory 96 and the plural-key end relative address memory 97 based on the coincidence signal 92. The key address counter circuit 93 outputs the address signal 95 to the address memories 96 and 97 at this timing. Further, the key address counter circuit 93 causes the match signal 9
Based on 2, the timing signal 94 that resets the flip-flops 86 and 88 is generated.

Next, the operation will be described. When the value of the in-record data relative address counter 84 is between the range indicated by the value of AS0 of the plural key start relative address memory 96 and the value of AL0 of the plural key end relative address memory 97,
The key write timing signal 9 for the first key in the record is output simultaneously with the data write timing signal 4. Then, K00 and K01 in REC0 of FIG. 4 are written in the key memory 7 at the same time as they are written in the data memory 5.

After K00 and K01 are written in the key memory 7, the key address counter circuit 93 increments the addresses of the plural key start relative address memory 96 and the plural key end relative address memory 97. When the value of the in-record data relative address counter 84 is in the range indicated by the value of AS1 of the plural-key start relative address memory 96 and the value of AL1 of the plural-key end relative address memory 97, the key write timing signal 9 writes data. It is output at the same time as the timing signal 4. Then, K02 in REC0 of FIG. 4 is written in the key memory 7 at the same time as it is written in the data memory 5. When the writing of the first record is completed, the key writing control circuit 8 is initialized. The above operation is repeated in the case of writing the next record.

Example 3. Although the key memory is individually prepared in the above embodiment, for example, a part of the local memory unique to the processor may be used.

Example 4. In the second embodiment, the plural-key head relative address memory 96 and the plural-key end relative address memory 97 are set as a memory in which only the head relative address of each of the plurality of keys and only the end address thereof. However, for example, as shown in FIG. 6, each address memory may be individually set for each address. In this case, the key address counter circuit 93 in the second embodiment becomes unnecessary.

Example 5. In the second embodiment, the case where the data has a plurality of key portions has been described. The order of setting the plurality of keys in one record in the key memory is the order of the key portions stored in the data. But,
For example, there is a case where the order of setting in the key memory of the key portion is not the order stored in the data. An example of such a case is shown in FIG. In FIG. 7, the key write address memory 101 is provided in the key address counter circuit 93. Key write address memory 101
Stores the position of the relative address in the key memory to which the key is written in the processing of one record. The key address counter circuit 93 generates a key write address signal 100 based on this information. The key write address memory 101 is a key write address signal 100.
Is sent to the key memory 7. The key memory 7 writes the key to the corresponding address of the key memory according to the content of the key write address memory 101 by the key write timing signal 9 and the key write address signal 100.

Example 6. In the fifth embodiment, as in the second embodiment, the case where a plurality of key portions existing in the data are set in the key memory in an arbitrary order rather than the order in which they are stored in the data has been described. However, for example, even when the key memories are individually provided as in the fourth embodiment, the key memories can be set in any order. For example, as shown in FIG. 8, the key write address memory 101
It is possible to set a plurality of key portions in the key memory in any order by providing a plurality of key portions corresponding to the number of key portions.

Example 7. In the above embodiment, the data memory 5
On the other hand, the case where the key is written in the key memory at the timing of writing the data is described. However, as shown in FIG. 9, the key may be written in the key memory 7 without the data memory.

In FIG. 9, the data read control circuit 3
The a outputs an input timing signal 4a for reading data to the processor 6. The processor 6 inputs data from the main memory 1 according to the input timing signal 4a. The key write control circuit 8 inputs the input timing signal 4a. The key write control circuit 8 uses this input timing signal 4a as a substitute for the data write timing signal 4 shown in FIG. If the input timing signal 4a operates under the same conditions as the data write timing signal 4 shown in FIG. 3, the key write control circuit 8 can perform the same operation as that of the above-described embodiment.
In this embodiment, since the data memory 5 does not exist, of the data read from the main storage device, the data other than the key portion is read and ignored at the same time and is discarded.

Example 8. In the above embodiment, the case where there is only one key memory 7 has been described, but a case where there are a plurality of key memories as shown in FIG. Figure 1
The key memory indicated by 0 is 3 of the key memories 7a, 7b and 7c.
It is divided into two parts. The key write timing signal 9 is supplied to the key memory 7 at each timing by the switch SW.
a, 7b, 7c are selected in order. Therefore, the key memory 7a
Only the key parts of K00, K10, and K20 are stored as the keys. After that, each key memory 7a, 7
b and 7c can be separately accessed by another program or a processing device.

Example 9. In the above-described embodiment, the case where the key is extracted from each record has been described, but in this embodiment, the case where the key is extracted from each record and the already deleted record is ignored will be described. FIG. 11 is a diagram showing the configuration of the key extracting device in this embodiment. In this example, a case will be described in which a deleted record is detected and the data and key of the record are not written to the data memory and the key memory. In this embodiment, it is assumed that a specific value FF (H) is recorded in the first word at the beginning of the deleted record. Figure 1
In No. 1, the second record (REC1) is a deleted record. The data input section 2 includes an input register 110. The input register 110 sequentially inputs each word from the main storage device 1. The input register 110 operates with a clock in phase with the data write timing signal 4 (or key write timing signal 9). The data input to the input register 110 at a certain clock timing is output from the input register 110 to the data memory 5 and the key memory 7 at the next clock timing. The register 111 holds a specific value FF (H). The comparator 112 receives the data input to the input register and the register 1
The value FF (H) held in 11 is compared. The flip-flop 113 holds the match result when the comparison results of the comparator 112 match. The flip-flop 113 outputs the coincidence signal 114 to the AND gate 115. The AND gate 115 stops the data write timing signal 4 output from the data write control circuit 3 when the coincidence signal 114 is output. While the match signal 114 is being output from the flip-flop 113, the data write timing signal 4 remains at the data memory 5
Therefore, the data output from the input register 110 is not written to the data memory 5. Also, the key write control circuit 8 that operates based on the data write timing signal 4 does not operate. Therefore, the key write timing signal from the key write control circuit 8 is not output to the key memory 7. Therefore, the input register 11
The data output from 0 is not written to the key memory.

When the first record (REC0) in FIG. 11 is input, the comparator 112 outputs a specific value FF.
Since (H) is not detected, all the words of the first record are stored in the data memory 5 by the same operation as that of the above-described embodiment.
Memorized in. Similarly, key 0 (K00, K01, K
02) is stored in the key memory 7. Next, when the first word of the second record (REC1) is input, the comparator 1
12 detects FF (H) and outputs the match result to the flip-flop 113. The flip-flop 113 outputs the coincidence signal 114. The coincidence signal 114 continues to be output until the flip-flop 113 is reset. The reset circuit 116 detects the end of one record and outputs a reset signal 117 at the end of one record. The reset circuit 116 can be configured by the in-record data relative address counter 84, the record length register 81, the comparator 90, and the like in the key write control circuit 8. Reset circuit 116 reset signal 1
When 17 is output, the flip-flop 113 is reset and the output of the coincidence signal 114 is stopped. In this way, the flip-flop 113 continues to output the match signal from the first word of the second record to the last word of the second record. Therefore, all the words of the second record and the key parts (K10, K11, K12) of the second record are not output to the data memory 5 and the key memory 7.

Example 10. In the above embodiment, the case of ignoring the data of the deleted record by suppressing the data write timing signal has been described, but in this embodiment, the key of the deleted record is ignored by suppressing the key write timing signal 9. The case will be described. 12 is different from FIG. 11 described above in that one input of the AND gate 115 is the key write timing signal 9 from the key write control circuit 8. The reset signal 91 from the key write control circuit 8 is used as the reset signal for the flip-flop 113.
Is the point that is used. According to this example, when the first word of the second record (REC1) is input, the flip-flop 113 outputs the coincidence signal 114 and stops the output of the key write timing signal 9. The flip-flop 113 continues to output the coincidence signal 114 until the key write control circuit 8 outputs the reset signal 91 indicating the end of one record. Therefore, the second record (RE
The key of C1) is not stored in the key memory 7.

Example 11. Example 9 and Example 10 above
In the above, the case where the data and / or the key of the deleted record is ignored has been described, but the kind of the ignored record is not limited to the deleted record. That is, the above-described method can be used when performing the record selection process of determining whether or not to select a record having a certain specific value. For example, when there is a word indicating male or female, it is possible to select only the male and retrieve the key part from the record of the male.

Example 12 In the above-described embodiment, the case of extracting the key from each record has been described, but in this embodiment, the case of adding the additional information to the key and writing it in the key memory will be described. FIG. 13 is a diagram showing the configuration of this embodiment. In addition to keys, the flag 0 or the flag 1 is recorded in the key memory 7. This flag 0
Alternatively, the flag 1 stores the identifier of the record.
For example, a serial number numbered in the order of record input is stored as an identifier. In this way, by adding the serial numbers of the records to the keys, it is possible to sort the records in the order in which the records were input when the keys are used for sorting. The counter 121 is a counter that counts up or down each time a record is input. The up / down selection unit 122 selects whether to increase or decrease the counter value of the counter 121. Here, the case where the count is sequentially increased from "1" will be described. The selector 120 selects and outputs either the data input from the main storage device 1 or the counter value output from the counter 121. The selector 120 is
After the transfer of one record is completed, the counter value is selected from the counter 121 and output. Also, the key write control circuit 8 generates an extra key write timing signal 9 for one clock when the transfer of the first record is completed. Delay circuit 12
3 outputs a 1-clock delay signal 125 delayed by 1 clock from the reset signal 91 to the selector 120 based on the reset signal 91 output from the key write control circuit. The selector 120 outputs the 1-clock delay signal 1
The counter value in the counter 121 is output at the timing of 25. Therefore, the key memory 7 can store the counter value as a flag during one clock after the transfer of one record is completed. In addition, the delay circuit 123 delays the reset signal 91 by 2 clocks and outputs the 2-clock delay signal 12
4 is output to the counter 121. The counter 121 increments the counter value based on the 2-clock delay signal 124.

For example, when each word of the first record (REC0) is input to the selector 120, the counter 121 holds the counter value 1. When the first record ends, the delay circuit 123 outputs the 1-clock delay signal 125 to the selector. Selector is counter 1
The counter value “1” is input from 21 and is output to the key memory 7. The key write control circuit generates the key write timing signal 9 one clock after the reset signal 91. Therefore, the counter value “1” is recorded in the flag 0 of the key memory 7. The delay circuit 123 outputs the 2-clock delay signal 124 to the counter 121, and the counter increments the counter value to "2". At the same time when the counter value is changed, the input of the second record (REC1) is started. The counter 121 holds the counter value “2” while each word of the second record is being input. When the input of the second record is completed, the selector 120 selects and outputs the counter value “2” from the counter 121 based on the 1-clock delay signal 125 of the delay circuit. As a result, the counter value “2” is stored in the flag 1. By outputting the flag 0, the flag 1, etc. in association with the key in this manner, it becomes possible to perform special processing of data by using the value of this flag in the later sort processing.

Example 13. In Example 12 above,
1 for multiple keys retrieved from one record
The case where one flag is added has been described, but in this embodiment, when one record has a plurality of keys, the case where a flag is added to each key will be described. FIG. 14 is a diagram showing the configuration of this embodiment. The register 130 has a data portion that holds the data from the main storage device 1 and a count portion that holds the counter value from the counter 121. Register 130
The count part of does not normally output the counter value,
The counter value is output when the key write timing signal 9 is output. Therefore, when the key write timing signal 9 is not generated, the data is output from the data portion of the register 130. When the key write timing signal 9 is generated, both the data of the register 130 and the counter value are output and output to the key memory 7. The key memory 7 is composed of three parts 7a, 7b and 7c, each of which has a key part for holding a key and a flag part for holding a flag.
Therefore, a flag is held corresponding to each key. By configuring the key memory in this way, even when the key memories 7a, 7b, and 7c are independently processed, it is possible to finally determine which record the key is from the value of the flag, The flag can be used to reintegrate the key.

Example 14 In the above embodiment, the case where the processor 6 inputs data from the main storage device 1 has been described. However, as shown in FIG. 15, a DMA (direct memory access) 6a is provided and the DMA 6a is used.
Data may be input from the main storage device 1. The processor 6 can perform other processing by giving the data necessary for starting the DMA 6a to the DMA 6a, and the efficiency of data processing is further improved.

Example 15 In the above embodiment, the key extracting device for performing the sorting process is described, but it is also possible to extract a specific part or item from arbitrary data, such as extracting the employee number and the name from the personnel record. The present invention is effective.

The present invention is also effective when extracting specific data from a database and creating a new database. For example, by using a database processing language called SQL, a fictitious table (this is called a view) may be generated from a table that already exists and this view may be searched. Since this view is a fictitious table, it is not actually recorded, and it is generated every time a request is made by searching the actually recorded table. Alternatively, it is temporarily stored in a main storage device, a cache memory, or the like. Thus, when using a fictitious table like a view, a fictitious table must be generated from a table that actually exists, either temporarily or frequently. By using the method of retrieving the key part according to the above-described embodiment, a fictitious table called this view can be retrieved at high speed. Thus, in the present invention, the key does not mean only the sort key,
It means a specific part of arbitrary data or a specific item.

Example 16 In the above-described embodiment, the case where one record is composed of word units is shown. But 1
The unit forming the record may be another unit. For example, it may be configured in byte units or bit units. If one record is composed of byte units or bit units, the key head relative address register 8
2. The key end relative address register 83 and the in-record data relative address counter 84 hold or count addresses in byte units or bit units.

[0049]

As described above, according to the present invention, data input means for inputting data, key storage means for storing a key portion existing in data, and data input by the data input means are performed in parallel. By providing the key writing means for taking out the key portion from the data and writing it in the key storage means, the key portion can be taken out from the data at high speed. Further, since the processor is not used for extracting the key part, the processor load is reduced and the processing efficiency of the processor is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a key extracting device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal circuit of a key write control circuit 8 according to the first embodiment of the present invention.

FIG. 3 is a chart of an operation of the key write control circuit 8 according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram showing a key extracting device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an internal circuit of a key write control circuit 8 in Embodiment 2 of the present invention.

FIG. 6 is a diagram showing an internal circuit of a key write control circuit 8 when an address memory is set to be different for each address according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing an internal circuit of a key write control circuit 8 in a case where a key portion of a key portion is set in an arbitrary order in a fifth embodiment of the present invention.

FIG. 8 is a diagram showing an internal circuit of a key write control circuit 8 in the case where a plurality of key write address memories 101 are provided in correspondence with the number of key portions in the sixth embodiment of the present invention.

FIG. 9 is a configuration diagram showing a key extracting device according to a seventh embodiment of the present invention.

FIG. 10 is a configuration diagram showing a key extracting device according to an eighth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a key extracting device according to a ninth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a key extracting device according to a tenth embodiment of the present invention.

FIG. 13 is a configuration diagram showing a key extracting device according to a twelfth embodiment of the present invention.

FIG. 14 is a configuration diagram showing a key extracting device according to a thirteenth embodiment of the present invention.

FIG. 15 is a configuration diagram showing a key extracting device according to a fourteenth embodiment of the present invention.

FIG. 16 is a configuration diagram showing a conventional key extraction device.

[Explanation of symbols]

 1 main memory 2 data input part of key extraction device 3 data writing control circuit 4 data writing timing signal 5 data memory 6 processor 7 key memory 8 key writing control circuit 9 key writing timing signal 81 record length register 82 key start relative address register 83 key end relative address register 84 in-record data relative address counter 85 comparator 86 flip flop 87 comparator 88 flip flop 89 AND gate 90 comparator 91 reset signal 92 key end match signal 93 key address counter circuit 94 flip flop reset signal 95 key address Output signal 96 Multiple key start relative address register 97 Multiple key end relative address register 100 Key write Address signal 101 Key write address memory 110 Input register 111 Register 112 Comparator 113 Flip-flop 114 Match signal 115 AND gate 116 Reset circuit 117 Reset signal 120 Selector 121 Counter 122 Up / Down selector 123 Delay circuit 124 2 clock Delay signal 125 1 clock Delayed signal 130 register

Claims (20)

[Claims] 1. A key extracting device for inputting data and extracting a key portion existing in the data, the key extracting device having the following elements: (a) data input means for inputting data; and (b) storing a key portion. Key storage means, (c) Key writing means for taking out a key portion from the data and writing it in the key storage means in parallel with the data input by the data input means. 2. The key extracting device according to claim 1, further comprising: (a) data storing means for storing data; and (b) the data inputting means. Data writing means for writing data to the data storage means in parallel with data input. 3. The data input means, as data,
Inputting a plurality of fixed-length records having a key portion at a predetermined key position, and the key writing means extracts the key portion from each record input by the data input means and stores it in the key storage means. The key extracting device according to claim 1 or 2, characterized in that 4. The key writing means comprises: (a) a key position storage means for storing the key position; (b) a counting means for counting the data position of a record input by the data input means; and (c) ) Comparing means for comparing the key position stored in the key position storing means with the data position counted by the counting means, and (d) data for the key storing means based on the comparison result by the comparing means. 4. A key extracting device according to claim 3, further comprising a signal means for outputting a timing signal for instructing writing of the key. 5. The key writing means further comprises a reset means for storing the record length and resetting the key writing means when the data position by the counting means reaches the record length. 4. The key extraction device described in 4. 6. The key position storage means stores a relative address from the head of the record to the key position as a key position, and the counting means stores the relative address from the head of the record to the currently input data as the data position. 6. The key extracting device according to claim 4, wherein the key extracting device counts as. 7. The key extracting device according to claim 4, 5 or 6, wherein said key position storing means stores a leading position and an ending position of a key portion as key positions. 8. The record input by the data input means has a plurality of key portions, and the key position storage means stores a plurality of key positions.
Alternatively, the key extraction device described in item 5. 9. The key writing means further comprises a key writing position memory means for storing a key writing position for writing the key portion of the key storing means corresponding to each of the plurality of key portions stored in the key position storing means. Have
When outputting the timing signal, the signal means selects a key writing position corresponding to a key portion to be stored in the key storing means from the plurality of key writing positions stored in the key writing position memory means. 9. The key extracting device according to claim 8, which outputs the data to a key storage means. 10. The comparison means has a comparator for comparing the key position stored by the key position storage means with the data position counted by the counting means, and holding means for holding the comparison result of the comparator. 7. The signal means outputs the comparison result held in the holding means to the key storage means as a timing signal at the timing of data input by the data input means. Key removal device according to item 8 or 9. 11. The key extracting device further comprises a comparing device for comparing the data input by the data input device with predetermined data, and the key storing device by the key writing device based on the comparison result of the comparing device. 4. The key extracting device according to claim 3, further comprising a key writing stopping means for stopping writing of the key portion to the key writing device. 12. The key extracting device further comprises an identifier storing means for storing the identifier of the record from which the key portion is extracted together with the key portion when the key writing means writes the key portion in the key storing means. The key extracting device according to claim 3, wherein 13. A sort processing device, comprising the key extracting device according to claim 1, 2 or 3, and further comprising a sorting means for sorting the key portions stored in the key storage means. 14. The key extracting device according to claim 1, 2 or 3, further comprising access means for accessing the key portion stored in the key storage means as a new file. Database processing unit. 15. A key extraction method having the following steps: (a) a data input step of sequentially inputting data, and (b) whether or not the data sequentially input by the data input step is a key portion by the data input step. A determination step of determining when inputting data, (c) an extraction step of extracting data determined to be the key portion based on the determination result of the determination step when inputting data to be input in the data input step. 16. The key extracting method further includes a key position storing step of storing a key position where a key portion in the data exists in advance, and the determining step includes the key stored in the key position storing step. 14. The key extracting method according to claim 13, wherein the key portion is determined from the data input in order using the position. 17. The key extracting method according to claim 13, further comprising a repeating step of repeating the data input step, the determining step, and the extracting step to extract a plurality of key portions. Method. 18. The key extracting method further comprises a key storage position outputting step of outputting a key storage position for storing the extracted key portion when the extracting step extracts the key portion by the repeating step. 16. The key extracting method according to claim 15, wherein: 19. The key extracting method further divides the data sequentially input by the data input step into records of a predetermined length, and resets the data input step, the determination step, and the extraction step at each record division. 16. The method according to claim 13, 14 or 15, further comprising a reset step.
The key removal method described. 20. The key extracting method further comprises a data storing step of storing the data input in the data input step.
The key removal method described in 5 or 16.