JPH06161616A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To evade the shut off of a system even if a power source device is stopped. CONSTITUTION:In a processor module 10a, power source is supplied from a power source device A 20a and in a processor module 10b, power source is supplied from a power source device B 20b. Each of processor modules 10a, 10b is provided with power source information storage parts 11a, 11b where the operation information of the power source devices 20a, 20b is stored, fault notification reception means 12a, 12b for receiving notifications of the power source devices 20a, 20b and control means 13a, 13b performing the operation control of the processor modules 10a, 10b. When either of the power source devices 20a, 20b is failed, the control means 13a, 13b refer to the information of the power source information storage devices 11a, 11b, stops the operation when the failed power devices 20a, 20b are on the side of a processor in use and continues the operation when they are on the side of the other processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system capable of degenerate operation, and more particularly to a power supply system thereof.

[0002]

2. Description of the Related Art Generally, in an information processing apparatus which is required to have high reliability, a plurality of processors and a plurality of external storage devices are provided so that if one processor or the external storage device fails, another processor or the like operates. A multiprocessor system is used which is capable of performing. In such a multiprocessor system, a plurality of processor boards, memory boards, and input / output control boards are mounted on a motherboard, and power is supplied to these boards from the same power supply device, and the processor is Multiprocessor system,
The memory is the total capacity of all the memories, and the input / output device is operated in a mirroring configuration.

FIG. 2 shows the configuration of such a multiprocessor system. The system shown in the figure has a configuration of two processor modules, two memory modules, and two input / output control device modules. That is, the two processor modules are a processor board [A] 1a and a processor board [B] 1b on which a CPU (central processing unit) and its peripheral devices are mounted, and two memory modules include a RAM and its controller. The mounted memory board [A] 2a and the mounted memory board [B] 2b. The input / output control device module is a controller such as a magnetic disk connected to the input / output control device module, and is an input / output control board [A] 3a and an input / output control board [B] 3b. These boards are connected to the system bus 4 and are supplied with power from the power supply device 5 through the power supply line 6. Also, processor board [A]
A power failure notification line 7 for notifying a failure of the power supply device 5 is connected to [B] 1a and 1b.

Such a multiprocessor system is
The two processors each perform various processes at the same time, and their capabilities are doubled. Also, the two memories are used as the total capacity of each memory,
Further, the external storage device such as a magnetic disk connected to the two input / output control boards [A] [B] 3a, 3b has a mirroring structure. That is, two processors are used to distribute the load and two memories are set to increase their capacity. In addition, the mirroring configuration of the input / output device is a configuration in which two external storage devices and the like are set so as to hold exactly the same data.

In such a multiprocessor system, in a normal operation, the processors perform respective processes with each other, and when certain data is written to the external storage device as a result of the process, this data is stored in the system bus 4. Via the input / output control board [A] [B] 3a,
The same data is stored in the external storage devices that are respectively transferred to 3b.

On the other hand, in such a multiprocessor system, for example, when the processor board fails, the remaining processors continue the degenerate operation, and when the memory board fails, the remaining memory degenerates the capacity. And continue driving. When the input / output control board fails, the mirroring is generally stopped and the operation is continued.

[0007]

However, the conventional multiprocessor system described above is provided with two modules each to ensure the reliability against the failure of any one of the modules. Since the power supply device 5 to be supplied is common, there is a problem that the system is stopped when the power supply device 5 fails.

In order to deal with such a problem, there is a configuration in which a power supply device equivalent to the power supply device 5 is provided as a spare and the power supply device 5 is switched to the spare power supply device when a failure occurs. However, in the case of such a configuration, the spare power supply device also requires a capacity equivalent to that of the power supply device 5, and this causes a problem of cost increase.

The present invention has been made in order to solve the above-mentioned conventional problems, and it is possible to prevent the system from being stopped even if the power supply device fails, and to suppress the cost increase. The purpose is to provide.

[0010]

A multiprocessor system of the present invention is a multiprocessor system including a plurality of processor modules, and a plurality of power supply devices each arbitrarily connected to the plurality of processor modules, A power supply information storage unit that is provided in each of the plurality of processor modules and stores, for each of the plurality of power supply devices, operation information indicating whether or not each power supply device is operating normally, and all of the plurality of power supply devices. Failure receiving means for receiving a failure notification from the power supply device, and the power supply device that has sent the failure notification by referring to the power supply information storage unit when the failure notification means receives the failure notification from any of the power supply devices. If the power supply unit is supplying power to its own processor module, It is characterized in that a control means for stopping the operation of Le.

[0011]

In the multiprocessor system of the present invention, when one of the power supply units fails, the power supply unit sends a power supply failure notification to each processor module. When the power failure notification is received by the failure notification receiving means, the control means reads the information in the power information storage unit and recognizes which power supply device has failed. If the failed power supply is a power supply that is supplying power to its own processor module, the operation of its own processor module is stopped and the failed power supply supplies power to another processor module. If
Continue driving as it is. Therefore, even if one of the power supply units fails and the processor module that is being supplied with power from that power supply unit stops, the other processor modules can easily recognize this and shift to degenerate operation. It can be done smoothly.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the relationship between a processor module and a power supply device in the multiprocessor system of the present invention. The system shown in the figure shows a system in which power is supplied from two power supply devices [A] 20a and [B] 20b to two processor modules [A] 10a and [B] 10b, respectively. That is, the processor module [A] 10a is supplied with power from the power supply [A] 20a through the power supply line [A] 30a, and the processor module [B] 10b is supplied with the power supply [B] 2.
0b supplies power through the power supply line [B] 30b. In addition, the processor module [A] 10a,
[B] 10b includes power supply devices [A] 20a and [B], respectively.
20b to power failure notification lines [A] 40a, [B] 40b
A power failure notification is sent via the.

Two processor modules [A] 10
a and [B] 10b respectively include power supply information storage units 11a and 1b.
1b, failure notification receiving means 12a and 12b, and control means 13a and 13b are provided. Power supply information storage unit 1
1a and 11b are power supply devices [A] 20a and [B] 20b
Has a function of storing operation information indicating whether or not each is normally operated. Further, the failure notification receiving means 12
Each of a and 12b has a function of receiving a failure notification from any of the power supply devices [A] 20a and [B] 20b.

The control means 13a, 13b are connected to one of the power supply units [A] 20 by the failure receiving means 12a, 12b.
a, [B] When the failure notification is received from the 20b, the power supply device that has sent the failure notification refers to the power supply information storage units 11a and 11b, and the processor unit module [A] 10a
(Or [B] 10b) is the power supply device [A] 20a (or [B] 20b) that is being supplied with power, the operation of its own processor module [A] 10a (or [B] 10b) is performed. The power supply device [A] 20a (or [B] 20b) that has stopped and sent the failure notification is the other processor module [B] 10b (or [A] 10a)
If the power is supplied to the processor module itself [A] 10a (or [B] 10
It has a function of continuing the operation of b).

FIG. 3 shows a specific configuration of the multiprocessor system of the above embodiment. 3, the processor modules [A] 10a and [B] 10b shown in FIG.
Is a processor board [A] 10a and [B] 10b, and a memory module including a RAM and its memory control unit is a memory board [A] 50a, [B].
It is composed of 50b. Further, the input / output control device module including a disk controller and the like is the input / output control boards [A] 60a and [B] 60b.

The processor board [A] 10a, the memory board [A] 50a, the input / output control board [A] 60a.
Are connected to even slots of the system bus 70, and are configured to be supplied with power from the power supply device [A] 20a through the power supply line 30a. On the other hand, the processor board [B] 10b, the memory board [B] 50b, and the input / output control board [B] 60b are connected to odd-numbered slots of the system bus 70, and the power supply [B] 20b to the power supply line 30b.
It is configured to be supplied with power via. In addition, these functions have two processor boards [A] as before.
10a [B] 10b performs processing with double the capacity,
The capacities of the memories of the two memory substrates [A] 50a and [B] 50b are doubled. On the other hand, the input / output control boards [A] 60a and [B] 60b have a mirroring structure.

FIG. 4 shows a specific structure of the processor board [A] 10a. This processor board [A] 10a is
CPU (central processing unit) 101a, hardware configuration information 102a, NMI (non-maskable interrupt) status register 103a, OR circuit 104a, data bus 10
5a. In addition, NMI status register 1
03a corresponds to the power supply information storage unit 11a in FIG.
101a and the OR circuit 104a are the failure notification receiving means 12a.
In addition, the CPU 101a corresponds to the control means 13a.

In such a processor board [A] 10a, the power failure notification lines 40a and 40b are connected to the OR circuit 1.
It is connected to the NMI terminal 1011a which is an external interrupt terminal of the CPU 101a via 04a. The power supply failure notification lines 40a and 40b are input to the NMI status register 103a to store the failure status. Hardware configuration information 10
Reference numeral 2a is a non-volatile memory such as a ROM or a battery backup memory, and stores information about the hardware configuration such as the slot number of each board. The CPU 101a and the hardware configuration information 102a and the NMI status register 103a are connected by a data bus 105a, and the CPU 101a can read the contents of the hardware configuration information 102a and the NMI status register 103a via the data bus 105a. ing. The configuration of the processor board [B] 10b is also the same as that of the processor board [A] 10a, and thus the description thereof is omitted here.

Next, the operation of the multiprocessor system having the above configuration will be described. First, in a normal normal operation, the processor boards [A] 10a and [B] 10b have a two-processor configuration, and the memory boards [A] 50a and [B] 50b are the same as those of the present embodiment. If the capacity of one sheet is 32 Mbytes, the total of two sheets is 64
It is operated as an M byte. The input / output control boards [A] 60a and [B] 60b have a redundant configuration.
The system is working with mirroring.

Next, the operation when the power supply unit fails will be described by taking the case where the power supply unit [A] 20a fails as an example. In such a case, when the power supply device [A] 20a fails, the failure notification signal is first notified to the processor boards [A] 10a and [B] 10b via the power supply failure notification line 40a.

As a result, each processor board [A] 10
a, [B] 10b CPU 101a, 101b NMI
A power failure notification is input to the terminals 1011a and 1011b, and interrupt processing occurs. CPU 101a, 101
b generates NMI status register 1 when an interrupt occurs
03a, 103b and hardware configuration information 102
Read a and 102b, and recognize that this stops the power supply to the substrates connected to the even-numbered slots. The processor board [A] 10a connected to the even-numbered slot has a time (typically several tens of ms to several hundreds of meters) from the reception of the power failure notification to the actual stop of power supply.
In s), a power stop process is performed, such as writing the data in the RAM on the memory board [A] 50a to the magnetic disk connected to the input / output control board [A] 60a.

On the other hand, the processor board [B] 10b connected to the odd-numbered slot remains the power supply unit [B] 2
Since the power supply is continued from 0b, the hardware connected to the odd-numbered slot is recognized based on the information of the hardware configuration information 102b, and the memory board [B] 50b
The degenerate operation is performed using the input / output control board 60b.
That is, in this case, the processor board [B] 10b is a single processor, the memory board [B] 50b alone is 32 MB capacity reduction, and the input / output control board [B] 60.
The degenerate operation is performed in the state without mirroring by b.

In such a case, the processor board [B] 10b connected to the odd slot has the hardware configuration information 102b and the NMI status register 103.
Since it is possible to recognize which board has stopped by simply referring to b, it is not necessary to separately manage which board is in a stopped state as a multiprocessor system.
It is possible to smoothly shift to the degenerate operation.

In the above embodiment, the configuration including two processors and two power supply units has been described, but the present invention is not limited to this. For example, for three or more processors, three or more power supplies. Configuration that power is supplied from the device,
Alternatively, if the configuration is such that at least two power supply devices each supply power to different processors, such as a configuration in which power is supplied from two power supply devices to three or more processors, the above-described embodiment It can be similarly implemented.

[0025]

As described above, according to the multiprocessor system of the present invention, operation information indicating whether or not a plurality of power supply units are operating normally is provided, and any one of the power supply units sends a failure notification. If the power supply unit that failed is the power supply unit for the local processor module, the operation of the local processor module is stopped. It is possible to provide a highly reliable multiprocessor system that does not stop, and the power supply unit can share its capacity with multiple units, so compared to the conventional one with a spare power supply unit. Cost reduction can be achieved.

Further, when the failed power supply device is not the power supply device for its own processor module, this processor module can easily recognize which processor module has stopped, so that the transition to the degenerate operation is performed smoothly. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram of main parts of a multiprocessor system of the present invention.

FIG. 2 is a block diagram of a conventional multiprocessor system.

FIG. 3 is a block diagram of a multiprocessor system of the present invention.

FIG. 4 is a specific configuration diagram of a processor board in the multiprocessor system of the present invention.

[Explanation of symbols]

 10a, 10b Processor module 11a, 11b Power information storage 12a, 12b Failure notification receiving means 13a, 13b Control means 20a, 20b Power supply device 30a, 30b Power supply line 40a, 40b Power failure notification line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G06F 15/16 470 H 9190-5L

Claims (1)

[Claims] 1. A multiprocessor system including a plurality of processor modules, wherein a plurality of power supply devices each of which is arbitrarily connected to the plurality of processor modules; and a plurality of power supply devices provided in the plurality of processor modules, respectively. A power supply information storage unit that stores operation information on whether each power supply device is operating normally, and a failure reception for receiving a failure notification from all the power supply devices of the plurality of power supply devices. And a failure notification means for receiving a failure notification from any of the power supply devices, the power supply device that has sent the failure notification refers to the power supply information storage unit, and supplies power to its own processor module. If it is a power supply unit that is installed, it is equipped with a control means for stopping the operation of its own processor module. Multi-processor system that.