JPH06161408A - Display controller - Google Patents

Abstract

PURPOSE:To decrease the physical size of the display controller by providing an address converting means which is arranged in front of a storage part and an adjusting means which converts display information into a serial output. CONSTITUTION:This display controller is equipped with the address converting means 13 which is provided behind a VRAM controller 12 and before the storage part M, a data buffer 14, and the adjusting means C which converts the display information SOUT outputted from the storage part M in plane order into the serial output of RGBi and sends the serial output to a CRT 10. This address converting circuit 13 consists of a multiplexer, selector, or circuit pattern and is provided and then the display information is only sent apparently as well as a conventional system when viewed from the side of a CPU 6, thereby applying this controller to hardware and software which are designed for a conventional controller, as it is without any special alteration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device.

[0002]

2. Description of the Related Art For color display devices such as CRTs,
In color display, a plane system in which a plurality of planes such as R (red), G (green), B (blue), and i (luminance) are overlapped is often used.

FIG. 7 is a block diagram showing a display control device according to the prior art. In order to realize this plane method,
As shown in FIG. 1, a separate storage unit (V
A display control device to which a RAM (dual port memory for image) is allocated is used.

In FIG. 7, reference numeral 1 is a system bus to which the CPU 2 and the like are connected, and 3 is a VRAM controller connected to the system bus 1. The VRAM controller 3 accesses the storage units MR, MG, MB, Mi in response to a read / write request from the system bus 1 and also performs vertical synchronization signal VSYNC and horizontal synchronization signal HS.
YNC is generated, and this storage unit MR, MG, MB, M
The SAM controller 5 that controls the output of the display data in i is controlled. Further, 4 is a data buffer.

MR is a storage unit (VRAM group) assigned to the R (red) plane, and this storage unit M
Only the display information of the R plane is temporarily stored in the R and sent to the display device. Similarly, MG is a storage unit dedicated to the G (green) plane, and MB and Mi are storage units dedicated to the B (blue) and i (luminance) planes, respectively.

[0006]

In recent years, the capacity of the above VRAM alone has increased, and the bus width has also expanded. However, as described above, if an independent storage unit (VRAM group) is assigned to each plane, the number of VRAMs required for the entire display control device increases, and the physical size of this display control device increases. Further, even if the capacity of the VRAM alone increases, there is a problem that the large capacity cannot be fully utilized. In the above example, the case where color display is performed using four planes has been described, but the above problem becomes more serious when color display is performed using a larger number of planes such as eight planes.

Therefore, the present invention uses a small number of VRAMs.
It is an object of the present invention to provide a compact display control device that can realize plane type color display.

[0008]

In order to achieve the above-mentioned object, the present invention is provided in the preceding stage of a storage unit, and has display information, plane selection information in lower bits, and upper plane selection information of this plane selection information. It is provided with an address conversion means for converting so that the bits have coordinate address information, and an adjusting means for converting the display information output from the storage unit in plane order into serial output.

[0009]

With the above structure, the display information sent from the system bus to the display control device is converted by the converting means so as to have plane selection information in lower bits and coordinate address information in higher bits than the plane selection information. Sent to storage. Therefore, the VRA that constitutes the storage unit
When the inside of M alone is viewed along the address, the display information is stored so as to be continuous in each plane order. Where this V
Since the RAM outputs information in the order of addresses due to its characteristics, the display information is output from the storage unit in the order of planes. Then, the display information in this plane order is adjusted by the adjusting means.
It is converted to serial output and then sent to the display device.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing device adopting a display control device according to an embodiment of the present invention, FIG. 2 is a block diagram of the display control device, and FIGS. FIG. 5 is an explanatory view of the conversion procedure, FIG. 5 is a correspondence diagram of each plane and its storage state, and FIG. 6 is the same time chart.

In FIG. 1, 6 is a CPU, 7 is a ROM that stores an operating system, 8 is a RAM that stores an application program that operates on the operating system, 9 is a keyboard,
10 is a color CRT as a display device, CU is this CR
A display controller 11 of the present embodiment for controlling T10 is a system bus.

In FIG. 2, reference numeral 12 is a VRAM controller connected to the system bus 11. This VRAM
The controller 12 reads / reads from the system bus 11.
In response to the write request, the storage unit M (VRAMVO, V1, V
(2, V3), and controls the SAM controller 15 for displaying on the CRT 10. The VRAM controller 12 also generates a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC, and C
Send to RT10.

The SAM controller 15 is a VRAMV.
The VRAM controller 12 controls the output of the display information transferred to the SAM units in 0, V1, V2, and V3.
The clock of the SAM section and the timing of output enable are controlled by the display timing generated by.
SC0, SC1, SC2 and SC3 are the above VRAMV
These are serial clock signals of O, V1, V2, and V3 (signals for raising the display address), and SOE
0, SOE1, SOE2, and SOE3 are serial output enable signals. Further, 13 is an address conversion unit provided in the subsequent stage of the VRAM controller 12 and in the previous stage of the storage unit M, 14 is a data buffer, and C is the display information SOUT output from the storage unit M in plane order, and is converted into RGBi serial output, It is an adjusting means for sending this serial output to the CRT 10, and 16 of them is a latch and 17 is a shift register.

Next, the address conversion means 13 will be described. The address conversion means 13 can be composed of a multiplexer, a selector, or a circuit pattern. As shown in FIG. 3, the operation is as shown by the arrow indicating the display information (the plane selection information is in the upper bits and the coordinate address information is in the lower bits) input from the CPU 6 side via the system bus 11. In addition, the display information is converted into display information to be output to the VRAM (the plane selection information is included in the lower bits and the coordinate address information is included in the upper bits).

Here, in the conventional display control device and software based on this display control device, the VRAM is displayed as the display information (upper part in FIG. 3) input from the CPU 6 side.
The controller 3 (FIG. 7) uses the upper-bit plane selection information to select the VRAM group MR for each plane of RGBi,
The display information is written to the lower-order bit coordinate address by allocating to the corresponding one of MG, MB, and Mi. On the other hand, in the display control device of this embodiment, as will be described later, the display information is actually written in plane order in the VRAM alone. However, since the address conversion means 13 is provided, it is sufficient from the side of the CPU 6 to send the display information according to the conventional method in appearance, and the hardware based on the conventional display control device is assumed. , It can be applied to software as it is without any special change.

The address conversion means 13 may be as follows. That is, as shown in FIG. 4A, in the address on the CPU 6 side, the upper bits n, n
-1 is connected to the terminals A1 and A0 on the VRAM side, respectively. Then, in the address on the CPU 6 side, the lower bits n-2, 1, ..., 1, 0 may be connected to the terminals An, An-1, ..., A2 on the VRAM side.

Further, in this embodiment, since four planes of R, G, B, and i are used, the plane selection information is sufficient for 2 bits. For example, the plane selection information is set as shown in FIG. 4 (b). To do. In order to perform multi-gradation display, a means for switching the number of bits of plane selection information at high speed, such as a shifter or a selector, may be used.

Next, referring to FIG. 5, the plane and VRA
Correspondence with MVO, V1, V2, and V3 will be schematically described. In FIG. 5A, P1, P2, P3, P4
Are planes of R, G, B and i, E1, E2, respectively.
... are pixels on each plane.

As described above, the display information is converted by the address conversion means 13 so as to have plane selection information in the lower bits, and then VRAMVO, V1, VRAM.
2, output to V3. Here, as described above, VR
Due to its characteristic, the AM can perform input / output only in the address order. Therefore, when writing to VRAM with plane selection information in the lower bits,
As shown in (b), the display information is written in the order of planes such as R → G → B → i → R.

Then, VRAMVO, V1, V2, V3
Corresponds to 1-bit display information per pixel, and 4 bits per plane of display information are written in each VRAM, the correspondence between the pixels E1, E2, ... 5 (b) is shown at the bottom.

Next, referring to FIGS. 1 and 6, the SAM
The display information is controlled by the controller 15 to display VRAM.
Output from VO, V1, V2, V3 to the adjusting means C,
The operation of the adjusting means C for converting this display information into a serial output to the CRT 10 will be described.

First, at times t1 to t2, the SAM controller 15 enables the serial output enable signal SOE0 of the VRAMVO, raises the serial clock signal SC0 of the VRAMVO, and sequentially raises the display address in the VRAMVO. As a result, FIG.
As shown in (b), in the plate P1, the pixel E1
Display information R of 4 to E4 (for 4 bits) is read, and similarly, each plane P2, P3, P4 of display information G, B, i is also read for 4 bits. Then, at time t6, all of the display information R, G, B, i for the above-mentioned pixels E1 to E4 are gathered, and the SAM controller 15 operates the latch 16 in the adjusting means C, and these display information are displayed. Latched. The output of the latch 16 is output to RGBi by the shift register 17.
Of the sync signals VSYNC, H
It is sent to the CRT 10 in synchronization with the SYNC.

Further, at time t2 to t3, the VRAM
V1, VRAMV2 at time t3 to t4, time t4
The processes similar to the above are performed for VRAMV3 from t5 to t5. By repeating these processes, continuous serial output can be sent to the CRT 10.
As described above, the display control unit CU of the present embodiment includes the CRT 10
Even when viewed from the side, the operation similar to that of the conventional display control device is apparently performed, and therefore, the conventional device can be used for the CRT 10 side.

[0025]

As described above, according to the present invention, the display information is provided before the storage unit, and the display information has the plane selection information in the lower bits, and the coordinate address information in the upper bits of the plane selection information. And an adjusting means for converting the display information output from the storage unit in the order of planes into a serial output. Therefore, it is not necessary to provide an independent storage unit for each plane, and the physical size of the display control device can be reduced accordingly. In addition, large capacity VRA
With respect to M as well, the size merit can be fully utilized by storing the display information continuously in the order of each plane. Moreover, from the viewpoint of the CPU side, since it is possible to send the same information as the conventional display information, compatibility with existing hardware and software can be accepted.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing device that employs a display control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a display control device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of display information and an exchange procedure in the display control device according to the embodiment of the present invention.

FIG. 4A is an explanatory diagram of display information and an exchange procedure in the display control device according to the embodiment of the present invention. FIG. 4B is an explanatory diagram of display information and an exchange procedure in the display control device according to the embodiment of the present invention.

FIG. 5 (a) Correspondence diagram of a plane of a display control device according to an embodiment of the present invention and its storage state. (B) Correspondence diagram of a plane of a display control device according to an embodiment of the present invention and its storage state.

FIG. 6 is a time chart of a display control device according to an embodiment of the present invention.

FIG. 7 is a block diagram of a display control device according to a conventional technique.

[Explanation of symbols]

 10 Color CRT 11 System Bus 13 Address Converting Means C Adjusting Means P1, P2, P3, P4 Planes V0, V1, V2, V3 VRAM M Storage Unit

Claims (1)

[Claims] 1. A display control device which is connected to a system bus and temporarily stores display information for each plane of a display device in a storage unit composed of a VRAM and then sends the display information to the display device. And an address conversion unit which is provided in the preceding stage and converts the display information so that the lower bit has plane selection information and the upper bit of the plane selection information has coordinate address information. A display control device comprising: an adjusting unit that converts display information that is sequentially output to serial output.