JPH06153245A - Transmission memory control circuit - Google Patents

Abstract

PURPOSE:To obtain the transmission memory control circuit by which no duplication takes place in transmission data with respect to the transmission memory control circuit. CONSTITUTION:The circuit is provided with a memory 11 storing transmission data, a register memory 12 receiving a channel number and storing control data of a relevant channel, and an arithmetic operation section 13 applying various arithmetic operation processing to the transmission data read from the memory 11 based on the control data given from the register memory 12 and also a transmission memory 14 receiving an output from the arithmetic operation section 13 and in which data are written synchronously with the channel clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission memory control circuit, and more particularly to a circuit configuration in an HDLC handler provided in a DLC common part in a digital switching network.

[0002]

2. Description of the Related Art FIG. 10 is a conceptual diagram of a conventional exchange system. In the figure, 1 is a digital subscriber terminal (T
E), 2 is a digital subscriber circuit (DLC) provided corresponding to these digital subscriber terminals 1, and 5 is a DLC common section (DLC) connected to the digital subscriber circuit 2.
C). Reference numeral 5a is an HDLC handler provided in a one-to-one correspondence with the digital subscriber circuit 2. 6 is DL
Microprocessor for controlling C common unit 5, 7 is DLC
An exchange (NW), 8 connected to the common unit 5 is the exchange 7
Call processor (CP
R).

In the exchange system thus constructed, the digital line is H by the HDLC handler 5a.
Control information is exchanged in the DLC format.
The HDLC handler 5a includes a data transmission circuit and a data reception circuit.

FIG. 11 is a block diagram showing a configuration example of a conventional circuit and shows a configuration of a data transmission circuit. In the figure, 11 is a memory for storing transmission data, and 12 is a register memory (register file) which receives a channel number (CH NO) as an address and outputs control data stored at a corresponding address. 13 is memory 1
This is a calculation unit that adds various calculations (CRC calculation, 0 insertion, etc.) to the data read from 1, based on the input control data. The outline of the operation of the circuit configured as described above is as follows.

First, when CH NO is given, the control data stored in the corresponding address is output from the register memory 12 by using the CH NO as an address, and the control data enters the arithmetic unit 13. The calculation unit 13 performs processing such as CRC calculation, 0 insertion, and flag addition on the data read from the memory 11.

Now, the 0 insertion will be described. On the transmitting side, when five "1" s appear consecutively in the frame contents other than the flag, "0 insertion" (0 insertion) is always performed to insert one "0" next. This is a process performed on the receiving side to extract a clock from the received data.

FIG. 12 is a diagram showing the operation timing of the conventional circuit. Processing of each CH is performed in synchronization with the channel clock (CH clock). In the figure, CH n and CH
Two types of CH of m are shown. The operation of each CH is composed of T1 state, T2 state, and T3 state. CH from register memory 2 in T1 state
Read n control data. In the T2 state, the arithmetic processing by the arithmetic unit 3 is performed. In the T3 state, the transmission data is assembled and output based on the result calculated by the calculation unit 3.

[0008]

In the above-mentioned conventional data transmission circuit, when the corresponding channel data is transmitted by the external CH NO, the corresponding channel data can be transmitted only after the calculation. . Therefore, it is unavoidable that there is a certain bit phase difference between the transmission data. Furthermore, if the number of transmission request bits from the outside can be arbitrarily changed depending on the channel, it becomes difficult to further define the phase difference.

This will be described with reference to the drawings. FIG. 13 is a diagram showing the timing of channel data transmission. (A)
Shows the case where CH n is 4 bits and CH m is 8 bits. In this case, since 4-bit data comes before 8-bit data, no overlap occurs between CH n data transmission at the timing of T3 and the next CH m data transmission. However, as shown in (b), CH n is 8
If the next CHm is 4 bits, C
While the data transmission of H n is not completed, the data transmission of the next CH m starts and the data transmission of 2CH overlaps as shown in the figure.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a transmission memory control circuit in which transmission data does not overlap.

[0011]

FIG. 1 is a principle block diagram of the first invention, and FIG. 2 is a principle block diagram of the second invention. The same parts as those in FIG. 11 are designated by the same reference numerals.
In FIG. 1, 11 is a memory for storing transmission data, 1
Reference numeral 2 is a register memory that receives a channel number and stores control data of the corresponding channel. Reference numeral 13 is an arithmetic operation for adding various arithmetic operations to transmission data read from the memory 11 based on the control data given from the register memory 12. The unit 14 is a sending memory which receives the output from the arithmetic unit 13 and writes it in the inside thereof in synchronization with the channel clock.

In FIG. 2, reference numeral 20 is a timing generator which receives a CH clock and generates various timing signals. Other configurations are the same as those in FIG. The output of the timing generation unit 20 is stored in the transmission memory 14, the calculation unit 13, and the memory 11.

[0013]

[Action]

(First Invention) The output of the arithmetic unit 13 is output as transmission data via the transmission memory 14. All of the transmission data once enters the transmission memory 14 and is then output from the transmission memory 14, and for example, the CH transmission data of CH NOn-1 CH is transmitted at the input timing of CH NOn. With such a configuration, it is possible to provide the sending memory control circuit in which the sending data does not overlap. (Second invention) A transmission memory 14 is provided in order to prevent overlapping of transmission data. In this case, if the sending memory 14 absorbs the synchronization between the line clock and the system clock, the writing timing and the reading timing with respect to the memory may overlap.
This is because, as the system clock is fixed, if the line clock is arbitrarily taken, the write happens to hit the read time. Therefore, in order to avoid this, the timing generation circuit 20 is provided to shift the write timing by 1τ (the read timing may be the same) so that the write timing and the read timing do not overlap. did.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 3 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals. In the figure, reference numeral 15 is a latch that holds a CH NO input with a CH clock, and 16 is a para-serial conversion unit that converts the output (parallel data) of the transmission memory 14 into serial data and outputs it as transmission data.

CH NO is applied to the data input D of the latch 15.
Is input, and the CH clock is input to the clock input ck. A control signal from the timing generator 20 is input to the write input WE of the memory 11, and the Q output (CH NO) of the latch 15 is input to the address input. The output of the arithmetic unit 13 is input to the data input Din, and the data output Dout is input to the arithmetic unit 13.

The output of the arithmetic unit 13 enters the sending memory 14, the output of the timing generating unit 20 enters the write input WE of the sending memory 14, and the latch 15 enters the address input.
Q output (CH NO) is input, and the output of the sending memory 14 is input to the data input D of the parallel / serial conversion unit 16.
The output of the timing generator 20 is input to the parallel / serial converter 16 as a clock input, and the transmission data is output in synchronization with this clock. The operation of the circuit thus configured will be described below. (First invention) As a method for preventing the overlap of the above-mentioned transmission data, there is a method of reading out the data from the FIFO by storing the data in the FIFO after completion of the calculation for the corresponding channel, and a dedicated memory for each channel. There is a method of storing the data in a memory after completion of the calculation. A method of storing the corresponding channel in the FIFO may be used, but the control becomes complicated. Therefore, here, a method of providing a dedicated memory will be used.

When CH NO is input to the memory 11 as an address, the data stored in the address corresponding to this address is read. The read data enters the arithmetic unit 13, and the arithmetic unit 13 performs operations such as CRC calculation, flag addition, and 0 insertion. The data calculated in this manner is written to the same address as necessary and is given to the sending memory 14.

The timing generator 20 gives a write signal to the WE terminal when the calculation result is output from the calculator 13, and writes the write signal in the sending memory 14. At this time, the stored address is the address accessed by CH NO given from the latch 15.

In this way, the calculation result for each channel is written in the sequential sending memory 14. Then, when there is a transmission request for the same channel, the contents previously stored in the memory 14 are transmitted. That is, n C
When there is a request to send H, the contents of the n-1CH before that are sent. The transmitted data is converted to parallel data by the parallel / serial conversion unit 16 and then output as transmission data.

It is sufficient to have as many addresses as the number of channels that can be transmitted in the transmission memory 14, and the transmission channel request is
There is no problem in any order of CH NO because all that is required is to enter the address. By doing so, it becomes possible to transmit the transmission data to the channel for which the transmission request is made, at a predetermined timing. In addition, the transmission data can be assembled regardless of what CH NO is input. (Second invention) FIG. 4 shows a write enable signal * WE (*
Is a diagram showing a specific configuration example of the creation circuit,
A circuit in which a part of the timing generator 20 is extracted is shown. In the figure, U1 is a latch that receives the CH clock at the D input and the * line clock at the clock input ck, G1 is an AND gate that receives the * Q output of the latch U1 and the line clock, and U2 is the output of the AND gate G1 at the D input. , Clock ck2 at the clock input ck.
Here, ck2 indicates the trigger by the falling edge of the master clock (system clock).

U3 is a latch which receives the Q output of the latch U2 at its D input and receives the clock ck1 at its clock input ck. Here, ck1 indicates a trigger by the rising edge of the master clock. G2 is an OR gate that receives the write enable signals * WE and * HT6 signals.
Here, * HT6 indicates an inverted signal of t6 in the internal operation cycles t1 to t6 in the operation unit 13. Figure 1
The T2 state which is the operation state in 2 is t1 to
It is composed of a cycle of t6.

G3 is the output of the OR gate G2 and the latch U3.
OR gate, which receives the output of
The OR gate receives 1 to t6 and write enable * WE. U4 is a latch which receives the Q output of the latch U3 at its D input and receives the clock ck1 at its clock input ck. G
Reference numeral 5 is an OR gate for receiving the Q output of the latch U3 and * Q output of the latch U4, and G6 is an OR gate for receiving the output of the OR gate G5 and the output of G4. G7 is an OR gate G3
An AND gate for receiving the outputs of G6 and G6, and a sending memory 14 for receiving the output of the AND gate G7 as a write enable signal * WE.

The output of the AND gate G7 enters the write enable signal * WE to the sending memory 14 as active low and enters the write enable signal RE as active high. The operation of the circuit thus configured will be described below with reference to the time chart.

First, description will be made with reference to the time chart of FIG. In the figure, (a) shows the master clock MCK
(Also referred to as system clock), (b) is a line clock, (c) is a CH clock indicating a channel break,
(D) is 8-bit data composed of B1 to B8. The system clock (a) and the line clock (b) are not synchronized as shown in the figure.

(E) is the output (latch) of the AND gate G1, (f) is the Q output of the latch U3 (), and (g) is the internal cycle of the operation unit 13, which is 6 cycles from t1 to t6. (H) is the inverted signal of t6 (* HT6),
(I) is a write enable signal. The write enable signal is generated in low active in synchronization with the internal cycle as shown in the figure.

(J) is the * Q output of the latch U4 (),
(K) is a signal indicating the "1" state during the internal cycles t1 to t6, (l) is the output of the OR gate G5 (), (m)
Is a read (R) / write (W) address switching signal.

In the circuit of FIG. 4, normally, the line clock becomes a pulse as shown in (f) as a signal synchronized with the system clock by the latches U2 and U3. On the other hand, the output of the OR gate G2 issues a low active pulse during the internal cycle t6. This signal is OR gate G
After 3 go into Andgate G7. The other input of the AND gate G7 is always "1". The reason is shown below.

As shown in (k) and (i), t1 to t6
Is always "1", the output of the OR gate G4 maintains "1" even if the write enable * WE becomes low active. As a result, this "1" level enters the AND gate G7 as "1" via the OR gate G6.

As a result, (i)
The low active pulse corresponding to t6 of the above enters the sending memory 14 as the * WE signal. Looking at the timing at this time, the writing mode W is set from (m). Therefore, write mode and read mode do not overlap,
It can be written by the output of the AND gate G7. Note that * WE shown in (i) and the output of the AND gate G7 *
Note that it is different from WE. * WE shown in (i)
Has a continuous pulse, and has only one pulse.

5 to 8 are all in the W mode from the timing (m) when the write enable * WE is output, the same as the timing of FIG.
The t6 cycle of WE can be used as the write enable signal of the transmission memory 14.

Here, when the system clock (MCK) and the line clock are significantly deviated from each other as shown in FIGS. 9 (a) and 9 (b), the Q output of the latch U3 is extended as shown in (f). Then, the low active pulse of the t6 cycle of the OR gate G2 is masked. This timing is (m)
As is clearer, it is still in the read R mode. If the low active pulse of t6 is output as * WE as it is, the read mode and the write mode will overlap. Therefore, the output of the OR gate G2 is masked by the synchronizing signal.

On the other hand, at this time, the * Q output of the latch U4 is
The "0" state continues as shown in (j). Here, if the OR gate G5 is used for OR, the output will be as shown in (l). This signal and the low active of the * WE signal output from the OR gate G4 are followed by the OR gate G6. As a result, the output of the OR gate G6 is delayed by 1τ from the t6 cycle. Looking at the timing at this time, the (m) shows the W cycle, and no overlap occurs. in this way,
In the case where the read R mode and the write W mode overlap, the writing can be delayed by 1τ to avoid the mode overlap.

In the above embodiment, the case where the write timing is sent by 1τ with respect to the read timing has been described as an example, but the present invention is not limited to this. A configuration in which the read timing is delayed by 1τ with respect to the write timing is also possible.

[0034]

As described above in detail, according to the present invention, it is possible to firstly provide a transmission memory control circuit in which transmission data does not overlap with each other, and secondly, write to the transmission memory. It is possible to provide a transmission memory control circuit in which the read mode and the read mode do not overlap.

[Brief description of drawings]

FIG. 1 is a principle block diagram of a first invention.

FIG. 2 is a principle block diagram of a second invention.

FIG. 3 is a configuration block diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing a specific configuration example of a write enable signal generation circuit.

FIG. 5 is a time chart showing the operation of the write enable signal generation circuit.

FIG. 6 is a time chart showing the operation of the write enable signal generation circuit.

FIG. 7 is a time chart showing the operation of the write enable signal generation circuit.

FIG. 8 is a time chart showing the operation of the write enable signal generation circuit.

FIG. 9 is a time chart showing the operation of the write enable signal generation circuit.

FIG. 10 is a conceptual diagram of a conventional exchange system.

FIG. 11 is a block diagram showing a configuration example of a conventional circuit.

FIG. 12 is a diagram showing operation timing of a conventional circuit.

FIG. 13 is a diagram showing a timing of CH data transmission.

[Explanation of symbols]

 11 memory 12 register memory 13 arithmetic unit 14 sending memory

Front page continued (72) Inventor ▲ Taka ▼ Ryoji Nora 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Minoru Nakahara, 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Communication Systems Co., Ltd.

Claims (4)

[Claims] 1. A memory (11) for storing outgoing data
A register memory (12) for receiving the channel number and storing the control data of the corresponding channel; and, based on the control data given from the register memory (12) for the transmission data read from the memory (11). A transmission memory control circuit comprising a calculation unit (13) for applying various calculation processes, and a transmission memory (14) which receives an output from the calculation unit (13) and writes the data therein in synchronization with a channel clock. 2. The data stored in the transmission memory (14) is synchronized with a change in the channel number, and the data of the immediately preceding channel is output as transmission data. The transmission memory control circuit according to claim 1. 3. A memory (11) for storing outgoing data.
A register memory (12) for receiving the channel number and storing the control data of the corresponding channel; and, based on the control data given from the register memory (12) for the transmission data read from the memory (11). An arithmetic unit (13) for applying various arithmetic processings, a transmission memory (14) for receiving the output from the arithmetic unit (13) and writing it in the channel in synchronization with the channel clock, and the transmission memory for receiving the channel clock (14),
A sending memory control circuit including a timing generator (20) for applying a timing signal to the arithmetic unit (13) and the memory (11). 4. The timing generator (20) sets one of the timings to 1 in order to prevent the write timing and the read timing from and to the sending memory (14) caused by the phase shift between the line clock and the system clock. 4. The transmission memory control circuit according to claim 3, wherein the transmission memory control circuit is arranged so as to be shifted in cycles.