JPH06152608A - Precharge system bus circuit - Google Patents

Abstract

PURPOSE:To obtain a hierarchical bus circuit with simplicity, high speed and low power consumption. CONSTITUTION:A high-order data bus 1 in a precharge cycle is discharged by a precharge transistor(TR) 2. A low-order data bus 12 is charged up to a power supply potential by a precharge TB 11. When the terminal RD of a transfer source register is at a high level and the level of stored data is low in the transfer cycle, the bus is discharged. When the terminal WR of a transfer destination register is at a high level, data are fetched from the bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus circuit used in a microprocessor, a digital signal processor or the like, and more particularly to a precharge for precharging a bus in a precharge cycle and for transferring data in a transfer cycle. The method relates to a bus circuit.

[0002]

2. Description of the Related Art As a conventional technique for increasing the speed of a precharge type bus circuit, for example, JP-A-3-7712 is known.
As disclosed in Japanese Patent Publication No. 9, a bus circuit is hierarchized to selectively perform data transfer between bus layers according to a data transfer path. According to this, since the bus circuit is divided, the bus capacitance such as wiring capacitance is divided and high-speed operation becomes possible.

The above prior art will be described below with reference to FIG. In FIG. 3, a block 30 includes a lower data bus 12, a precharge transistor 11 that charges the lower data bus 12 to a power supply potential immediately before data transfer,
Of the lower data bus discharge circuit 34 that discharges the lower data bus 12 when the upper data bus 1 is discharged and one of the registers in the block 30 is selected as the transfer destination; A register selection circuit 35 that discharges the upper data bus 1 when any one of them is selected as a data transfer source and the data is at a discharge level, and a register 3 that is a data transfer source or a transfer destination.
, 3a, 33b ... The input terminal in of the register is connected to the lower data bus 12.

The output terminal out of the register is connected to the input terminal of the register selection circuit 35. A plurality of blocks having the same function as the block 30 are connected to the upper data bus 1 like a block 40. Data can be transferred between any two registers via the upper data bus 1 in the same block or in different blocks. The precharge transistor 42 charges the upper data bus to the power supply potential immediately before data transfer. An inverted signal of the precharge control signal P1 is connected to the gate terminals of the precharge transistors 42 and 11.

Next, a conventional precharger having the above structure
The operation of the bus system for the bus system will be described. In the precharge cycle, the inverted signal of the precharge control signal P1 becomes low level, and the lower data bus 12 and the upper data bus 1 respectively pass through the precharge transistors 11 and 42 which are P channel MOS transistors. Is charged to the power supply potential.

In the transfer cycle, the lower data bus discharge circuit 34 discharges the upper data bus 1 and selects one of the registers (33a, 33b, ...) In the block 30 as the transfer destination. Discharge the lower data bus when The register selection circuit 35 is
Registers in the block 30 (33a, 33b, ...)
When any one of them is selected as the data transfer source and the data is at the discharge level, the upper data bus 1 is discharged.

[0007]

In the prior art, either the lower data bus discharge circuit 34 or the register selection circuit 35 is used depending on the data transfer direction. That is, when the register becomes the transfer destination, the lower data bus 12
Is discharged, and when it becomes the transfer source, the upper data bus 1
To discharge. The data buses that discharge are different, and are not truly hierarchical busses. Therefore, the control circuit for data transfer is complicated.

The present invention has been made in view of the above problems, and an object thereof is to provide a bus circuit having the simplicity, high speed, and low power consumption of a hierarchical bus circuit.

[0009]

A precharge type bus circuit of the present invention comprises an upper data bus and the upper data bus.
First precharge means for discharging the bus in a precharge cycle, a plurality of lower data buses, and second precharge means for precharging each of the lower data buses in a precharge cycle And a plurality of buffer circuits for respectively coupling the upper data bus and the plurality of lower data buses and bidirectionally transmitting data in a transfer cycle subsequent to the precharge cycle. To do.

[0010]

[Function] Upper data in the precharge cycle
The bus is discharged by the first precharge means. The lower data bus is charged to the power supply potential by the second precharge means. In the transfer cycle, the buffer circuit bidirectionally transfers data between any lower data buses via the upper data buses.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram showing a precharge type bus circuit according to the present invention. The bus circuit of the embodiment comprises an upper data bus 1, a precharge transistor 2 for discharging the upper data bus 1, and a plurality of register blocks 18, 28 ... The register block 18 includes a bidirectional buffer 10 for coupling an upper data bus to a lower data bus, a lower data bus 12, a precharge transistor 11 for charging the lower data bus 12 to a power supply potential, and a lower data. It is composed of a plurality of registers 13a, 13b, ... Connected to the bus 12.
The precharge transistor 2 is an N channel MOS transistor, and the precharge transistor 11 is a P channel MOS transistor. Precharge
The drain of transistor 2 is connected to upper data bus 1. A precharge signal P1 is connected to the gate of the precharge transistor 2. One input / output terminal of the bidirectional buffer 10 is connected to the upper data bus 1. The other input / output terminal of the bidirectional buffer 10 is connected to the lower data bus 12. The source of the precharge transistor 11 is the lower data bus 1.
Connected to 2. Precharge transistor 11
An inverted signal of the precharge signal P1 is connected to. The input / output terminals of the registers 13a, 13b ... Are connected to the lower data bus 12. When the read control terminal RD of the register is high level, it indicates that this register is the transfer source, and when the stored content of the register is low level, the lower data bus is discharged. When the write control terminal WR of the register is at the high level, it indicates that this register is the transfer destination, and the data is taken in from the lower data bus.

The bidirectional buffer 10 comprises P channel MOS transistors 10a and 10b and an N channel MOS transistor 10c. The drain, gate, and source of the transistor 10a are connected to the power supply 5, the precharge control signal P1, and the drain of the transistor 10b, respectively. The drain, gate, and source of the transistor 10c are connected to the gate of the transistor 10b, the source of the transistor 10b, and ground, respectively.

FIG. 2 shows the timings of the signal P1 for controlling each precharge transistor and its inverted signal, the transfer source register control signal RD, and the transfer destination register control signal WR. The first half of one cycle of data transfer
In the first cycle, the precharge control signal P1 is at a high level and its inverted signal is at a low level.
The bus is precharged. Second half (transfer cycle)
Then, the precharge control signal P1 goes low, its inverted signal goes high, and RD of the transfer source register and WR of the transfer destination register go high, so that data transfer is performed. In the precharge cycle, the precharge transistor 2 turns on and the upper data bus 1 is discharged through the precharge transistor 2. Similarly, in the precharge cycle, the precharge transistor 11 is turned on, and the lower data bus 12 is charged to the power supply potential via the precharge transistor 11.

In the transfer cycle, the RD of the transfer source register
Is high and the stored data is low, the lower data bus is discharged. When the WR of the transfer destination register is high level, data is taken in from the lower data bus.

With such a bus structure, all the registers connected to the lower bus can exchange data with each other. There is no limit to the number of lower buses, and any connection is possible as long as the lower buses are connected via the buffer circuit.

In the bus circuit having the above structure, the circuits other than the bidirectional buffer are the same as the basic bus structure having no hierarchical structure and are very simple. Since the bidirectional buffer divides the bus capacity, the speed can be increased. Further, if the power supply voltage of the bidirectional buffer is set lower than that of other circuits, only the signal amplitude of the bus can be reduced and power consumption can be reduced.

[0017]

As described above, the precharge type bus circuit of the present invention comprises a high-order data bus, a first precharge means for discharging the high-order data bus in a precharge cycle, and a plurality of high-order data buses. A lower data bus, a second precharge means for precharging each of the lower data buses in a precharge cycle, the upper data bus and the plurality of lower data buses are respectively coupled. Since a plurality of buffer circuits for bidirectionally transmitting data in the transfer cycle subsequent to the precharge cycle are provided, a bus circuit having a simple circuit configuration and high speed can be provided. Further, a bus circuit with low power consumption can be provided by lowering the power supply voltage of the bidirectional buffer.

[Brief description of drawings]

FIG. 1 is a diagram showing a precharge bus circuit according to the present invention.

FIG. 2 is an operation timing chart of the bus circuit shown in FIG.

FIG. 3 is a block diagram showing a conventional technique for increasing the speed of a precharge type bus circuit.

[Explanation of Codes] 1, 12 Data Bus 2, 11 Precharge Transistor 10 Bidirectional Buffer

Claims (3)

[Claims] 1. An upper data bus and the upper data bus
First precharge means for discharging the bus in a precharge cycle, a plurality of lower data buses, and second precharge means for precharging each of the lower data buses in a precharge cycle And a plurality of buffer circuits for respectively coupling the upper data bus and the plurality of lower data buses and bidirectionally transmitting data in a transfer cycle subsequent to the precharge cycle. Pre-charge type bus circuit. 2. The buffer circuit comprises a first P-channel MOS transistor having a drain connected to a power supply and a gate connected to a precharge control signal, and a drain connected to a source of the first transistor. 2 P-channel MOS transistor and the drain is the second
3. A precharge according to claim 1, wherein the precharge comprises a third N-channel MOS transistor whose gate is connected to the gate of the second transistor, and whose gate is connected to the source of the second transistor and whose source is connected to the ground. Method bus circuit. 3. The power supply voltage value of the buffer circuit is lower than the power supply voltage values of the other circuits.
The precharge bus circuit described in.