JPS58200321A - Bus interface circuit - Google Patents

Abstract

PURPOSE:To perform high-speed operation by performing clock control over a transfer gate and the gate of a specific MOS transistor (TR). CONSTITUTION:Buses 1 and 2 are connected to an interface 3. It is assumed that a larger load is connected to the bus 1 than the load connected to the bus 2. The interface 3 consists of CMOSTRs; P channel TRs 4 and 5 and N channel TRs 6 and 7 are connected in series. The bus 2 is connected to the gates of the TRs 5 and 6 and the bus 1 is connected to the output of a CMOS inverter; the buses 1 and 2 are connected to each other through the transfer gate 8. The transfer gate 8 and the gates of the TRs 4 and 7 are connected to the outputs of OR gates 9 and 10, which input the negative-phase clock phi' of a clock phi. Thus, high-speed operation is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus interface circuit that realizes a high-speed bus system.

Conventionally, the line of a digital integrated circuit, etc., was placed in a high impedance state when not in use, and a circuit was added to fix it at an .

On the other hand, when the bus is divided, a bidirectional bus driver is used as an interface circuit, and two 3-state buffers are switched to connect the bus and control the data transfer direction.

The present invention aims to realize an interface circuit that has both the functions of a bus potential fixing circuit and an interface circuit, and also provides an interface circuit that has a small number of elements and can operate at high speed.

An embodiment of an interface circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a digital integrated circuit including a Sun-Tzu interface circuit according to the present invention, and FIG. 2 shows its operation timing diagram.

As shown in Figure 1, the bus 1 and bus 2h interfaces have a larger load (many registers, memory).

Assume that a stray capacitance) is connected. Interference transistors 4, 5' and N-channel transistors 6.3 and 7 are connected in series. Bus 2 is transistor 5,
Bus 1 is connected to the output of the CMOS inverter, and Bus 1 and Bus 2 are connected through an N channel transfer gate 8. The gates of the transfer gate 8 and the transistor 4.7 are connected to the outputs of the OR gates 9, 1o (two OR gates)9.
A countertransition phase φ of the clock φ is inputted to 10.

It is assumed that this digital integrated circuit performs processing such as data transfer in synchronization with lock φ, that is, during the high level period of φ. Then, the low level period of clock φ is 1. Data transfer is not performed and the pass line is held in a high impedance state. In the case of this embodiment, the transfer gate 8 and the transistors 4 and 7 are turned on during the period when the clock 7 is at a high level (period shown in FIG. 2),
The input and output of the CMOS inverter are connected, and the power supply type) □,
1 midpoint between voltage vDD and ground potential (usually VDD/2
It is fixed in equilibrium at a potential of Therefore, bus 1 and bus 2 are simultaneously charged and discharged to an intermediate potential, and the potential is held while the clock T is at a high level.

When φ enters the low level period (periods I and II in FIG. 2), the buses 1 and 2 are charged and discharged from the maintained intermediate potential to VDD or the ground level by the data carried on the buses. Since the battery is charged and discharged from an intermediate potential in this manner, the response times for data 0 and 1 are approximately equal to 11. For example, if the bus potential is held at the power supply voltage vDD or the ground level, there will be no current bus, but the bus potential will need to be charged and discharged to an extent equivalent to the wire voltage, which will increase the response speed. However, this embodiment does not have such a drawback.

Next, the function of the bus interface 7 will be explained. A register 11 (assuming an address) and a register 12 (assuming an address A1) are connected to the bus 1 via three-state devices 7A 13-16. The input buffer 13 of the register is controlled by the AND output 17 with the address signal of the register 11 and the write signal W5 page, and the output buffer 14 from the register 11 is controlled by the address signal and the read signal R of the register 11.
and the AND output 18. register 12
Similarly, buffers 15 and 16 are controlled by AND outputs 19 and 2o of address signal A1 and write and read signals. One bus 2 has a register 21 ((address B)) with a 3-state buffer 7.
22° Connected via 3-state inverter 23, address signal B. AND with write W and read signal R
Data input/output from bus 2 is controlled by outputs 24 and 25.

When clock \ is low (period of FIG. 2), control of interface .beta. is performed by control signals 26 and 27.

During period I, the signal 26 is high and the signal 27 is low, so the transfer gate 8 is not in the 9FF state, and a CMOS inverter is formed in the interface 3 to invert and amplify the signal on the bus 2 and send it to the bus 1 with a large load. . At that time, as shown in FIG. 2, if AND6 page outputs 25 and 17 are .
Transferred to 1. If the data to be transferred is 1, bus 1
As shown in Figure 2, the changes in the power outage are shown at the intermediate potential.
: It works as it charges up to vDD.Next, in period ■, signals 26 and 27 both become low, so transfer gate! 3 vaporized transistors 4 and 7 are O
Due to the N state, the potential of bus 1 is discharged from vDD to an intermediate potential. Bus 2 is charged from GND and becomes a medium-heavy color.

When the signal 26 becomes low and the signal 27 becomes high during period ■, the transfer gate 8 is turned on, and the transistors 4 and 27 become high.
Since 7 is in the OFF state, the two buses are connected. At this time, if the AND outputs 20 and 24 are high, the data (for example, 0) in the register 12 is transferred to the register 21. The two buses are both discharged from the intermediate potential to the GND potential.

Furthermore, if the signals 26 and 27 are both low and 1 and the clock T is low, the two buses are completely separated and data transfer between the registers 11 and 12 is possible for the 7-page bus 1.

As described above, in this embodiment, the clock pulse i and the control signal 2
The combination of 6.27 allows two buses to be separated and connected to control the direction of data transfer. In addition, the bus potential is held at an intermediate potential during a half cycle of the clock, thereby speeding up the bus response time. In addition, in Fig. 1, 28 is A
It is an ND gate.

As described above, according to the bus interface circuit according to the present invention, buses can be easily separated and connected, thereby simplifying bus separation and system design.

Furthermore, since the bus is held at an intermediate potential by determining the period during which the bus becomes high impedance, the response speed of the bus is fast and faster data transfer is possible. In this way, since the interface circuit also serves as the intermediate potential holding function, there is no need to add a Bunadown pull-up circuit like in the past.
The number of elements can be reduced accordingly. Therefore, the bus interface circuit according to the present invention easily realizes a high-speed and flexible bus system that is suitable for increasing the scale and speed of digital integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital integrated circuit in one embodiment of the present invention, and FIG. 2 is a timing diagram for explaining its operation. 1.2...Bus, 3.Interface, 4゜5,6,71,-1.,transistor,8.
River...Transfer gate, 9,10・Song・6R gate, 11, 12゜21...Register, 13,
14, 15, 16.22...3 state buffer, 23...3 state inverter, 17
, 18, 19, 20, 24, 25...AND output, 26.27...music control signal, 28...AN
D gate.

Claims (1)

[Claims] In series connection, one conductivity type first. a second MOS transistor, a transistor of the other conductivity type connected in series, and the second MOS transistor. a third MOS) comprising a transfer gate connected between a drain common connection point and a gate common connection point of the transistor, the tone slave gate and the -1st and -1st MOS transistors; Mo of
s trough Iyu. A bus interface circuit characterized by hack control of game i.