JP2697635B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit including a domino circuit constituted by a dynamic logic circuit.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a conventional example of this type of domino circuit. This domino circuit has a power supply V at one end.
_DD has the other end connected to the storage node 7, a gate for inputting a signal from the clock input terminal 1, a precharge transistor 3, an output inverter 4 connected to the storage node 7, a power supply V _DD and a storage node 7. And a transistor 5 whose gate is connected to the ground GND, and which is connected to one end of the storage node 7 and is turned on or off according to the logic of the input signal 9.
The MOS logic circuit 2 is connected between the other end different from the one end connected to the storage node 7 of the nMOS logic circuit 2 and the ground GND, and has a gate connected to the charge extracting transistor 6 connected to the clock input terminal 1. It is composed of

The precharge transistor 3 precharges the nMOS logic circuit 2 to the level of the power supply _VDD when the signal input from the clock input terminal 1 is at "0" level, and changes the output of the output inverter 4 to "0". Level. When the signal of the clock input terminal 1 becomes “1”, when the condition of the nMOS logic circuit 2 is on, the charge is transferred to the ground G via the charge extracting transistor 6 grounded to the ground GND.
Data is read out by being discharged to ND and inverting the output of the output inverter 4. In addition, during low-frequency operation, if the off state of the precharge transistor 3 continues for a long time, the charge of the storage node 7 is released due to leakage of a transistor included in the circuit, and the output of the output inverter 4 malfunctions and is inverted. The weak charge holding transistor 5 is turned on to supply charges. Further, in domino circuit of the semiconductor integrated circuit disclosed in JP-63-56017, in order to prevent a malfunction of the output inverter 4 due to leakage of the transistor, the power supply V _DD and the charge retaining transistors as shown in FIG. 6 5 and the gate of the charge holding transistor 5 is connected to the output inverter 4 to turn on the charge holding transistor 5 only when the output of the output inverter 4 is "0". On the other hand, the precharging of the output inverter 4 and the nMOS logic circuit 2 is performed again by appropriately turning on the control transistor 8 using the auxiliary control signal.

[0004]

In the conventional domino circuit shown in FIG. 5, the charge holding transistor 5 is always operating, and the discharging operation from the charge extracting transistor 6 is prevented, so that the data reading speed is reduced. In addition, since the charge holding transistor 5 always operates and supplies current even during discharging, there is a problem that power consumption increases.

In the domino circuit of FIG. 6, during the execution period other than the precharge period, the charge holding transistor 5 is turned on whenever the output of the output inverter 4 is "0". There is no. Also, when the control transistor 8 is turned off when discharging from the charge extraction transistor 6, the power supply V _DD
And does not draw the discharge current. However, there is a problem that the data reading speed is reduced because the charge retaining transistor 5 becomes a load of the output inverter 4.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit using a domino circuit which prevents malfunction of the circuit due to transistor leakage and prevents unnecessary power consumption even when the read time of the domino circuit is long at low frequency operation. To provide.

[0007]

A domino circuit of a semiconductor integrated circuit according to the present invention has one end connected to a first power supply terminal, the other end connected to a storage node, and a clock signal input from a clock input terminal to a gate. A precharging transistor, an output inverter connected to the storage node, a logic circuit having one end connected to the storage node, and having a conductive state or a non-conductive state according to a predetermined logic of a signal input from the outside; A charge extraction transistor connected between a second power supply terminal and another end different from the one end connected to the storage node of the circuit and having a gate connected to the clock input terminal; a first power supply terminal and the storage node; Between the clock input terminal and the gate of the charge holding transistor. When the signal level exceeds the predetermined period for keeping the precharge transistor in the non-conductive state, the charge holding transistor is made conductive, and when the duration is within the predetermined period, the charge holding transistor is turned off. And a control circuit for turning on.

According to another aspect of the present invention, the above-described domino circuit further includes a leak compensation control transistor in series with the charge holding transistor between the first power supply and the storage node. The gate of the transistor is connected to the output of the output inverter.

Further, according to another aspect of the present invention, in each of the two aspects described above, a plurality of blocks except for the control circuit from the domino circuit are cascaded to form an aggregate block, and each block has a common configuration. Is connected between the clock input terminals of the one-stage block and the gates of the charge holding transistors of all the blocks, and the level of the input clock signal turns the precharge transistor of each block into a non-conductive state. When the continuation time exceeds a predetermined period, the charge holding transistor is turned on, and when the continuation time is within the predetermined period, the charge holding transistor is turned off.

[0010]

According to the present invention, by using the domino circuit having the above-described configuration, the off state of the precharge transistor can be maintained for a long time in the case of low frequency operation, or the precharge transistor can be turned off in the case of low frequency operation. When the off state continues for a long time and there is a concern about the actual leakage of charge from the storage node, the control circuit can be used to appropriately perform the precharge again, thereby eliminating the risk of malfunction. Also, at the time of discharging by the logic circuit, by turning off the charge holding transistor by the control circuit, it is possible to prevent the discharge current from being drawn from the power supply.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1A is a block diagram showing the configuration of a first embodiment of a domino circuit included in a semiconductor integrated circuit according to the present invention.

The basic configuration of this embodiment is the same as that of the conventional example shown in FIG. 5, and the components having the same numbers and the same names have the functions corresponding to those of FIG. . However, in the case of the present embodiment, the gate of the charge holding transistor 5 is not connected to the ground GND, and the control circuit 10 which is a feature of the present application is provided between the clock input terminal 1 and the gate of the charge holding transistor 5. ing.

As shown in FIG. 1B, the control circuit 10
When the cycle of the signal input from the clock input terminal 1 is a normal cycle, the output C thereof keeps the “1” level.
When the period of the signal input from the clock input terminal 1 is extended and the off time of the precharge transistor 3 exceeds the time T ₀ as shown in FIG. 1C, the output C of the control circuit 10 becomes “0” level. When the signal input from the clock input terminal 1 goes to the "0" level again and enters the precharge period of the circuit, the output C of the control circuit 10 is inverted to the "1" level. Such a control circuit 10 can be easily formed using an integration circuit.

Next, the operation of this embodiment will be described.

When the signal input from clock input terminal 1 is at "0" level, storage node 7 on the input side of nMOS logic circuit 2 and output inverter 4 is precharged to the level of power supply _VDD by transistor 3 for precharging. When the signal is charged and the signal from the clock input terminal 1 is at the “1” level, the precharge transistor 3 is turned off and nM
The charge is extracted from the storage node 7 via the charge extracting transistor 6 connected to the ground GND depending on the condition of the OS logic circuit 2. The operation of the charge holding transistor 5 at the input of the output inverter 4 is controlled by the control circuit 10. As described above, in the normal operation, the control circuit 10 does not move while the output C is kept at the "1" level as shown in FIG. 1B, so that the charge holding transistor 5 is not turned on. Moreover, when operated at a low frequency, the output C is "1" level to the "0 when a" 1 "level signal is longer than the time T ₀ as shown in FIG. 1 (c) of the control circuit 10 Change to the "level." Therefore, when the output C becomes the “0” level, the charge holding transistor 5 is turned on, and the charge is supplied to the storage node 7. By providing the control circuit 10 and the charge holding transistor 5 that perform such operations, it is possible to prevent the leakage of the recording node 7 that occurs only during low-frequency operation without affecting the speed during normal operation. Become. During normal operation, the charge holding transistor 5
Since no more charge is supplied, wasteful increase in power consumption can be prevented.

[0017] Figure 2 shows a configuration of a second embodiment of the present invention, with reference to cascaded first embodiment the N domino circuit 12 ₁ to 12 _N, except for the control circuit 10 of the above I have. In this case, one control circuit 10 is used in common to the N stages, and the output C receives a signal from the clock input terminal 1 and partitioned charge retaining transistor 5 of the domino circuits 12 ₁ to 12 _N . Control circuit 10 and each domino circuit 12 ₁
The individual operations of .about.12 _N are the same as those in the first embodiment. With such a configuration, it is possible to cope with the logic of a larger number of input signals 9.

Next, FIG. 3A is a diagram showing the configuration of a third embodiment of the present invention.

The basic structure of the present embodiment is the same as that of the first embodiment, but a leak compensation control transistor 20 is further provided between the charge holding transistor 5 and the storage node 7 to provide a leak compensation. The gate of the control transistor 20 is connected to the output side of the output inverter 4.

FIG. 3B is a timing chart when the embodiment is operated at a low frequency.

Since the leakage compensation control transistor 20 is controlled by the output signal of the output inverter 4, if the output of the output inverter 4 is "0" during an execution period other than the precharge period, the leakage compensation control transistor 20 is turned on. Is done. The charge holding transistor 5 is turned on when the read time of the domino circuit exceeds the time T ₀ during the low-frequency operation, as in the first embodiment. Therefore, storage node 7 is set to the level of power supply V _DD only when charge holding transistor 5 and leak compensation control transistor 20 are both in the ON state, that is, when there is actually a fear of charge leakage from storage node 7. It is precharged and can cancel the effect of leak.

[0022] Figure 4 shows the structure of a fourth embodiment of the present invention, with reference to cascade a third embodiment the N domino circuit 13 ₁ to 13 _N, except for the control circuit 10 of the above I have. One control circuit 10 is used in common to the N stages, and the output C receives a signal from the clock input terminal 1 and partitioned charge retaining transistor 5 of the domino circuits 13 ₁ to 13 _N. Each operation is the same as that of the third embodiment. With this configuration, it is possible to cope with the logic of a larger number of input signals 9.

[0023]

As described above, according to the present invention, the charge holding transistor is operated using the control circuit when the data reading time is long, such as at the time of low frequency operation, and the input side node is precharged again. Alternatively, the precharge is performed again only when there is actually a fear of leakage by using the leak compensation control transistor, and the charge holding transistor does not operate during other normal operations. No matter how long the read time is, it is possible to prevent a malfunction of the circuit and an unnecessary increase in power consumption.

[Brief description of the drawings]

FIG. 1A is a circuit diagram showing a configuration of a domino circuit according to an embodiment of the present invention, FIG. 1B is a timing chart when the embodiment is operated normally, and FIG. 6 is a timing chart when a low frequency operation is performed.

FIG. 2 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3A is a circuit diagram showing the configuration of a third embodiment of the present invention, and FIG. 3B is a timing chart when the embodiment is operated at a low frequency.

FIG. 4 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional example of a domino circuit.

FIG. 6 is a circuit diagram of another conventional domino circuit.

[Explanation of symbols]

Reference Signs List 1 clock input terminal 2 nMOS logic circuit 3 precharge transistor 4 output inverter 5 charge retention transistor 6 charge extraction transistor 7 storage node 9 input signal 10 control circuit 12 _{1 to} 12 _N domino circuit 13 _{1 to} 13 _N domino circuit 20 Leak compensation control transistor

Claims (4)

(57) [Claims] 1. A semiconductor integrated circuit including a domino circuit constituted by a dynamic logic circuit, wherein the domino circuit has one end connected to a first power supply terminal, the other end connected to a storage node, and the gate connected to a gate. A precharge transistor for inputting a clock signal from a clock input terminal; an output inverter connected to the storage node; one end connected to the storage node, and a conductive state or a conductive state according to a predetermined logic of a signal input from the outside; A logic circuit in a non-conducting state, a charge extraction circuit connected between a second power supply terminal and another end different from one end connected to the storage node of the logic circuit, and a gate connected to the clock input terminal Transistor; a charge holding transistor connected between the first power supply terminal and the storage node; Connected between the input terminal and the gate of the charge holding transistor, and when the level of the input clock signal exceeds a predetermined period of time for keeping the precharge transistor in a non-conductive state, the charge holding A control circuit for turning on the transistor and, when the duration is within a predetermined period, turning off the charge holding transistor. 2. The domino circuit according to claim 1, wherein the same block including a precharge transistor, an output inverter, a logic circuit, a charge extracting transistor, and a charge holding transistor has a plurality of stages. A cascade-connected collective block, connected between the clock input terminal of one block and the gates of the charge holding transistors of all blocks,
When the level of the input clock signal exceeds the predetermined period for keeping the precharge transistor in each block in the non-conductive state, the charge holding transistor is made conductive, and the duration is within the predetermined period. A control circuit common to each block for setting the charge holding transistor to a non-conductive state. 3. The domino circuit further includes a leak compensation control transistor in series with the charge holding transistor between the first power supply and the storage node, and a gate of the leak compensation control transistor is connected to the output of the output node. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to an output of the inverter. 4. The domino circuit according to claim 3, wherein the domino circuit comprises a precharging transistor, an output inverter, a logic circuit, a charge extracting transistor, a charge holding transistor, and a leak compensation control transistor. Is connected between the clock input terminal of one stage block and the gates of the charge holding transistors of all the blocks,
When the level of the input clock signal exceeds the predetermined period for keeping the precharge transistor in each block in the non-conductive state, the charge holding transistor is made conductive, and the duration is within the predetermined period. A control circuit common to each block for setting the charge holding transistor to a non-conductive state.