JPS54142057A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS54142057A
JPS54142057A JP5085878A JP5085878A JPS54142057A JP S54142057 A JPS54142057 A JP S54142057A JP 5085878 A JP5085878 A JP 5085878A JP 5085878 A JP5085878 A JP 5085878A JP S54142057 A JPS54142057 A JP S54142057A
Authority
JP
Japan
Prior art keywords
level
signal
node
becomes
rpc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5085878A
Other languages
Japanese (ja)
Inventor
Akira Osami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5085878A priority Critical patent/JPS54142057A/en
Publication of JPS54142057A publication Critical patent/JPS54142057A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Abstract

PURPOSE:To avoid the malfunction caused by attenuation of the charging level for the RAM circuit by connecting the MOS transistors (MOST) featuring different current capacity in parallel between the power source and one node of the circuit and then controlling the MOST's with the signals of different timing to each other. CONSTITUTION:When RAM basic clock inverse phiTTL shifts to the H-level and enters the reset precharge RPC period, RPC timing signal P becomes the H-level. And at the same time, one-shot RPC timing signal P0 featuring a shorter H-level period than signal P becomes the H-level in synchronization with signal P. The gates of MOSTQ10 and Q11 connected in parallel between node 6 and the earth are controlled by signal P0 and P each. Also, the gates of MOSTQ12 and Q14 connected in parallel between node 7 and power source VDD are controlled by signal P0 and P. As a result, active timing signal phi1 becomes the L-level. When signal inversion phiTTL becomes the L-level and enters the active period, the attenuation of the charging level is prevented at node 7 since the current capacity of MOST11 and 14 are set smaller than those of MOST10 and 12. Thus, a quick rise is secured for signal phi1, accordingly obtaining the steady operation.
JP5085878A 1978-04-27 1978-04-27 Logic circuit Pending JPS54142057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5085878A JPS54142057A (en) 1978-04-27 1978-04-27 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5085878A JPS54142057A (en) 1978-04-27 1978-04-27 Logic circuit

Publications (1)

Publication Number Publication Date
JPS54142057A true JPS54142057A (en) 1979-11-05

Family

ID=12870413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5085878A Pending JPS54142057A (en) 1978-04-27 1978-04-27 Logic circuit

Country Status (1)

Country Link
JP (1) JPS54142057A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07154240A (en) * 1993-10-08 1995-06-16 Nec Corp Semiconductor integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5334438A (en) * 1976-09-10 1978-03-31 Nec Corp Semiconductor circuit using insulating gate type field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5334438A (en) * 1976-09-10 1978-03-31 Nec Corp Semiconductor circuit using insulating gate type field effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07154240A (en) * 1993-10-08 1995-06-16 Nec Corp Semiconductor integrated circuit

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