JPH06150697A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To reliably detect a short circuit in a word line during a fail bit address judgment test. [Structure] A step-up power supply generation circuit 2 that generates a step-up power supply inside a chip, a first external power supply 7 that supplies a voltage equivalent to that of the step-up power supply, and a step-up power supply probe test capable of connecting the first external power supply 7 Pad 1 and step-up power supply probe inspection pad 1 connected to step-up power supply wiring 6 and resistor 8 for voltage drop.
It is a semiconductor integrated circuit characterized by being connected via. [Effect] During the fail bit address determination test, the short-circuited word line potential is lowered to a potential that can be detected by the circuit, and the short-circuited word line is reliably detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a step-up power supply generation circuit for charging a load at high speed,
In particular, the present invention relates to a semiconductor integrated circuit capable of reliably performing a fail bit address determination test for redundancy repair of a defective memory cell in a memory semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit for a memory, a redundancy repairing method of repairing a defective cell by replacing a defective memory cell with a normal cell in order to improve a yield is generally used. The fail bit address judgment test is being performed to identify the address.

An example of a conventional semiconductor integrated circuit will be described below with reference to the drawings. FIG. 6 shows an example of a connection diagram of a boosting power supply probe inspection pad of a conventional semiconductor integrated circuit. In FIG. 6, the word line drive circuit 3 charges the word line to a boosted potential by using a word line driver (not shown) determined by decoding an address to transfer the transfer gate of the selected memory cell. turn on. Step-up power supply probe inspection pad 1
Is connected to the boosted power supply line 6 between the word line drive circuit 3 and the boosted power supply generation circuit 2 that supplies the boosted voltage to the word line drive circuit 3.

With respect to the conventional semiconductor integrated circuit configured as described above, its usage and operation in the early stage of development will be described below.

First, at the time of probing inspection, it is checked whether or not the boosted power supply generation circuit 2 has achieved the capability as designed, by setting the needle 5 on the boosted power supply probe inspection pad 1 to detect the boosted voltage (VPP) and the boosted power supply generation circuit 2. It is possible to measure the current consumption. Further, the boosted power supply generation circuit 2 is a circuit for replenishing the charges originally consumed by the word line inside the chip and has a low current supply capability. Therefore, when the selected word line is short-circuited with another power supply, Current flows more than the capacity of the boosted power supply generation circuit 2.

Therefore, when the selected word line is short-circuited, the potential of the boosted voltage (VPP) drops, and when the next normal word line is selected, the boosted voltage is not restored to the complete potential. This sometimes caused malfunctions. By connecting the first external power supply 7 having a voltage equivalent to the boosted power supply voltage capable of supplying current to the boosted power supply probe inspection pad 1, the malfunction can be prevented. In the chip that has been subjected to redundancy repair after the fail bit address determination test, the current supply capability of the boosted power supply generation circuit 2 is sufficient.

[0007]

However, in the above-mentioned conventional structure, as described below, a short circuit of the word line may be missed during the fail bit address judgment test.

FIG. 7 is an assumed view in which a selected word line and a non-selected word line are short-circuited, and FIG. 3 shows an enlarged view of a part of the circuit in FIG.

In FIG. 7 and FIG. 3, when the selected word line 34 is short-circuited with the non-selected word line 35, the resistance value R2 of the resistor 17 between the step-up power supply generation circuit 2 and the word line drive circuit 3,
The resistance value R3 of the resistor 18 between the word line drive circuit 3 and the ground power supply pad (hereinafter referred to as VSS pad) 4, the resistance value R4 of the resistor 33 in the short-circuited portion 14, the resistance value R5 of the resistor 15 in the selected word line 34, and the selection The resistance value R6 of the resistor 16 of the unselected word line 35 short-circuited with the selected word line 34, the ON resistance Rtr1 of the word line drive signal driving transistor 30, the ON resistance Rtr2 of the word line charging transistor 31, and the word line ground Voltage (VPP) depending on the ratio of the on-resistance Rtr3 of the transistor 32 for use
In the fail bit address judgment test, the decrease in the word line potential due to a short circuit (Equation 1) depends on the arrangement of pads and the position of the short circuit. There is a problem that the word line to be rescued that cannot be detected and is short-circuited may be regarded as a normal word line.

[0010]

[Equation 1]

The present invention solves the above-mentioned conventional problems. In the fail bit address judgment test, the circuit surely senses the decrease in the word line potential due to the short circuit of the word line regardless of the arrangement of the pads and the position of the short circuit. It is an object to provide a semiconductor integrated circuit that can be controlled to a potential that can be adjusted.

[0012]

In order to solve the above-mentioned problems, a semiconductor integrated circuit according to the present invention comprises a step-up power supply probe inspection pad to which a first external power supply for supplying a voltage equivalent to that of the step-up power supply can be connected. A structure for connecting to a wiring for boosting power supply via a resistance for voltage drop, or a boosting power supply probe inspection pad to which a second external power supply for supplying an optimized voltage lower than the voltage of the boosting power supply can be connected, It has a structure connected to the step-up power supply wiring.

[0013]

According to the present invention, with the above configuration, a malfunction caused by a drop in boosted voltage due to a short circuit between the selected word line and another power supply is caused in the fail bit address judgment test at the chip development stage. This is prevented by connecting a first power source having a voltage equivalent to Furthermore, the drop of the word line potential when the word line is short-circuited is controlled by the resistor with the optimum resistance value inserted between the boost power supply generation circuit and the boost power supply probe inspection pad, or instead of inserting the resistance, the boost power supply probe inspection is performed. The pad is controlled by the optimized second external power supply having a voltage lower than the boosted potential, and the redundant repair address of the chip can be surely grasped.

[0014]

【Example】

(Embodiment 1) A semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 1, the boosted power supply generation circuit 2 supplies a voltage to the gate and the source of the word line driver in the word line drive circuit 3, which is not shown in FIG. The word line is selected by the decode signal of the row address, the word line is charged at high speed, and the transfer gate in the memory cell is turned on. The step-up power supply probe inspection pad 1 is connected to the step-up power supply wiring 6 between the word line drive circuit 3 and the step-up power supply generation circuit 2 via the resistor 8 calculated from the pad arrangement and the position of the worst case word line short circuit. It is connected.

Regarding the semiconductor integrated circuit configured as described above, in the fail bit address judgment test,
The operation when the selected word line and the non-selected word line are short-circuited will be described. FIG. 2 is an assumed view when a selected word line and a non-selected word line are short-circuited, and FIG. 3 is an enlarged view of a part of the circuit in FIG.

2 and 3, it is assumed that one selected word line 34 and one unselected word line 35 are short-circuited during the fail bit address determination test. The number of short-circuited non-selected word lines is set to one because the word line potential is the highest in that case. At this time, the resistance value of the resistor 8 inserted between the step-up power supply generation circuit 2 and the step-up power supply probe inspection pad 1 is R1, and the step-up power supply generation circuit 2
And the resistance value of the wiring resistance 17 between the word line driving circuit 3 and R
2, the resistance value of the wiring resistance 18 between the word line drive circuit 3 and the VSS pad 4 is R3, and the wiring resistance 15 of the selected word line 34 is 15.
R5, the resistance value of the wiring resistance 16 of the non-selected word line 35 is R6, and the resistance value of the short-circuit resistance 33 is R
4, word line drive signal drive transistor 3
The on resistance of 0 is Rtr1, the on resistance of the word line charging transistor 31 is Rtr2, and the on resistance of the word line grounding transistor 32 is Rtr3. At this time, if the potential of the boosting power source is VPP, the selected word line 34
Is equal to (Equation 2), and the potential of the selected word line can be surely lowered by optimizing the resistance value R1 of the resistor 8 between the boost power supply probe inspection pad 1 and the boost power supply generation circuit 2. Therefore, it is possible to reliably detect the short circuit of the word line.

[0018]

[Equation 2]

Next, taking the pad arrangements shown in FIGS. 2 and 3 as an example, the optimum value of the resistance value R1 of the resistor 8 added between the step-up power supply generation circuit 2 and the step-up power supply probe inspection pad 1 is actually obtained. View. The optimum value condition is (1) when the selected word line is short-circuited with the non-selected word line, the potential of the selected word line drops sufficiently, and (2) the address is changed to change the selected word line. When changing from a shorted word line to a non-shorted word line,
It is required that the time required for the potential of the word line drive signal to recover to the boosted potential is shorter than the time required for a normal word line to rise after an address change.

First, the condition (1) of the optimum value is imposed, and the lower limit of the resistance value of the added resistance is considered. In such a pad arrangement, the shorted word line has the highest potential when the word line closest to the pad is shorted. The ON resistance Rtr1 of the p-channel transistor 30 for driving the word line drive signal is 200Ω, the ON resistance Rtr2 of the n-channel transistor 31 for driving the word line is 200Ω, and the n resistance for the word line precharge is nΩ.
The on resistance Rtr3 of the channel transistor 32 is set to 45
Assuming that the wiring resistance value R5 of the selected word line 34 and the wiring resistance value R6 of the non-selected word line are equal to 0Ω, R5 = R6 = 2
Let KΩ. Sheet resistance of 1 layer aluminum is 55 mΩ, sheet resistance of 2 layers aluminum is 35 mΩ, wiring width of boosting power supply wiring is 10 μm, wiring length is 4 mm, wiring width of VSS power supply wiring is 50 μm, wiring length is 4 mm, and chip length is 4 mm. If the wiring in the side direction is a two-layer aluminum and the wiring in the short side of the chip is a one-layer aluminum, the resistance value R2 of the wiring resistor 17 for the step-up power supply is 22.
Ω, the resistance value R3 of the VSS power supply wiring resistance 18 becomes 4Ω, and the resistance value R4 of the word line short-circuit point resistance 33 becomes 68.
Ω and the potential of the step-up power supply is VPP, the short-circuited word line potential Vwl is 0.51 when the additional resistor 8 is not inserted.
It becomes VPP.

When the word line potential is the first required in the fail bit judgment test, the memory cell 40 in FIG.
When (VDD) is written and H is continuously read,
If the precharge potential of the bit lines 46 and 47 is 1.5 V and the threshold voltage of the transfer gate 42 in the memory cell is 1 V, the potential of the word line is simply 2 even if the sensitivity of the sense amplifier 41 is not taken into consideration. If 0.5V or more and the boost voltage VPP of the boost power source is 5V, 0.5VPP or more is required. If the sensitivity of the sense amplifier is taken into consideration, a higher word line potential is required. Therefore, in order to set the shorted word line potential to 0.5 VPP or less, the resistance value R1 of the additional resistor 8 must be 100 Ω or more.

Next, the upper limit of the resistance value of the resistance to be added by imposing the condition (2) of the optimum value will be considered. In the fail bit address determination test, a chip precharge period of 1.5 μS is secured. In the original evaluation, the determination time per chip is several tens of nanoseconds, but a higher resistance value is desirable for more reliable determination of the fail bit. When the resistance is high, it becomes difficult to satisfy the condition (2). Since the additional resistance is used only in the fail bit address judgment test, the cycle time is extended during the test. When applied to an actual device, the increase in test time due to the above-mentioned test is also slight when viewed from the total test time. 1.5 μS
It is necessary to recover from the potential of 0.5 VPP to the potential of VPP during this period, and assuming that the parasitic capacitance up to the word line drive circuit of the booster power supply generation circuit is 300 pF, the resistance value R1 of the additional resistor 8 is 5 KΩ or less. It will have to be done.

From the consideration given the above conditions (1) and (2), it is understood that the resistance value R1 of the additional resistor 8 may be in the range of 100Ω to 5KΩ. If the evaluation time is desired to be shortened, the value of the resistance to be added may be set to a small value of several hundreds Ω, and if the judgment is made surely considering the variation in the resistance of the short circuit, a larger resistance may be added.

(Embodiment 2) FIG. 5 is a block diagram of a semiconductor integrated circuit in a second embodiment. As shown in FIG. 5 as compared with FIG. 1, instead of inserting an optimized resistance between the boost power supply generation circuit 2 and the boost power supply probe inspection pad 1,
The boosting power supply probe inspection pad 1 has a configuration capable of connecting an optimized second external power supply 8 having a voltage equal to or lower than the voltage of the boosting power supply.

The operation during the fail bit address judgment test will be considered below using the same example as above. Consider from the condition that the potential of the word line is sufficiently lowered when the selected word line is short-circuited with the non-selected word line. From the result of the previous example, when R1 = 0, the potential of the short-circuited word line was 0.51 VPP. Therefore, when the voltage of the second external power supply is V2, the potential of the short-circuited word line is 0.
It becomes 51V2.

Therefore, in order to reliably grasp the short circuit of the word line, the value of the voltage V2 of the second external power supply is set to V2 <0.
It can be seen that 5VPP / 0.51 is sufficient. In the present case, the resistance component is about 20Ω and the delay time is about 10 nS.
Therefore, after the address is switched from the short-circuited selected word line to the normal word line, the condition that the potential of the boosted power supply is recovered by the time measurement is started is satisfied.

[0027]

As described above, according to the present invention, the boosting power supply probe inspection pad is connected to the boosting power supply wiring through the optimized additional resistance, or the second external power supply having a voltage lower than that of the boosting power supply is connected. By connecting the connectable step-up power supply probe pad to the step-up power supply wiring, the word line potential at the time of short-circuiting the word line can be sufficiently lowered, and the short-circuit of the word line can be reliably detected during the fail bit address judgment test. It will be possible.

Further, since it is not necessary to design the boosting power supply generation circuit current supply capability particularly in consideration of a short circuit between the boosting power supply and another power supply, it is possible to suppress the power consumption of the boosting power supply generation circuit. There is no need to design a step-up power supply that requires complicated control, and the design period can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a boost power supply probe inspection pad according to a first embodiment of the present invention.

[Fig. 2] Assuming diagram of word line short circuit

FIG. 3 is a partially enlarged view of an assumed diagram of a word line short circuit.

FIG. 4 is a memory cell configuration diagram of DRAM.

FIG. 5 is a configuration diagram of a boost power supply probe inspection pad according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a conventional pad for testing a boost power supply probe of a chip.

FIG. 7 is an assumed diagram of a word line short circuit in a conventional chip.

[Explanation of symbols]

1 boosting power supply probe inspection pad 2 boosting power supply generation circuit 3 word line drive circuit 4 ground power supply (VSS) pad 7 first external power supply 8 optimized additional resistance 9 optimized second power supply 14,33 short circuit Location 15 Resistance of selected word line 16 Resistance of non-selected word line 17 Wiring resistance between step-up power supply generation circuit and word line drive circuit 18 Wiring resistance between word line drive circuit and VSS pad 19 Step-up power supply generation circuit to word line V between drive circuits
SS capacitance 34 Selected word line 35 Non-selected word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 27/108

Claims (4)

[Claims] 1. A step-up power supply generation circuit that generates a step-up power supply inside a chip, a first external power supply that supplies a voltage equivalent to the voltage of the boost power supply, and a step-up power supply probe test to which the first external power supply is connectable. Integrated pad, and the boosting power supply probe inspection pad is connected to the boosting power supply wiring via a resistor for voltage drop. 2. The resistance according to claim 1, wherein the potential of the selected word line short-circuited with the non-selected word line is sufficiently lowered in the fail bit address judgment test, and the word line from the shorted word line to the normal word line is normal. A semiconductor integrated circuit having a resistance value with which the potential of a boosted power supply recovers to a desired value before a normal word line rises when the address is selected. 3. The resistance value according to claim 1 is 100Ω to 5
A semiconductor integrated circuit having a resistance value of KΩ. 4. A step-up power supply generation circuit for generating a step-up power supply inside a chip, a second external power supply for supplying a voltage lower than the voltage of the step-up power supply, and a step-up power supply probe connectable to the second external power supply. A semiconductor integrated circuit, comprising: a test pad, wherein the boost power supply probe test pad is connected to a boost power supply wiring.