JP3222345B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a dynamic RAM.

[0002]

2. Description of the Related Art A conventional semiconductor memory device such as a dynamic RAM includes, for example, a plurality of memory cell arrays each having a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines, and a plurality of boosting circuits. It is composed of a power supply generating circuit, a plurality of word line driving circuits, and other circuits such as a control circuit. Each memory cell has a capacitor, and the capacitor is connected to a bit line via, for example, an N-channel MOS transistor (hereinafter, referred to as NMOS). Each NMOS
Are connected to word lines, respectively. Each boosted power supply generation circuit generates a boosted potential VCC + Vtn + α (where VCC is the power supply potential, Vtn is the threshold value of the NMOS, α
> 0) periodically.

When writing the information "1" to the selected memory cell having the information "0", the boosted power supply circuit selected by the address supplies the charge to the boosted node, and the potential of the boosted node becomes It is boosted. This boosted potential is applied to the word line selected by the X address,
The MOS is turned on, and charges flow into the capacitor from the bit line. Thereby, the minute potential difference ΔV between the pair of bit lines
Occurs. The potential difference ΔV is amplified by the sense latch circuit, and the level of the bit line changes to the ground potential VSS. Thereafter, the bit line receives charges from the data bus, and the level of the bit line becomes VCC indicating information of "1". Therefore, charge from the bit line flows into the storage node (storage node) between the capacitor and the NMOS in the memory cell, and the information “1” is written. Here, a leak current occurs in the word line, and the potential of the word line becomes VC.
If the voltage drops below C + Vtn, the potential VCC of the information “1” cannot be written to the storage node. Next, when reading the information “1” written in the storage node, a sufficient minute potential difference ΔV cannot be obtained, and the sense latch circuit may not operate. Alternatively, even if the operation is performed, it takes time until information is latched. Therefore, in order to recover the potential drop of the word line due to the leak current, each boosted power supply generating circuit periodically performs a boosting operation and supplies a charge to the word line.

[0004]

However, the conventional semiconductor memory device has the following problems. FIG.
FIG. 3 is a sectional view showing a memory cell. In this memory cell, a capacitor 3 is formed between a cell plate 1 serving as a reference potential and a storage node 2. The capacitor 3 is connected to the bit line BL via an NMOS that is turned on or off at the level of the word line WL input to the gate 4. That is, the source 5 of the NMOS is connected to the storage node, and the drain 6 is connected to the bit line BL. When a leak current is generated in the word line WL and the leak current is larger than the charge recovery amount from the boosted power generation circuit, the level of the word line WL falls below the potential VCC + Vtn. In this case, the charge cannot be stored in the capacitor 3 at the power supply potential VCC. Examples of the leak current include a case where the word line WL in the memory cell array is short-circuited with the cell plate 1 and the bit line BL due to a high resistance, a case where the word line WL is generated in a boosted power generation circuit to which the word line WL is connected, and the like. . When a leak current occurs, a defective portion must be replaced with a redundant circuit or a spare cell at an initial stage. However, in the related art, there is no method for detecting a voltage drop due to a minute leak current in each word line WL. No substitution was made.

[0005]

According to a first aspect of the invention, in order to solve the above problems, a semiconductor memory device, a plurality of second
One signal line and one of the plurality of second signal lines.
Switch that is turned on when the first potential is applied.
A plurality of memory cell array having a plurality of memory cells including Tsu quenching transistor, than the first potential to the first signal line selectively said memory cell arrays via each node of the plurality of nodes A plurality of potential supply means for supplying a high second potential, a plurality of switch means, and an external terminal. Here, the plurality of switch means are respectively connected to the respective nodes,
One of those nodes is selected. The external terminal is commonly connected to the plurality of switch means, and is connected to one of the nodes via one of the switch means. According to a second invention, in a semiconductor memory device, a plurality of first signal lines and a plurality of first signal lines are provided.
A first signal line connected to each one of the plurality of second signal lines;
Switching transformer that turns on when a potential is applied
A plurality of memory cell arrays each including a plurality of memory cells including a transistor, a potential supply unit for supplying a second potential higher than the first potential , a plurality of boosting units, a plurality of switch units, and an external terminal. Have. Here, the step-up means before Kifuku number, the first by boosting the potential to generate a second potential, the first selectively said each memory cell array via the respective node in the plurality of nodes It has a function of supplying the second potential to the signal line. The plurality of switch means are each connected to each of the nodes, and select one of the nodes. The external terminal is commonly connected to the plurality of switch means, and is connected to one of the nodes via one of the switch means.

According to a third aspect of the present invention, the potential supply means according to the second aspect comprises a pulse signal generating circuit for generating a pulse of a predetermined potential based on a control signal; And a booster circuit for supplying the potential of The fourth invention is the semiconductor memory device, a plurality of
One of the first signal line and the plurality of second signal lines;
Connected and turned on when the first potential is applied.
A plurality of memory cell arrays having a plurality of memory cells including switching transistors; and a first memory cell array in each memory cell array selectively via each of the plurality of nodes.
And one or more potential supply means for supplying respectively the signal line second potential higher than said first potential, and
A plurality of first switch means, a second switch means,
It has a potential varying means and an external terminal. Here, the plurality of first switch means are respectively connected to the respective nodes, and select one of the nodes. The second switch means is configured to be turned on and off by a control signal. The potential varying means has a function of generating a potential corresponding to a leak current of the first signal line based on the potential of the selected one node via the first and second switch means. ing. Further, the external terminal outputs the potential generated by the potential varying means. In a fifth aspect based on the first, second, third, or fourth aspect, the first signal line is a word line, the second signal line is a bit line, and the first potential is a power supply potential. Make up. In a sixth aspect, an external terminal according to the first, second, third or fourth aspect is provided.
It consists of a measuring pad. In a seventh aspect, the external terminal according to the fourth aspect is constituted by a data output pad.

[0007]

According to the present invention, since the semiconductor memory device is configured as described above, the selected first signal line is connected to the second potential via each node by the potential supply means or the plurality of boosting means. Is given. The node connected to the selected first signal line is connected to the external terminal by selecting the switch means, or the node connected to the selected first signal line is , The first switch means is selected, and the second switch means is turned on and off, thereby being connected to the potential varying means. When connected to an external terminal, the potential of the selected first signal line is transmitted to the external terminal. Also,
When connected to the potential varying means, the potential of the first signal line is transmitted to the potential varying means, and a potential corresponding to the potential is generated by the potential varying means and supplied to the external terminal.
By applying, for example, a probe of a characteristic evaluation device to the external terminal, a decrease in the potential of the first signal line is measured. Therefore, the above problem can be solved.

[0008]

EXAMPLES First Embodiment FIG. 1 is a schematic configuration diagram of a semiconductor memory device showing a first embodiment of the present invention. This semiconductor memory device includes a plurality of memory cell arrays 10 ₁ to 10 _M (M is an integer). Each memory cell array 10 m _(m is an integer from 1 to M) has i a first signal line of the word lines WL, respectively, the total number of word lines WL in the memory device N (N Is an integer). Each word line WL _n in FIG. 1 (n is an integer from 1 to N), the word line drive circuit 20 ₁ to 20 _N are connected. Each word line drive circuit 20 _n is a circuit for selectively driving the word line WL _n, the X decoder (not shown) output nodes XD ₁ ~
XD _N are connected respectively. Each word line drive circuit 20 _n are connected to the boost node PW ₁ ~PW _M of the plurality of boosted power supply generating circuit 30 ₁ to 30 _M provided in correspondence to each memory cell array 10 _m.
Each booster power generating circuit 30 _m is potential supplying means to the selected word line WL _n in the memory cell array 10 _m, has a configuration in which the selection signal B1～B _M is given from the outside, respectively. Each boosted power supply generation circuit 30 _m has a function of supplying a second potential selected by the selection signals B1 to B _M and boosting the power supply potential VCC as the first potential.

[0009] Each boost node PW _m, the boost node P
P-channel MOS transistors (hereinafter referred to as PMOS) 41 ₁ to 41 _m which are a plurality of switch means for selecting W _m.
Each of the 41 _M sources is connected. Each PMOS
Select signals C _{1 to} C _M specified by addresses are input to the 41 _m gates, respectively. The drain of each PMOS 41 _m is commonly connected to a measuring pad 42 which is an external terminal for a probe. The measuring pad 42 is formed of a metal thin film that is not coated with an insulating film such as a passivation film, and has a size such that the measuring pad 42 can be probed by a characteristic evaluation device such as a memory tester. Each word line drive circuit 20 _n includes an NMOS 21 and a PMOS 22 whose drains are connected to each other. The source of each NMOS 21 is ground potential VSS
To be connected, each PMOS22 source is connected to a node PW _m. Each NMOS 21 and P
The output node XD _n is connected to the gate of the MOS 22, and the drains of the NMOS 21 and the PMOS 22 are connected to the word line WL _n , respectively. Each boosted power generation circuit 30 _m includes a pulse signal generation circuit (OSC) 31 that generates a signal S31 _m that periodically swings the potential VCC and the potential VSS, and a boost circuit (CP) 32, respectively. . Each of the selection signals _Bm is input to the booster circuit 32.

FIG. 3 is a circuit diagram showing the memory cell array in FIG. It is shown to FIG. 3 the memory cell array 10 _1, for example, other memory cell array 10 _m
Has a similar configuration. The memory cell array 10 ₁ is provided with a plurality of bit line pairs BL ₁ , BL _{1 / to} BL _j , BL _{j / of a} second signal line orthogonal to the word lines WL ₁ to WLi. And bit line pair B
The memory cells 11 are connected to intersections of L ₁ , BL _{1 / to} BL _j , BL _{j /} , respectively. Each bit line BL ₁ ~B
Between the L _j or BL ₁ / to BL _{j /} and the cell plate 1, a capacitor 11a and a storage node 11b and Sui
The NMOS 11c, which is a switching transistor, is connected in series. Structure of each capacitor 11a and the storage node 11b and NMOS11c is now as shown in FIG. 2, the gate of each NMOS11c are respectively connected to the word line WL _n.

FIG. 4 is a waveform diagram showing the operating voltage in FIG. The operation of the semiconductor memory device of FIG. 1 will be described with reference to FIG. As an example, explaining the writing operation of the information "1" into one of the memory cell 11 connected to the word line WL _1. Here, it is assumed that there is no leakage current in the word line WL _1. Level selection signal B ₁ is selected by the address, the potential from the potential VSS VCC
Changes in, boosted power supply generating circuit 3 by the selection signal B ₁
0 ₁ is activated. Booster circuit 32 of the booster power generating circuit 30 in _1, since the supply charge to the boosted node PW _1, the level of the boosted node PW ₁ is increased. Here, the booster circuit 32 outputs the signal S31 from the pulse signal generation circuit 31.
Potential VCC + Vtn + α (hereinafter, referred to as “voltage”)
This potential is referred to as VPW). Therefore, the level of the boosted node PW ₁ is changed to the potential VPW.

[0012] Then, the selected output node XD ₁ of X-decoder, for example, a transition from the potential VPW to VSS, NMOS 21 in the word line drive circuit 20 ₁ is turned off, PMOS 22 is turned on. Thereby, the word line W
L ₁ is selected, the level of the word line WL ₁ is potential VS
Transition from S to the potential VPW. Each NMOS11c in the memory cell 11 connected to the word line WL ₁ is turned on, respectively. At this time, the level of each storage node 11b is set to the potential VSS according to the information held first.
Alternatively, since the potential VCC is taken, the storage node 11
b and bit lines BL ₁ -BL having a potential of VCC / 2
the charge transfer between the _j or the bit line BL 1 _/ to BL j _/
Done . Therefore, each bit line pair BL _1, BL ₁ / ~B
A minute potential difference ΔV is generated between L _j and BL _{j /} . Potential difference ΔV
Is amplified by the sense latch circuit, not shown, the bit lines BL ₁ to BL _j is changed to the potential VSS or potential VCC. After that, of the bit lines BL _{1 to} BL _j , for example, BL ₁ of the selected bit line receives the charge from the data bus and transitions to the potential VCC indicating the information “1”. Therefore, charge flows into the storage node 11b in the selected memory cell 11, and information "1" is written. For a read, the word line WL ₁ is selected in the same manner as the write. In the memory cell 11 connected to the word line WL _1, the bit line pair BL _1, BL _{1 /}
The small potential difference ΔV between 〜BL _j and BL _{j /} is amplified. The selected example of the bit lines BL ₁ potential of the bit lines BL ₁ to BL _j transits to VCC, data "1" is read out.

FIG. 5 is a waveform diagram showing the operation of the leak current compensation of FIG. If the leakage current is generated in the word line WL _n, the potential of the word line WL _n and boosted node PW _m connected thereto is reduced over time. Boosted power supply generating circuit 30 _m corresponding to the word line WL _n compensates for periodically its potential drop. That is, the pulse signal generation circuit 31 supplies the booster circuit 32 with a signal S31 that transitions between the potential VSS and the potential VCC at regular intervals. Booster circuit 3
2, receives the transition of the signal S31, boosts the boosted node PW _m to VPW. Thus, the potential of the boosted node PW _m connected thereto and a word line WL _n, periodically VP
W, and as shown in FIG. 5, the information of the potential VCC "1" is written to the selected storage node 11b.

FIG. 6 is a waveform diagram for explaining the leak current detecting operation in FIG. In the semiconductor memory device of this embodiment, since a measuring pad 42, when the leakage current can not be compensated by the boosted power supply generating circuit 30 _m occurs, replaced spare cells such detection to example defective portions thereof can do. For example, the selected word line WL
_In order to detect that a leak current has occurred in ₁ ,
The level of the selection signal C ₁ specified by the address is
The potential changes from the potential VPW to the potential VSS. As a result, the selected PMOS 41 ₁ is turned on, and the boosting node PW ₁ is connected to the measuring pad 42. The measuring needle of the characteristic evaluation device is applied to the measuring pad 42. The selection signals B ₁ and output node XD _1, the word line WL ₁ is selected,
After the potential of the word line WL ₁ rises, boost node PW ₁ (i.e., the selected word line WL _{1 n)} the voltage level and current values of, measured in the characteristic evaluation apparatus. Other word lines WL ₂ , W in the memory cell array 10 ₁
L _3, ..., detection of leakage current in WL _i is the selection of an output node _{XD 1 XD 2, XD 3,} ..., it is performed by switching the XD _i. Detection of the leak current of the word line WL _n in the memory cell array 10 _m other than the memory cell array 10 ₁ also by sequentially switching the selection of the signals B _1, C _1, is similarly performed.

As described above, according to this embodiment, a plurality of PMOSs 41 serving as switch means are provided in a semiconductor memory device.
_m and a measurement pad 42 are provided, and each boost node PW _m is connected to the measurement pad 42 based on the selection signal C _m . Further, the respective output nodes XDn potential level of the X-decoder has a configuration in which the measurement pad 42 and the word line WL _n are connected. for that reason,
Easily by using the characteristic evaluation apparatus, the potential and current for each word line WL _n can be measured respectively, the word line W
In the leakage current of the L _n can be detected which can not hold the potential VPW. Furthermore, by comparing the detection results, it is also possible to specify a portion that causes a defect. For example, boosting if the power supply leakage current in the booster circuit 32 of the generator 30 in _one occurs, the memory cell array 10 _one word line WL ₁ to WL _i detection result and each of the other memory cell array 10 ₂ to 10 _N comparing the corresponding detection result, voltage drop or current value in the detection result of the word lines WL ₁ to WL _i is larger than the other.
Further, if the leak current is generated in the word lines WL _1, by comparing the detection results with each other the word lines WL ₁ to WL _i to be boosted by the same booster power generating circuit 30 _1, the voltage drop of the word line WL ₁ or the current value becomes larger than the other, defective word line WL ₁ is detected. Therefore, it is possible to select a defect in the word line and the boosted power supply generating circuit at an initial stage, and the defective portion can be replaced with a redundant circuit or a spare cell.

Second Embodiment FIG. 7 is a schematic diagram showing the configuration of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 7, the same elements as those of FIG. 1 are denoted by the same reference numerals. The semiconductor memory device includes a plurality of memory cell array 10 ₁ to 10 _M of the same configuration as the first embodiment
When a plurality of word line driving circuits 20 ₁ to 20 _N, a PMOS 41 ₁ to 41 _M is a plurality of switch means, the external end
And a measurement pad 42 as a child, which are connected in the same manner as in the first embodiment. Further, instead of the plurality of boosted power supply generating circuit 30 ₁ to 30 _M in the first embodiment in the semiconductor memory device, potential VPW is a second potential
Power supply generating circuit 50 as potential supply means for supplying
And boosting circuits 60 _{1 to} 60 _{M as} a plurality of boosting means for boosting the potential VCC to the second potential VPW. Each booster circuit 60 _m are commonly connected to the boost node PV boosting power source generating circuit 50, boosted node PW ₁ ~PW _M of the respective booster circuit 60 _m is, the word line WL _n via the word line drive circuit 20 _n It is configured to be connected. Each booster circuit 60 _m corresponds to each of the memory cell arrays 10 _m , and has a configuration in which a select signal B _m is input to each of the booster circuits 60 _m . Each boost node PW
_A word line drive circuit 20 _n is commonly connected to _m .
The boosted power supply generating circuit 50 includes a power supply potential VCC and a ground potential V
A pulse signal generating circuit (OSC) 51 for generating a signal S51 _m that periodically amplitudes the signal SS, and a booster circuit (CPA)
52.

FIG. 8 is a waveform diagram showing the operating voltage of FIG. 7. The operation of the semiconductor memory device of FIG. 7 will be described with reference to FIG. Here, potential word line WL ₁ is selected level of the word line WL ₁ from the potential VSS VPW
Up to the transition to. First, the booster circuit 52 receives a pulse from the pulse signal generation circuit 51 and periodically supplies a charge to the booster node PV. Thereafter, when the selection signal B ₁ transitions from the potential VSS to the potential VCC, the booster circuit 60
Level of the boosted node PW ₁ of ₁ boosts the potential VCC to the potential VPW. At the same time, the boost node PV and the boost node PW ₁ conduct, and the charge is periodically supplied to the boost node PW ₁ . That is, the level of the boosted node PW ₁ is compensated to the potential VPW as in FIG. Subsequently, the output node XD ₁ is selected, and the output node XD ₁ is selected.
_{The 1} level changes from the potential VPW to the potential VSS. NMOS 21 of the word line drive circuit 20 in ₁ is turned off, PM
OS 22 is turned on. Level of the word line WL ₁ is shifted from the potential VSS to the potential VPW. The subsequent data write operation and read operation are the same as in the first embodiment.

FIG. 9 is a waveform diagram for explaining the leak current detecting operation in FIG. For example, in order to detect a leakage current in the word line WL ₁ which is selected it has occurred, as in the first embodiment shifts the level of the selection signals C ₁ from the potential VPW to the potential VSS. With this, PM
The OS 41 ₁ is turned on, the boost node PW ₁ is selected and connected to the measurement pad 42. By setting the level of the output node XD ₁ to the potential VSS, the word line WL ₁ is connected to the boost node PW ₁ , and the word line WL ₁ is connected to the measurement pad 42. Devoted to measuring needle characterization device to the measuring pad 42, the voltage level and the current value of the boost node PW ₁ after the rise of the potential of the word line WL ₁ is measured by the characterization device. Memory cell array 10 ₁
Other word lines WL _2, WL ₃ in, ..., detection of leakage current in WL _i is the selection of an output node XD ₁ X
D _2, XD _3, ..., it is performed by switching the XD _i. Leakage current detection in the word line WL _n in the memory cell array 10 _m other than the memory cell array 10 ₁ also by sequentially switching the selection of the signals B _1, C _1, is similarly performed. As described above, in the second embodiment, a plurality of switching means such as the PMOS 41
_m and a measuring pad 42 are provided, and each boosting node PW _m is connected to the measuring pad 42 based on the selection signal C _m . Therefore, as in the first embodiment, the potential and current for each word line WL _n can be easily measured. Therefore, it is possible to detect can not be holding the potential VPW of the word line WL _n,
Some have a defective portion redundancy circuit may be replaced by spare cells. Further, in the present embodiment, since the operation of each boosting circuit 60 _m is compensated by one boosting power generation circuit 50, the layout area of the semiconductor memory device can be reduced.

Third Embodiment FIG. 10 is a schematic block diagram of a semiconductor memory device according to a third embodiment of the present invention. Common elements in FIGS. 1 and 7 are denoted by the same reference numerals. ing. This semiconductor memory device includes a plurality of memory cell arrays 10 having the same configuration as that of the second embodiment.
₁ to 10 _M and a plurality of word line drive circuits 20 ₁ to 20 _N
, A plurality of PMOSs 41 _{1 to} 41 _M , one measuring pad 42 as an external terminal, and a plurality of booster circuits 60 _{1 to} 6 ₁
0 _M , which are connected in the same manner as in the second embodiment. In the storage device of the present embodiment, the boosted power generation circuit 5
A boost power supply generating circuit 70 is provided instead of 0. The boosted power supply generation circuit 70 has a pulse signal generation circuit (OSC) 71 whose operation is controlled based on the control signal SC1 to generate a pulse signal S71 having the potential VCC, and a pulse signal S
And a booster circuit (CPA) 72 for boosting the booster 71. The boost power generation circuit 70 is connected to each boost circuit 60 _m via a boost node PV. The control signal SC1 is
A signal generated by a sensor circuit (not shown),
For example, the level of the control signal SC1 when the potential VPW in the word line WL _n has decreased potential from the potential VCC VS
The transition is made to S. In the semiconductor memory device of FIG. 10, the level of the selected word line WL _n are operation between the transition from the potential VSS to the potential VPW, and subsequent write operation is the same as in the second embodiment.

FIG. 11 is a waveform diagram for explaining the leak current detecting operation in FIG. There are two methods for detecting a leak current in the semiconductor memory device, the first method and the second method. The first method is that the pulse signal generation circuit 71
While operating the a method for detecting the leakage current of each word line WL _n, the second method, in a state of stopping the operation of the pulse signal generating circuit 71, the leakage current of each word line WL _n It is a method of detecting. In the first method, a leak current is detected by the same operation as in the second embodiment. In the second method, for example, to detect a leakage current of the word line WL _1, first, the level of the control signal SC1 for example, potential since at a potential VSS to stop the control signal operated from outside the sensor circuit VCC Transition to. Control signal SC
The pulse signal generation circuit 71 is stopped by the transition of the 1 level. For example, the level of the signal S71 is maintained at the potential VCC. After the level of the selected word line WL ₁ is stood up to the potential VPW, to transition to the potential VSS of the level of the selection signals C ₁ from the potential VPW, to turn on the PMOS 41 _1. Thus, the boost node PW ₁ is connected to the measuring pad 42. The level of the output node XD ₁ potential V
By the SS, the word line WL ₁ is boosted node PW ₁
, And the word line WL ₁ is connected to the measurement pad 42. Measurements needle devoted to the measurement pad 42 characteristic evaluation apparatus, the voltage level and the current value of the boost node PW ₁ after the rise of the potential of the word line WL ₁ is measured by the characterization device. The memory cell array 10 other word lines WL ₂ in _1, WL _3, ..., detection of leakage current in WL _i is the selection of an output node XD ₁ XD _2, XD _3,
... it is carried out by switching to XD _i. Memory cell array 10
Word line WL in memory cell array 10 _m other than ₁
The detection of the leak current in _n is similarly performed by sequentially switching the selection of the signals B ₁ and C ₁ .

As described above, in the third embodiment, a plurality of PMOSs 41 serving as switch means are provided in a semiconductor memory device.
_m and a measuring pad 42 are provided, and each boost node PW _m
And the configuration of connecting respectively to the measuring pad 42 based on the selection signal C _m a. Therefore, as in the first embodiment, the potential and current for each word line WL _n can be easily measured. It can be detected which can not hold the voltage VPW in the leakage current of the word line WL _n, some have a defective portion redundancy circuit may be replaced by spare cells. Further, in this embodiment, since the operation control can be configured a pulse signal generating circuit 71 in the booster power generating circuit 70 with control signals SC1, when detecting the leakage current, the charge for the word line WL _n to be detected Supply can be eliminated. Therefore, there is no leakage current in the booster circuit 72, the detection of the leakage current of the word line WL _n, becomes easier than the second embodiment. Further, even when the non-detection of the leakage current, it is possible to stop the operation of the booster circuit 72, for example, when the word line WL _n holds the potential VPW, and the current consumption by stopping the step-up circuit 72 in the standby Can be reduced.

Fourth Embodiment FIG. 12 is a schematic diagram showing the configuration of a semiconductor memory device according to a fourth embodiment of the present invention. Common elements in FIGS. 1, 7 and 10 are denoted by the same reference numerals. Is attached. The semiconductor memory device of this embodiment, without using the measurement pad <br/> de 42 employed in the first to third embodiments, the external terminal having the semiconductor memory device
In some data output pad 90, which measures the leakage current of the word line WL _n. This semiconductor memory device includes a plurality of memory cell arrays 101 to ₁ similar to the first embodiment.
0 _M and a plurality of word line driving circuits 20 ₁ to 20 _N, a plurality of boosted power supply generating circuit 30 ₁ to 30 is a potential supplying means
_M and a plurality of PMOSs 41 _{1 as first} switch means.
To 41 _M , which are connected in the same manner as in the first embodiment. The drain of each PMOS 41 _m is connected to the node P
ADV is commonly connected to the switch 80 as the second switch means, and the output side of the switch 80 is connected to the gate of the NMOS 81 as the potential variable means. NMOS 81
Of the NMOS 8 is connected to the power supply potential VCC.
First source is connected to a data output pad 90. The switch 80 is controlled based on a control signal SC2 from the outside.
It has a function of outputting the potential of the drain of the OS 41 _m . The control signal SC2 is generated, for example, by applying a super voltage to a certain address pin. Write operation in this semiconductor memory device and
The read operation is performed in the same manner as in the first embodiment.

FIG. 13 is a waveform diagram illustrating the leak current detecting operation in FIG. For example, the word line WL ₁
When the leakage current is detected, first, a super voltage is applied to an address pin of a semiconductor memory device (not shown),
The level of the control signal SC2 is changed from the potential VSS to the potential VCC. The switch 80 is turned on by the level transition of the control signal SC2, and the drain of each PMOS 41 _m and NM
The gate of the OS 81 is connected. Then, the level of the selection signals C ₁ by the address to transition from potential VPW to potential VSS, and turn on the PMOS 41 _1. This allows
Boost node PW ₁ is connected to the gate of NMOS 81. The level of the selection signal B ₁ is set to a potential VCC transitions the level of the output node XD ₁ from the potential VCC to the potential VSS. Thus, the word line WL ₁ is connected to the gate of the NMOS 81. In this state, the data output pad 90
To the data output pad 9
A voltage level of 0 and a current value are measured. When the semiconductor memory device is a molded assembly, the data output pad 90 is measured by applying a measuring needle to the output terminal of the package to which the data output pad 90 is connected by bonding.
Voltage level measured by the measurement is in conductive position VCC when the leakage current is no position electrostatic changes the conduction state of NMOS81 if leakage current has occurred VC
Lower than C. The memory cell array 10 other word lines WL ₂ in _1, WL _3, ..., detection of leakage current in WL _i is the selection of an output node XD ₁ XD _2, XD _3,
... it is carried out by switching to XD _i. Memory cell array 10
Word line WL in memory cell array 10 _m other than ₁
The detection of the leak current in _n is similarly performed by sequentially switching the selection of the signals B ₁ and C ₁ .

[0024] As described above, in this fourth embodiment, since the configuration of pads for measuring the leakage current of each word line WL _n in the data output pad 90, similar to the first embodiment The effect can be obtained, and the leakage current to the mold assembly can be detected. For this reason, it is also possible to sort out defects after assembly. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (1) Measurement of leakage current in the first to third embodiments, but is performed by selecting the word line WL _n of one, a function of simultaneously selecting a plurality of word lines WL _n in the multi-bit products The present invention is also applicable to a semiconductor memory device having the same. That is, by switching the selection signal C _m, it is possible to perform the switching of the memory cell array 10 _m, it is possible to detect the leakage current of the word line WL _n in the memory cell array 10 having different _m. (2) The measurement pads 42 of the first to third embodiments need only be probeable, and need not be formed in a pad structure. (3) boost node PW _m and the boosting circuit 32, ... are constituted of, but is not limited to the first to fourth embodiments. For example, it may be configured such that one of the boosted node PW plurality of memory cells in _m array 10 ₁ to 10 _M is connected. (4) In the configuration of the word line drive circuit 20 _n , PM
While connected to the word line WL _n the boost node PW _m in OS 22, the word line WL _n and the boost node PW in NMOS
_m may be connected to each other. (5) Even if the selection signals B _m and C _m are the same signal, the same effects as in the first to fourth embodiments can be obtained. (6) In the fourth embodiment, a plurality of boosted power generation circuits 3
Although 0 _m is used, 1 _m as in the second and third embodiments is used.
The same effect can be obtained even if two boosted power supply generating circuits 50 and 70 are used. (7) The semiconductor memory device in which a plurality of word lines WL _n in the multi-bit product is output a plurality of data are selected at the same time, switches 80 and NMOS8 in the fourth embodiment
1 and the like may be provided, and the leakage current may be measured at the plurality of data output pads 90 ,.

[0025]

As described [Effect Invention above in detail, according to the present invention, with respect to the first signal line in the plurality of memory cell array of the semiconductor memory device, higher than the first potential second potential A potential supply means or a step-up means for respectively supplying via each node, further provided a plurality of switch means for selecting the node and an external terminal connected thereto,
Alternatively, the first and second switch means are provided with a potential variable means and an external terminal connected thereto. Therefore, the potential supplying means walking is the reduction potential of the first signal lines and the second potential by the boosting means can be detected at their external terminals. That is, a leak current can be detected. It follows, it is possible to extract the defective portion at the initial stage,
It can be obtained replacing them in the redundant circuit.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a memory cell.

FIG. 3 is a circuit diagram showing a memory cell array in FIG. 1;

FIG. 4 is a waveform chart showing operating voltages in FIG.

FIG. 5 is a waveform diagram showing an operation of leak current compensation of FIG.

FIG. 6 is a waveform diagram illustrating a leak current detection operation in FIG.

FIG. 7 is a schematic configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a waveform chart showing operating voltages in FIG. 7;

9 is a waveform diagram illustrating a leak current detection operation in FIG.

FIG. 10 is a schematic configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 11 is a waveform diagram illustrating a leak current detection operation in FIG.

FIG. 12 is a schematic configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 13 is a waveform diagram illustrating a leak current detection operation in FIG.

[Explanation of symbols]

10 ₁ ~ 10 _M memory cell array 20 ₁ to 20 _N word line drive circuit 30 ₁ ~30 _M, 50,70 boosted power supply generating circuit 31, 51, 71 the pulse signal generating circuit 32,52,7 second boost circuit 41 _{1-41 M} PMOS 42 measuring pad 80 switch 81 NMOS 90 data output pad WL ₁ to WL _N word line PW ₁ ~PW _M, PV boost node

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/401-11/4099 G11C 29/00

Claims (7)

(57) [Claims] 1. A plurality of first signal lines and a plurality of second signal lines.
Connected to each one of the signal lines and provided with a first potential
Including the switching transistor
A plurality of memory cell array having a plurality of Moriseru, second potential higher than said first potential to the first signal line in selective each memory cell array through each node of the plurality of nodes A plurality of potential supply means for respectively supplying: a plurality of potential supply means; a plurality of switch means each connected to each of the nodes; and a plurality of switch means for selecting one of the nodes; Connected to one of said nodes via one of
A semiconductor memory device, comprising: an external terminal. 2. A plurality of first signal lines and a plurality of second signal lines.
Connected to each one of the signal lines and provided with a first potential
Including the switching transistor
A plurality of memory cell array having a plurality of Moriseru, said a potential supply means for supplying a second potential higher than the first potential, to generate a second potential by boosting the first potential, a plurality of nodes A plurality of boosting means for selectively supplying the second potential to the first signal line in each of the memory cell arrays via each of the nodes in A plurality of switch means for selecting one of the switch means; a common connection to the plurality of switch means; and a connection to one of the nodes via one of the switch means.
A semiconductor memory device, comprising: an external terminal. 3. The semiconductor memory device according to claim 2, wherein said potential supply means generates a pulse of a predetermined potential based on a control signal, and said pulse supply circuit is boosted in response to a transition of said pulse. And a booster circuit for supplying a second potential. 4. A plurality of first signal lines and a plurality of second signal lines.
Connected to each one of the signal lines and provided with a first potential
Including the switching transistor
A plurality of memory cell array having a plurality of Moriseru plurality said of each node in the node selectively through the relative first signal line in each memory cell array first and second potential higher than the potential, respectively One or a plurality of potential supply means for supplying, a plurality of first switch means respectively connected to the respective nodes and selecting one of the nodes, a second switch which is turned on and off by a control signal Switch means; and a potential variable means for generating a potential corresponding to a leak current of the first signal line based on a potential of the selected one node via the first and second switch means. An external terminal for outputting a potential generated by the potential varying means. 5. The semiconductor memory device according to claim 1, wherein said first signal line is a word line, said second signal line is a bit line, and said first potential is a power supply potential. A semiconductor storage device characterized by comprising: 6. The semiconductor memory device according to claim 1, wherein said external terminal is constituted by a measuring pad. 7. The semiconductor memory device according to claim 4, wherein said external terminal is constituted by a data output pad.