JPH06149651A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the current consumption of a microcomputer having a memory circuit to which a reading circuit following steady current consumption is added in order to execute a high-speed reading. CONSTITUTION:A CPU 10, a ROM 40, a RAM 50, an operation control circuit 80, and a PORT 70 are mutually connected through an address bus 60 and a data bus 70 based upon a reference address outputted from a CPU 10a. At the time of inputting a mode switching signal from a mode terminal 20, the circuit 80a specified the permission/inhibition of instruction fetching operation from the incorporated ROM 40 and respectively controls the reading of the ROM 40 and the RAM 50 by using AMPOFF signals 81, 82 to the ROM 40. Then a port switching signal 83 is outputted to a PORT 30 so as to selectively switch an I/O port function and a function for accessing an external memory. Thereby the operation of the reading circuit is stopped during the period of no access to the incorporated memory so as to reduce current consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a built-in memory such as an instruction ROM, and more particularly to a microcomputer having a function of suppressing current consumption in the built-in memory.

[0002]

2. Description of the Related Art Recently, microcomputers (hereinafter referred to as "microcomputers") are widely used for machine control, data communication control, etc., because of their small size and multi-functionality. Further, there is also a high demand for the processing (command execution) speed of the microcomputer itself, and a higher speed operation is required. On the other hand, in order to avoid the difficulty of designing the interface part associated with high-speed operation or high cost due to the use of high-speed memory to follow the microcomputer in peripheral devices such as memory that were conventionally connected externally with the microcomputer. In addition, a single-chip microcomputer incorporating such peripheral devices on the same chip has been widely demanded.

Further, as the internal structure of the microcomputer, in order to perform a high-speed read operation from a built-in memory, for example, read data from the cell portion is based on a reference voltage set near the threshold value of a transistor. Higher speed is supported by adopting a method that enables high-speed reading by sensing the minute amplitude of the (digit line).

A conventional example will be described with reference to the drawings.

FIG. 7 is a block diagram showing the configuration of a conventional microcomputer 1c.

The microcomputer 1c is a central processing unit (hereinafter referred to as C
PU) 10 and operation mode designation (hereinafter, MODE)
Terminal), a port having an extended function when an external memory is connected (hereinafter simply referred to as PORT) 30, an instruction code and immediate data, in addition to the functions of a normal input / output (I / O) port. ROM 40 that stores
A data RAM 50, an address bus 60 and a data bus 70 for the CPU 10 to access devices such as internal and external memories or ports, control of instruction execution and stop operation of the microcomputer 1c, and expansion operation when an external memory is connected. An operation control circuit (hereinafter, referred to as ACON) 80c for performing the operation is provided.

Next, the configuration of each part of the microcomputer 1c will be described.

The address bus 60 is connected to the CPU 10 and ACON.
The reference address is output from the CPU 10 by connecting the memory and port of the 80c, the ROM 40, the RAM 50, and the PORT 30.

The data bus 70 comprises a CPU 10 and an ACON 8
0c, the ROM 40, the RAM 50, the memory and the port of the PORT 30 are connected, and the R / W data is exchanged with the CPU 10.

The ACON 80c is a CPU as shown in FIG.
10 can write to and read from the data bus 70. Two 1-bit execution designation registers (hereinafter referred to as STB
A C register 85, a port function designation register (hereinafter referred to as an MM register) 86, and an OR gate 87 are provided.

The MODE terminal 20 is a terminal for designating the operation mode of the microcomputer 1c, and permits or prohibits the instruction fetch operation from the built-in ROM 40.

The PORT 30 is a multiplexed port to which an address bus and a data bus for accessing an external memory and an RD / WR strobe are added in addition to the function of a normal I / O port. Furthermore, PORT
The 30 can selectively switch between two operations of an I / O port function and a function of accessing an external memory by a PORT operation switching signal 83 output from the ACON 80c.

The ROM 40 and the RAM 50 are memories capable of reading data from the cell portion at high speed. For example, the ROM 40 and the RAM 50 sense a signal having an extremely small amplitude on a digit line as shown in FIG.
A sense amplifier that generates read data is used, and a stop signal AMPOFF that stops the operation of the sense amplifier unit is input.

Normally, since the input signal AMPOFF is at "0" level, the output levels of the NOR gates 91 and 93 are "1", and the route of P ₆ → N ₇ → N ₈ → N ₉ and
P ₄ → N ₆ route, P ₂ → N ₄ route, P ₁ →
A normal current flows along the route of N ₁ → N ₂ .

Next, the operation of the microcomputer 1c will be described.

First, when a "0" level is input to the MODE terminal 20, the operation mode is set to an internal ROM access mode (hereinafter referred to as a sigle chip mode; SC mode) for fetching an instruction from the ROM 40 included in the microcomputer 1c. To be done.

At this time, the microcomputer 1c fetches an instruction from the ROM 40, reads or writes data from the RAM 50, accesses the PORT 30 as an I / O port, and outputs or inputs predetermined data according to the contents of the instruction fetch. Execute instructions.

Next, in the above state, when the CPU 10 executes the instruction, the "1" level is written from the data bus 70 to the 1-bit register MM86 included in the ACON 80c, and the output signal 83 of the OR gate 87 is "1". Then, the PORT 30 switches from the normal function as an I / O port to the function of outputting an address / data bus for referring to an external memory and a strobe of RD / WR.

That is, the port terminal group 31 has an address
Data bus ADn (n is an integer indicating the bus width such as 8 or 16 and is not limited to a specific bus width),
Port terminal 32 is RD inverted, port terminal 33 is WR inverted
Functions as a signal input / output terminal or output terminal.

The operation in this case is an external memory reference mode (hereinafter referred to as an external expansion mode) in which the CPU 10 performs instruction fetch and data R / W to an external memory externally connected to the microcomputer 1c, A reference address is input / output to / from the address bus 60 and reference data is input / output via the data bus 70 from the port terminal group 31 and the port terminals 32 and 33, respectively.

Next, when the "1" level is input to the MODE terminal 20, the output signal 83 of the OR gate 87 becomes the "1" level, and the PORT 30 functions as an ordinary I / O port, so that the external memory is operated. To the function of outputting the address / data bus for referencing and the strobe of RD / WR.

That is, the port terminal group 31 has an address
The data bus ADn, the port terminal 32 always function as an RD, and the port 33 always functions as an input / output terminal or an output terminal of an inverted WR signal. At this time, no instruction is fetched from the built-in ROM 40, and the ROM-less mode in which only the external memory is always accessed is operated.

The above operation is summarized as a list of operation modes of the microcomputer 1c shown in FIG.

Next, the operation when the instruction execution of the microcomputer 1c is stopped will be described.

1-bit register ST of ACON 80c
The BC 85 is a register that defines the instruction execution and stop operation of the microcomputer 1c, and is normally "0". But the CPU
When the "1" level is set by the instruction execution operation of the CPU 10, the microcomputer 1c including the instruction fetch operation of the CPU 10
All the instruction execution operations of (3) are stopped, and the so-called standby state is maintained in which the stopped state is maintained until the stop release is designated by the stop release factor.

The output signals (hereinafter referred to as AMPOFF) 81 and 82 of the STBC register 85 are R respectively.
Input to OM40 and RAM50, ROM40, R
In AM50, when AMPOFF31 and 32 are input, the operation of the data reading circuit is stopped.

At this time, the microcomputer 1c goes into the standby state, so that not only the instruction execution operation is stopped but also the supply of the internal clock is stopped, the through current at the time of switching the transistor is eliminated, and the ROM 40, R
By cutting off the current that was constantly flowing in the data reading circuit of AM50, the consumption of current (power) can be suppressed to an extremely low level.

[0028]

In the conventional microcomputer,
In a read circuit of a built-in memory (ROM, RAM), in order to perform high-speed data reading, a read circuit such as a sense amplifier which enables high-speed reading by increasing the sense sensitivity of a digit line by flowing a steady current is used. The current is always consumed regardless of the operating frequency of the microcomputer and the content of the instruction.

Further, in the case of a complementary MOS semiconductor device, basically, only a through current at the time of switching of a transistor flows, and it is considered that most of the total current consumption (power) as a microcomputer is due to this steady current. Become.

Therefore, in such a situation, conventionally, the operation of the data read circuit of the ROM and RAM is stopped only in the standby mode. Therefore, only the external memory is referred to and the built-in ROM is not referred to in the ROMless mode. , Or for the built-in ROM in the extended mode where the access to the built-in ROM is not always performed, the current is consumed even during the period when the read operation is not necessary because the above reading circuit is always operating regardless of the access. It has the drawback that it is done.

An object of the present invention is to efficiently reduce the current consumption of a microcomputer incorporating a memory to which a reading circuit through which a constant current flows for high-speed reading is added by eliminating the above-mentioned drawbacks. With the goal.

[0032]

A feature of the present invention is that a CPU
And an internal ROM and an internal RAM provided with a reading circuit that enables high-speed reading by constantly flowing a current,
A MODE terminal for designating permission and prohibition of an instruction fetch operation from the internal ROM, a port capable of selectively switching a function of a general-purpose input / output port and an interface function with an externally arranged memory, and the CPU An STBC register that specifies execution and stop of execution of an instruction by
An SC mode that is provided with an MM register that specifies a function of the port, and is set by a first voltage level of the MODE terminal and a first output level of the MM register;
An external expansion mode set by the first voltage level of the MODE terminal and a second output level of the MM register; a ROMless mode set by the second voltage level of the MODE terminal; In a microcomputer for instructing a read operation corresponding to a standby mode set by a state in which the STBC register is designated, in any of the SC mode, the external extension mode, the ROMless mode and the standby mode, While the internal ROM and the internal RAM are not referenced by the CPU, the internal ROM and the RAM
It is provided with means for stopping the operation of the reading circuit. Further, the means decodes a reference address of the CPU input via an address bus, and when the reference address of the decoding result is within the address range of the internal RAM, it is low level, and when it is out of the range, it is high level. A first output signal and a decoder for outputting a second output signal which is at a low level when the reference address of the decoding result is within the address range of the internal ROM and is at a high level when out of the range; A STBC register, and stops the operation of the read circuit of the internal RAM by the logical sum output signal of the first output signal of the decoder and the output signal of the STBC register, and outputs the second output signal of the decoder. And an output signal of the STBC register and a logical sum output signal of the second voltage level to read the internal ROM. It can be configured to stop the operation of the circuit out.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The microcomputer of the present invention is to determine the period during which the internal memory is referred to by the CPU and stop the operation of the read circuit of the internal memory when the internal memory is not accessed.

A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the microcomputer 1a described in the first embodiment.
2 is a block diagram showing the configuration of the operation control circuit 8 for the microcomputer 1c described in the conventional example.
In this example, the operation control circuit 80a is only replaced with 0c, and other configurations and operations are the same as those described in the conventional example, so only the changes will be described.

FIG. 2 is a block diagram of an operation control circuit (hereinafter referred to as ACON) 80a in the microcomputer 1a, which is different from the ACON 80c described in the conventional example in the address bus 70.
An address decoding circuit (hereinafter, referred to as DEC) 84 for decoding the signal and an OR gate 881 are newly added.

The DEC 84 decodes the reference address of the CPU 10 input via the address bus 60. As a result of the decoding, the reference address is the internal ROM 4
When the address range is 0, the decoding result 841
"0" level is output as.

If the reference address is outside the address range of the built-in ROM 40, a "1" level is output to the OR gate 881 as the decoding result 841. The output signal of the OR gate 881 is the AMPOFF signal 81 for stopping the operation of the read circuit of the ROM 40.

Next, the operation of the microcomputer 1a will be described with reference to FIG. In addition, the MODE terminal 20 of the microcomputer 1a,
The operation mode by the MM register 86 and the STBC register 85 is the same as described in the conventional example.

First, when the "0" level is input to the MODE terminal 20, the SC mode in which the instruction is fetched from the built-in ROM 40 is set, and the microcomputer 1a is in the ROM 40.
From the RAM 50 according to the contents
Command execution such as read / write of data from or to I / O port to the PORT 30.

At this time, when the signal level for designating the operation mode applied to the MODE terminal 20 is "0", AMPOFF is set.
Since the output level of the STBC register 85 of 81 is "0", the output level of the AMPOFF 81 is "0" when the reference address is within the address range of the internal ROM 40 by the DEC 84 of the AMPOFF 81. When the address is out of the range of the ROM 40, the AMPOFF 81 outputs "1" level.

Therefore, when referring to the ROM 40, the AMP
The output level of OFF81 is "0", so ROM40
Read circuit operates, and in other cases, the read circuit stops operating.

Next, in the above-mentioned state, the MM of the ACON 80a from the data bus 70 is operated by the instruction execution operation of the CPU 10.
When the “1” level is written in the register 86, the output signal 83 of the OR gate 87 becomes the “1” level. As a result, the PORT 30 is switched to the external expansion function for referring to the external memory, and the microcomputer 1a enters the expansion mode.

At this time, the AMPOFF 81 changes based on the reference address as in the SC mode, and RO
It controls the operation of the read circuit of M40.

Next, when the signal level for designating the operation mode applied to the MODE terminal 20 is "1" level, OR
The output signal 83 of the gate 87 becomes "1" level, and PO
The RT 30 is switched to the extended function as in the extended mode.

At this time, no instruction is fetched from the built-in ROM 40, and only the external memory is accessed at all times.
It operates as OM-less mode.

The AMPOFF 81 has a MODE terminal 2
Since the level applied to 0 is always the "1" level, the read circuit of the ROM 40 stops operating.

Next, the operation for stopping the instruction execution of the microcomputer 1a is performed by the S of the ACON 80 as described in the conventional example.
The TBC register 85 is set to the "1" level from the data bus 70 to shift to the standby state.

The output signal of the STBC register 85 is RA
A signal for stopping the operation of the read circuit of M50 (hereinafter,
It is input to the RAM 50 as 82 (referred to as AMPOFF).

In the RAM 50, the operation of the data reading circuit is stopped when the AMPOFF 82 is input, as in the case of the ROM 40.

As described above, the microcomputer 1a is
If the internal RAM 40 is not accessed in M-less mode,
And built-in ROM 40 in SC mode or extended mode
When accessing other than the above, by stopping the operation of the read circuit of the built-in ROM 40, it is possible to reduce the current consumption during an unnecessary period.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows the microcomputer 1b described in the second embodiment.
2 is a block diagram showing the configuration of the first embodiment, and the entire configuration and operation are different from the microcomputer 1a described in the first embodiment only in that the operation control circuit 80a is replaced with the operation control circuit 80b in this example. Since other configurations and operations are the same as those described in the conventional example, only the changes will be described.

FIG. 5 shows the operation control circuit A in the microcomputer 1b.
FIG. 7 is a block diagram of the CON 80b, in which the RAM 50 by the DEC 84 is added to the ACON 80a described in the first embodiment.
The difference is that a result signal 842 obtained by decoding the address range of 1 and an OR gate 882 are newly added.

The address decoding result signal 842 and the output signal 82 of the STBC register 85 are input to the OR gate 882, and the output thereof is input to the RAM 50 as a signal (hereinafter referred to as AMPOFF) 82 for stopping the operation of the reading circuit of the RAM 50. Has been done.

The microcomputer 1b described in the second embodiment is different from the microcomputer 1a described in the first embodiment in that it has a built-in RAM 5
When the RAM 50 is not referred to by decoding the address range of 0 by the address bus 60, the RAM 5
The operation of the 0 read circuit can be stopped. FIG. 6 shows an operation at the time of referring to the built-in ROM 40, RAM 50, external memory, and the like.

As a result, not only the ROM 40 but also the RAM
If 50 is not being accessed, the operation of each read circuit is stopped to further reduce the current consumption.

In addition, in the second embodiment, a built-in ROM
Although the RAM and the RAM are mentioned above, the current consumption can be suppressed to a necessary minimum throughout the microcomputer 1b by performing the same control for other peripheral functions.

[0059]

According to the microcomputer of the present invention described above, the built-in memory is accessed by a microcomputer using a high-speed read circuit by causing a current to constantly flow in the memory built in the conventional microcomputer. By determining the period from the reference address output from the CPU, the setting value of the operation mode designation pin (MODE) and the port function designation register (MM), (1) Only the externally connected memory without accessing the built-in ROM When accessing, the operation of the read circuit portion of the built-in ROM is always stopped to reduce unnecessary current consumption in the read circuit. (2) When accessing the built-in ROM, the read circuit of the ROM is operated only during the access period to the built-in ROM, and the operation of the read circuit is stopped when there is no access to the ROM, thereby requiring current consumption in the read circuit. It can be efficiently suppressed to the minimum. (3) In the control described in the above item (2), if the same control is performed for other peripheral functions including the built-in RAM, it is possible to efficiently reduce the current consumption over the entire microcomputer.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer 1a according to a first embodiment.

FIG. 2 is a block diagram of an operation control circuit 80a in the first embodiment.

FIG. 3 is a timing chart illustrating the operation of the first embodiment.

FIG. 4 is a block diagram of a microcomputer 1b according to a second embodiment.

FIG. 5 is a block diagram of an operation control circuit 80b in the second embodiment.

FIG. 6 is a timing chart illustrating the operation of the second embodiment.

FIG. 7 is a block diagram of a microcomputer 1c in a conventional example.

FIG. 8 is a block diagram of an operation control circuit 80c in a conventional example.

FIG. 9 is a diagram showing an example of a high-speed read circuit in a conventional ROM 40, RAM 50.

FIG. 10 is a diagram showing a list of operation modes of a microcomputer 1c in a conventional example.

[Explanation of symbols]

 1a, 1b, 1c Microcomputer 10 CPU 20 Operation mode designation terminal (MODE) 30 Port with extended function (PORT) 31 Port terminal group with extended function 32, 33 Port terminal with extended function 40 ROM 50 RAM 60 Address bus 70 Data bus 80a , 80b, 80c Operation control circuit (ACON) 84 Address decode circuit 85 Execution designation register (STBC) 86 Port function designation register (MM) 87, 881, 882 OR gate

Claims (2)

[Claims] 1. An internal ROM and an internal RAM equipped with a central processing unit, a read circuit that enables high-speed reading by causing a constant current to flow, and designation of permission and prohibition of an instruction fetch operation from the internal ROM. An operation mode designating terminal, a port capable of selectively switching between the function of a general-purpose I / O port and the interface function of an externally arranged memory, and designation of execution and suspension of execution of instructions by the central processing unit. ROM access provided with an execution designation register and a port function designation register for designating the function of the port, and set by the first voltage level of the operation mode designation terminal and the first output level of the port function designation register The mode, the first voltage level of the operation mode designating terminal and the second output level of the port function designating register. Corresponding to the external memory reference mode set by the above, the ROMless mode set by the second voltage level of the operation mode designating terminal, and the standby mode set by the state where the execution designating register is designated. In the microcomputer for instructing the read operation by the central device, the internal ROM and the internal RAM are not referred to in any of the ROM access mode, the external memory reference mode, the ROMless mode, and the standby mode. A microcomputer provided with means for stopping the operation of the read circuit of the internal ROM and the RAM during the period. 2. The means decodes a reference address of the central processing unit input via an address bus, and if the reference address of the decoding result is within the address range of the internal RAM, it becomes low level and out of the range. If so, a first output signal that becomes a high level, and a second output signal that becomes a low level if the reference address of the decoding result is within the address range of the internal ROM and a high level if it is out of the range. A decoder for outputting and an execution designating register, and stop the operation of the read circuit of the internal RAM by an OR output signal of the first output signal of the decoder and the output signal of the execution designating register, The logical sum output signal of the second output signal of the decoder, the output signal of the execution designating register and the second voltage level causes The microcomputer according to claim 1, wherein the microcomputer is configured to stop the operation of the read circuit of the internal ROM.