JPH06148661A - Production of substrate for display device - Google Patents
Production of substrate for display deviceInfo
- Publication number
- JPH06148661A JPH06148661A JP30195792A JP30195792A JPH06148661A JP H06148661 A JPH06148661 A JP H06148661A JP 30195792 A JP30195792 A JP 30195792A JP 30195792 A JP30195792 A JP 30195792A JP H06148661 A JPH06148661 A JP H06148661A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- plating
- transparent electrode
- electric field
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、液晶表示装置等、表示
装置用基板の製法に関する。特に電極の抵抗を一段と下
げることに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a display device substrate such as a liquid crystal display device. In particular, it relates to further lowering the resistance of the electrodes.
【0002】[0002]
【従来の技術】液晶表示装置等、表示装置は、マン・マ
シーン・インターフェースとしては、是非必要となる技
術である。特に、最近、コンピューター端末等におい
て、ダウン・サイジングの意味からも、液晶表示装置は
必須となってきた。2. Description of the Related Art A display device such as a liquid crystal display device is an essential technology for a man-machine interface. Particularly, recently, in computer terminals and the like, liquid crystal display devices have become indispensable also from the viewpoint of downsizing.
【0003】電気抵抗値、生産時の制御性、膜の均一
性、光の透過率、微細加工性等の点から、産業的には、
圧倒的に、インジウム−錫の酸化物(いわゆるITO)
が使われている。From the viewpoint of electric resistance, controllability during production, film uniformity, light transmittance, fine workability, etc., industrially,
Overwhelmingly, indium-tin oxide (so-called ITO)
Is used.
【0004】この技術内容は、「薄膜ハンドブック」、
日本学術振興会第131委員会 編、オーム社刊に詳し
い。The technical contents are "Thin Film Handbook",
Detailed information on Ohmsha, edited by the 131st Committee of Japan Society for the Promotion of Science.
【0005】[0005]
【発明が解決しようとする課題】最近、コンピューター
端末等に使われる液晶表示装置において、高品位表示の
要求が現実のものとなってきた。これらの液晶表示装置
においては、STN等、単純モードの液晶表示装置が主
に使われている。これらの液晶表示装置には、表示にお
いて、クロストーク現象等、表示の質の低下が見られる
が、現状では仕方なく使われている。Recently, in liquid crystal display devices used for computer terminals and the like, the demand for high-quality display has become a reality. In these liquid crystal display devices, simple mode liquid crystal display devices such as STN are mainly used. In these liquid crystal display devices, the display quality is deteriorated due to a crosstalk phenomenon or the like in the display, but it is unavoidably used at present.
【0006】この現象は、透明電極(ITO)の電気抵
抗値が十分、低くなく、従って、CR時定数が大きいこ
とに起因する。現在の技術では、ITOの比電気抵抗率
は、2×10ー4Ωcm程度までしか、達成されていな
い。ちなみに、金や銅、アルミニウムの比抵抗率は、2
×10-6Ωcm程度である。This phenomenon is caused by the fact that the electric resistance value of the transparent electrode (ITO) is not sufficiently low and therefore the CR time constant is large. With the current technology, the specific electric resistivity of ITO has been achieved only up to about 2 × 10 −4 Ωcm. By the way, the resistivity of gold, copper, and aluminum is 2
It is about 10 −6 Ωcm.
【0007】ところが、金や銅、アルミニウムをITO
に接して配線された(いわゆる補助電極)基板の開発が
なされているが、この場合、ITOや基板への接着強度
の欠如が問題となる。However, gold, copper and aluminum are replaced with ITO.
A substrate in which wiring is formed in contact with the substrate (so-called auxiliary electrode) has been developed, but in this case, the lack of adhesion strength to ITO or the substrate becomes a problem.
【0008】また、この補助電極形成のコストは出来る
だけ、低減させることが要求される。例えば、フォトリ
ソグラフィー法及び蒸着プロセスを用いた方法は、確実
なものであるが、コストが高く、とても一般に使われる
方法とは考えられない。Further, it is required to reduce the cost of forming the auxiliary electrode as much as possible. For example, the method using the photolithography method and the vapor deposition process is reliable, but the cost is high, and it cannot be considered as a method generally used.
【0009】また、この問題は、強誘電性液晶表示装置
においてもあてはまる。This problem also applies to the ferroelectric liquid crystal display device.
【0010】[0010]
【課題を解決するための手段】本発明は前述のような課
題を解決するために、基板の主面全面に亘る透明電極の
上に、所望の状態にパターン化されたレジスト膜を形成
し、透明電極の腐食液で微細加工をし、洗浄し、次に前
記レジスト膜を縮まらせ、透明電極の露出部をオゾンま
たは酸素プラズマで清浄化し、透明電極の露出部にイン
ジウム電界鍍金を施し、更に、この上に、銅単層電界鍍
金または、金単層電界鍍金または、銅電界鍍金と金の電
界または無電界鍍金の2層鍍金をこの順に施し、洗浄、
乾燥させ、レジスト膜を除去、洗浄、乾燥させ、この
後、所望の温度プロフィールで、所望の最高温度まで熱
処理するような表示装置用基板の製法を提供するもので
ある。In order to solve the above-mentioned problems, the present invention forms a resist film patterned in a desired state on a transparent electrode over the entire main surface of a substrate, Fine processing with a corrosive liquid for the transparent electrode, washing, then shrinking the resist film, cleaning the exposed part of the transparent electrode with ozone or oxygen plasma, indium electroplating on the exposed part of the transparent electrode, , A copper single-layer electric field plating, a gold single-layer electric field plating, or a two-layer plating of copper electric field plating and gold electric field or electroless plating, in this order, and washing,
The present invention provides a method of manufacturing a substrate for a display device in which the resist film is dried, the resist film is removed, washed, and dried, and then heat-treated at a desired temperature profile to a desired maximum temperature.
【0011】本発明はさらに、基板の主面全面に亘る透
明電極の上に、所望の状態にパターン化されたレジスト
膜を形成し、透明電極の腐食液で微細加工をし、洗浄
し、次に前記レジスト膜を縮まらせ、透明電極の露出部
をオゾンまたは酸素プラズマで清浄化し、透明電極の露
出部にニッケル電界または無電界鍍金を施し、更に、こ
の上に、銅単層電界鍍金または、金単層電界または無電
界鍍金または、銅電界鍍金と金の電界または無電界鍍金
の2層鍍金をこの順に施し、洗浄、乾燥させ、レジスト
膜を除去、洗浄、乾燥させ、この後、熱処理するような
表示装置用基板の製法をも明かにする。Further, according to the present invention, a resist film patterned in a desired state is formed on the transparent electrode over the entire main surface of the substrate, finely processed with a corrosive liquid for the transparent electrode, and washed. Shrink the resist film to, the exposed portion of the transparent electrode is cleaned with ozone or oxygen plasma, nickel electric field or electroless plating is applied to the exposed portion of the transparent electrode, further, copper single-layer electric field plating or, Gold single-layer electric field or electroless plating or two-layer plating of copper electric field plating and gold electric field or electroless plating is applied in this order, washed and dried, and the resist film is removed, washed and dried, and then heat treated. A method of manufacturing such a substrate for a display device will be clarified.
【0012】なお、パターン化されたレジスト膜を、熱
的効果により縮まらせるか、オゾンまたは酸素プラズマ
を照射することにより、前記レジスト膜を縮まらせるの
が、望ましい。It is desirable that the patterned resist film is shrunk by a thermal effect, or the resist film is shrunk by irradiating ozone or oxygen plasma.
【0013】[0013]
【作用】まず、基板への接着力、具体的には、ITO並
びに、ガラス質基板表面への接着力は、インジウムない
し、インジウム合金が付着力が良好である。この現象
は、ガラス用ハンダ等で実証されている。また、特に銅
や金はその貴金属性の故に付着力は極めて乏しい。IT
O並びに、ガラス質基板表面への接着力の強い金属とし
ては、他に、ニッケルがある。クロムもそうであるが、
鍍金技術の困難さは尋常でない(クロム鍍金技術は、勿
論、あるが)。First, indium or an indium alloy has a good adhesive force to the substrate, specifically, ITO and the adhesive force to the glass substrate surface. This phenomenon has been verified with glass solder and the like. Also, copper and gold, in particular, have extremely poor adhesion due to their noble metal properties. IT
Nickel is another example of O and a metal having a strong adhesion to the surface of the glass substrate. As is chrome,
The difficulty of plating technology is unusual (though of course there is chrome plating technology).
【0014】また、インジウムは、水溶液を使った、電
気鍍金で可能である。インジウムを析出させるため、物
理的析出法を使う必要がない。物理的析出法は、蒸着機
やスパッター装置等、高価な設備が必要である。もちろ
ん、インジウム金属は、蒸着等、物理的手法でも析出可
能であるが。ニッケルは、もっとも鍍金し易い金属であ
り、電気鍍金や、ITO上への選択鍍金も可能である。Indium can be electroplated using an aqueous solution. Since indium is deposited, it is not necessary to use a physical deposition method. The physical precipitation method requires expensive equipment such as a vapor deposition machine and a sputtering apparatus. Of course, indium metal can be deposited by a physical method such as vapor deposition. Nickel is the metal that is most easily plated, and electroplating and selective plating on ITO are also possible.
【0015】電気抵抗は、銅、や金を使用することによ
り、最も理想的に下がる。また、プロセス的に、ITO
の微細加工(これは、従来なされるプロセスである)
に、若干のプロセスを追加することにより、より低抵抗
の電極を得るのが望ましい。これが、以下の提案であ
る。すなわち、基板の主面全面に亘るITOの上に、所
望の状態にパターン化されたレジスト膜を形成し、IT
Oの腐食液で微細加工をし、洗浄し、前記レジスト膜を
シュリンクさせ、ITOの露出部を招来させ、次にこの
ITOの露出部にインジウム鍍金ないしニッケル鍍金を
施し、更に、この上に、銅鍍金ないし、金鍍金をなし、
洗浄、乾燥させ、レジスト膜を除去、洗浄、乾燥させ、
この後、所望の温度プロフィールで、熱処理することで
ある。なお、銅鍍金の場合、耐腐食性の意味から、鍍金
された銅の表面に無電界金鍍金を行うのも、望ましい。
最後の熱処理は、基板への付着力を高めること、さら
に、インジウム鍍金を行った場合は、銅や金とインジウ
ム合金を形成させ、耐熱性を向上させることもねらいで
ある。The electric resistance is most ideally lowered by using copper or gold. Also, in terms of process, ITO
Microfabrication (this is a conventional process)
It is desirable to obtain a lower resistance electrode by adding a few processes to the above. This is the following proposal. That is, a resist film patterned in a desired state is formed on the ITO over the entire main surface of the substrate, and the IT
Fine processing with an O corrosive liquid, washing, shrinking the resist film to bring exposed areas of ITO, and then applying indium plating or nickel plating to the exposed areas of ITO, and further, No copper plating or gold plating,
Wash, dry, remove resist film, wash, dry,
This is followed by heat treatment with a desired temperature profile. In the case of copper plating, it is also desirable to perform electroless gold plating on the surface of plated copper from the viewpoint of corrosion resistance.
The final heat treatment is aimed at increasing the adhesion to the substrate and, when indium plating is performed, forming indium alloy with copper or gold to improve heat resistance.
【0016】これでは、ITO電極の検査も一度で済
む。最後の熱処理は、下地金属インジウムと銅、あるい
は金の一部の合金反応を進めるためと、基板と前記合金
との接着力を向上させる意味もある。下地金属がニッケ
ルの場合も、これで接着力の向上が図れる。With this, the inspection of the ITO electrode can be performed only once. The final heat treatment also has the meaning of promoting the alloy reaction of a part of the underlying metal indium and copper or gold, and improving the adhesive force between the substrate and the alloy. Even when the base metal is nickel, this can improve the adhesive strength.
【0017】なお、前記積層導体において、インジウム
ないしインジウム合金ないしニッケルの層は基板への付
着力にのみ寄与するものであり、電気抵抗を下げるには
卓効はない。従って、付着力さえ、満足出来れば、銅や
金からなる層の体積は、前記層に比べて、大であるべき
である。In the above-mentioned laminated conductor, the layer of indium, indium alloy or nickel contributes only to the adhesion to the substrate and is not effective for reducing the electric resistance. Therefore, the volume of the layer made of copper or gold should be larger than that of the layer if the adhesion is satisfactory.
【0018】[0018]
【実施例】以下、本発明の実施例を説明する。ここで
は、単純型のマトリクス表示装置について述べる。しか
し、この実施例は基本的には、EL表示装置等にもあて
はまるものである。EXAMPLES Examples of the present invention will be described below. Here, a simple matrix display device will be described. However, this embodiment basically also applies to an EL display device and the like.
【0019】(実施例1)(図1)に従って説明する。
構成断面図、(図1)において、1はガラス基板、2は
ITO、3はフォトレジスト、4はインジウム金属層、
5は銅層、6は銅層の表面の金層、7はインジウム−銅
の合金からなる層である。(Example 1) (FIG. 1) will be described.
In the cross-sectional configuration diagram (FIG. 1), 1 is a glass substrate, 2 is ITO, 3 is a photoresist, 4 is an indium metal layer,
Reference numeral 5 is a copper layer, 6 is a gold layer on the surface of the copper layer, and 7 is a layer made of an indium-copper alloy.
【0020】ITOを主面全面に有するコーニング社製
#7059ガラス基板1を入手した。東京応化製ポジレ
ジスト、OFPRを使い、公知のフォトリソグラフィー
法でもって、(図1)(a)の如く、レジストパターン
3を作った。次に、O2アッシャーで、処理した。さら
に、公知の方法で、沃化水素酸で、ITOを微細加工し
た(図1)(a)。A Corning # 7059 glass substrate 1 having ITO on the entire main surface was obtained. Using a positive resist, OFPR manufactured by Tokyo Ohka Co., Ltd., a resist pattern 3 was formed by a known photolithography method as shown in FIG. Then, it was treated with an O2 asher. Further, ITO was finely processed with hydroiodic acid by a known method (FIG. 1) (a).
【0021】次に、約150℃以上に基板を加熱し、フ
ォトレジストを縮ませた。さらに、紫外線を照射、発生
するオゾンにより、ITOのレジストからの露出部を洗
浄した(図1)(b)。Next, the substrate was heated to about 150 ° C. or higher to shrink the photoresist. Further, the exposed part of the ITO from the resist was washed with ozone generated by irradiation with ultraviolet rays (FIG. 1) (b).
【0022】硫酸インジウム、約60グラムと、硫酸ナ
トリウム、約10グラムを約1リットルの純水に溶解さ
せた溶液で、約0.1ミクロンの厚みのインジウム電気
鍍金をITO上に行う。次に、よく洗浄する。更に、酸
性の硫酸銅系の溶液で、この上に、約2ミクロンの厚み
の銅の電気鍍金を行った。さらに、市販の金の無電界鍍
金液により、この上に約0.2ミクロンの金層を形成し
た(図1)(c)。About 60 grams of indium sulphate and about 10 grams of sodium sulphate were dissolved in about 1 liter of pure water and indium electroplated to a thickness of about 0.1 micron on ITO. Next, wash thoroughly. Further, with an acidic copper sulfate-based solution, copper electroplating with a thickness of about 2 μm was performed thereon. Further, a commercially available gold electroless plating solution was used to form a gold layer of about 0.2 μm thereon (FIG. 1) (c).
【0023】レジストを有機溶剤で剥離し、よく洗浄
し、乾燥させ、(図1)(d)を得た。The resist was peeled off with an organic solvent, thoroughly washed and dried to obtain (d) in FIG.
【0024】この後、約150℃まで、徐徐に昇温し、
最終てきには約260℃まで、昇温させ、基板を熱処理
した。この時、インジウム金属層は、インジウム−銅の
合金層になっているのが、オージェ電子分析によって明
かになった。かくて、(図1)(e)を得た。これら、
鍍金層のITOへの付着力は実用に耐えるものであっ
た。Thereafter, the temperature is gradually raised to about 150 ° C.,
Finally, the temperature was raised to about 260 ° C. and the substrate was heat-treated. At this time, it was revealed by Auger electron analysis that the indium metal layer was an indium-copper alloy layer. Thus, (FIG. 1) (e) was obtained. these,
The adhesion of the plating layer to ITO was practical.
【0025】ITO電極のシート抵抗は、約1桁下がっ
ていた。通常の如く、この基板に、ポリイミド膜を形成
し、をレーヨン繊維を用いて、ラビング処理を行った。
このような2枚の基板を、ITO膜が対向するように、
間隙が7.0ミクロンとなるように、貼り合わせ、この
間隙にSTN用ネマティック液晶組成物を充填した。ク
ロストークは、ほとんど無く、コントラストも約50%
上昇した。The sheet resistance of the ITO electrode was reduced by about one digit. As usual, a polyimide film was formed on this substrate and was rubbed with rayon fibers.
The two substrates are placed so that the ITO films face each other.
The two were bonded so that the gap was 7.0 μm, and this gap was filled with the nematic liquid crystal composition for STN. Almost no crosstalk and contrast of about 50%
Rose.
【0026】(実施例2)(図2)に従って説明する。
構成断面図、(図2)において、8はガラス基板、9は
ITO、10はフォトレジスト、11はニッケル金属
層、12は金層である。(Embodiment 2) (FIG. 2) will be described.
In the configuration cross-sectional view (FIG. 2), 8 is a glass substrate, 9 is ITO, 10 is a photoresist, 11 is a nickel metal layer, and 12 is a gold layer.
【0027】ITO9を主面に有するコーニング社製#
7059ガラス基板8を入手した。東京応化製ポジレジ
ストを使い、公知のフォトリソグラフィー法でもって、
(図2)(a)の如く、レジストパターン10を作っ
た。次に、O2アッシャーで、処理した。次に、市販の
塩鉄溶液でITOを微細加工して、(図2)(a)を得
た。Corning # with ITO 9 on the main surface
The 7059 glass substrate 8 was obtained. Using a positive resist made by Tokyo Ohka, with a well-known photolithography method,
(FIG. 2) A resist pattern 10 was formed as shown in FIG. Then, it was treated with an O2 asher. Next, the ITO was finely processed with a commercially available salt iron solution to obtain (a) in FIG.
【0028】次に、基板をドライエッチャーで、約20
分、酸素プラズマに晒す。かくして、レジストの端部
は、一般に、酸素プラズマによるレジスト材料の分解が
より速いことにより、実質上、フォトレジストを縮ませ
た効果が発生する。すなわち、清浄なITOのレジスト
からの露出部が得られる(図2)(b)。Next, the substrate is dried with an etcher for about 20 minutes.
Min, expose to oxygen plasma. Thus, the edges of the resist generally have the effect of substantially shrinking the photoresist due to the faster decomposition of the resist material by the oxygen plasma. That is, an exposed portion of the clean ITO is obtained (FIG. 2) (b).
【0029】次に、市販の薬品を用い、前記露出部にの
み、選択的に、約0.5ミクロンのニッケル電気鍍金を
行った。この時、析出速度の制御は、ニッケル層の膜剥
がれを防ぐため、非常に重要である。さらに、金の電界
鍍金液により、約1.5ミクロンの金層を得る(図2)
(c)。Next, using a commercially available chemical, nickel electroplating of about 0.5 micron was selectively performed only on the exposed portion. At this time, control of the deposition rate is very important in order to prevent film peeling of the nickel layer. Furthermore, a gold layer of about 1.5 μm is obtained by gold electroplating solution (FIG. 2).
(C).
【0030】レジストを有機塩素系溶剤で剥離し、よく
洗浄し、乾燥させ、(図2)(d)を得た。The resist was stripped with an organic chlorine-based solvent, thoroughly washed, and dried to obtain (FIG. 2) (d).
【0031】この後、基板を約100℃で熱処理した。
これら、鍍金層のITOへの付着力は実用に耐えるもの
であった。After that, the substrate was heat-treated at about 100.degree.
The adhesion of the plating layer to ITO was practically useable.
【0032】ITO電極のシート抵抗は、約1桁下がっ
ていた。通常の如く、この基板に、ポリイミド膜を形成
し、をレーヨン繊維を用いて、ラビング処理を行った。
このような2枚の基板を、ITO膜が対向するように、
間隙が7.0ミクロンとなるように、貼り合わせ、この
間隙にSTN用ネマティック液晶組成物を充填した。ク
ロストークは、ほとんど無く、コントラストも約40%
上昇した。The sheet resistance of the ITO electrode was reduced by about one digit. As usual, a polyimide film was formed on this substrate and was rubbed with rayon fibers.
The two substrates are placed so that the ITO films face each other.
The two were bonded so that the gap was 7.0 μm, and this gap was filled with the nematic liquid crystal composition for STN. Almost no crosstalk and contrast of about 40%
Rose.
【0033】[0033]
【発明の効果】以上本発明は、表示装置の表示品位の向
上を実現するに有力な方法を提供するものであり、産業
に貢献するところ大である。As described above, the present invention provides an effective method for improving the display quality of a display device and greatly contributes to the industry.
【図1】本発明の実施例を説明するための構成断面図FIG. 1 is a structural cross-sectional view for explaining an embodiment of the present invention.
【図2】本発明の実施例を説明するための構成断面図FIG. 2 is a configuration cross-sectional view for explaining an embodiment of the present invention.
1 ガラス基板 2 ITO 3 フォトレジスト 4 インジウム金属層 5 銅層 6 銅層の表面の金層 7 インジウム−銅の合金からなる層 8 ガラス基板 9 ITO 10 フォトレジスト 11 ニッケル金属層 12 金層 1 Glass Substrate 2 ITO 3 Photoresist 4 Indium Metal Layer 5 Copper Layer 6 Gold Layer on Copper Surface 7 Layer Made of Indium-Copper Alloy 8 Glass Substrate 9 ITO 10 Photoresist 11 Nickel Metal Layer 12 Gold Layer
Claims (4)
望の状態にパターン化されたレジスト膜を形成し、透明
電極の腐食液で微細加工をし、洗浄し、次に前記レジス
ト膜を縮まらせ、透明電極の露出部をオゾンまたは酸素
プラズマで清浄化し、透明電極の露出部にインジウム電
界鍍金を施し、更に、この上に、銅単層電界鍍金また
は、金単層電界鍍金または、銅電界鍍金と金の電界また
は無電界鍍金の2層鍍金をこの順に施し、洗浄、乾燥さ
せ、レジスト膜を除去、洗浄、乾燥させ、この後、熱処
理することを特徴とする表示装置用基板の製法。1. A resist film patterned in a desired state is formed on a transparent electrode over the entire main surface of a substrate, finely processed by a corrosive liquid for the transparent electrode, and washed, and then the resist is formed. The film is shrunk, the exposed part of the transparent electrode is cleaned with ozone or oxygen plasma, indium electrolytic plating is applied to the exposed part of the transparent electrode, and further, copper single-layer electrolytic plating or gold single-layer electrolytic plating is applied on this. A substrate for a display device, characterized in that two-layer plating of copper electric field plating and gold electric field or electroless plating is applied in this order, washed and dried, the resist film is removed, washed and dried, and then heat-treated. Manufacturing method.
望の状態にパターン化されたレジスト膜を形成し、透明
電極の腐食液で微細加工をし、洗浄し、次に前記レジス
ト膜を縮まらせ、透明電極の露出部をオゾンまたは酸素
プラズマで清浄化し、透明電極の露出部にニッケル電界
または無電界鍍金を施し、更に、この上に、銅単層電界
鍍金または、金単層電界または無電界鍍金または、銅電
界鍍金と金の電界または無電界鍍金の2層鍍金をこの順
に施し、洗浄、乾燥させ、レジスト膜を除去、洗浄、乾
燥させ、この後、熱処理することを特徴とする表示装置
用基板の製法。2. A resist film patterned in a desired state is formed on a transparent electrode over the entire main surface of a substrate, finely processed with a corrosive liquid for the transparent electrode, washed, and then the resist is formed. The film is shrunk, the exposed part of the transparent electrode is cleaned with ozone or oxygen plasma, and the exposed part of the transparent electrode is subjected to nickel electric field or electroless plating, and further, copper single layer electric field plating or gold single layer is formed on this. Characteristic of performing electric field or electroless plating or two-layer electroplating of copper electric field plating and gold electric field or electroless plating in this order, washing and drying, removing the resist film, washing and drying, and then performing heat treatment And manufacturing method of substrate for display device.
により縮まらせることを特徴とする請求項1または2記
載の表示装置用基板の製法。3. The method for manufacturing a substrate for a display device according to claim 1, wherein the patterned resist film is contracted by a thermal effect.
たは酸素プラズマを照射することにより、前記レジスト
膜を縮まらせることを特徴とする請求項1または2記載
の表示装置用基板の製法。4. The method for manufacturing a substrate for a display device according to claim 1, wherein the patterned resist film is irradiated with ozone or oxygen plasma to shrink the resist film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30195792A JPH06148661A (en) | 1992-11-12 | 1992-11-12 | Production of substrate for display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30195792A JPH06148661A (en) | 1992-11-12 | 1992-11-12 | Production of substrate for display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06148661A true JPH06148661A (en) | 1994-05-27 |
Family
ID=17903158
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30195792A Pending JPH06148661A (en) | 1992-11-12 | 1992-11-12 | Production of substrate for display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06148661A (en) |
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1992
- 1992-11-12 JP JP30195792A patent/JPH06148661A/en active Pending
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WO1999059024A3 (en) * | 1998-05-12 | 2000-01-13 | Minnesota Mining & Mfg | Display substrate electrodes with auxiliary metal layers for enhanced conductivity |
US6037005A (en) * | 1998-05-12 | 2000-03-14 | 3M Innovative Properties Company | Display substrate electrodes with auxiliary metal layers for enhanced conductivity |
JP2002514790A (en) * | 1998-05-12 | 2002-05-21 | ミネソタ マイニング アンド マニュファクチャリング カンパニー | Display substrate electrode with auxiliary metal layer to enhance conductivity |
US6756087B2 (en) | 1998-12-25 | 2004-06-29 | International Business Machines Corporation | Method for removing organic compound by ultraviolet radiation and apparatus therefor |
US6468599B1 (en) | 1998-12-25 | 2002-10-22 | International Business Machines Corporation | Method for removing organic compound by ultraviolet radiation |
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JP2004519009A (en) * | 2001-02-03 | 2004-06-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for improving the conductivity of transparent conductor lines |
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US7343666B2 (en) | 2004-06-30 | 2008-03-18 | Hitachi Global Storage Technologies Netherlands B.V. | Methods of making magnetic write heads with use of linewidth shrinkage techniques |
US8230582B2 (en) | 2004-06-30 | 2012-07-31 | HGST Netherlands B.V. | Methods of making magnetic write heads with use of a resist channel shrinking solution having corrosion inhibitors |
JP2014178691A (en) * | 2006-01-20 | 2014-09-25 | Intellectual Discovery Co Ltd | Plastic flat display and method of manufacturing the same |
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