JPH0614535B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0614535B2 JPH0614535B2 JP59180447A JP18044784A JPH0614535B2 JP H0614535 B2 JPH0614535 B2 JP H0614535B2 JP 59180447 A JP59180447 A JP 59180447A JP 18044784 A JP18044784 A JP 18044784A JP H0614535 B2 JPH0614535 B2 JP H0614535B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- tunnel injection
- gate
- channel
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000002347 injection Methods 0.000 claims description 42
- 239000007924 injection Substances 0.000 claims description 42
- 230000006698 induction Effects 0.000 claims description 11
- 230000003068 static effect Effects 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 239000000969 carrier Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 101100336281 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GCR1 gene Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明はトンネル注入型静電誘導トランジスタを用いた
半導体集積回路に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit using a tunnel injection type static induction transistor.
静電誘電型トランジスタ（以下、ＳＩＴと略す）は、ゲ
ート領域とゲート領域の間で空乏層がつながって生じて
いる電位障壁の高さを変化させてソース領域・ドレイン
領域の間の電流を制御するトランジスタである。このと
き、電位の制御が空乏層の静電容量を通して行われるこ
とから、バイポーラトランジスタにおけるベース層の蓄
積容量がないものに相当し、ＦＥＴと比べてみても非常
に高速、低雑音で動作するという優れた特性を有してい
る。An electrostatic dielectric transistor (hereinafter abbreviated as SIT) controls the current between a source region and a drain region by changing the height of a potential barrier generated by connecting a depletion layer between gate regions. It is a transistor. At this time, since the control of the potential is performed through the capacitance of the depletion layer, it corresponds to a bipolar transistor having no storage capacitance in the base layer, and operates at very high speed and low noise as compared with an FET. It has excellent characteristics.
しかし、従来のＳＩＴはソース領域・ドレイン領域間、
特にソース領域・ゲート領域間の寸法が割合と大きな構
造になっていたため、キャリアが結晶格子の散乱を受
け、上限周波数が制限される問題点があった。However, in the conventional SIT, between the source region and the drain region,
In particular, since the size between the source region and the gate region is relatively large, the carriers are scattered by the crystal lattice, and there is a problem that the upper limit frequency is limited.
このような問題点を除去するために、キャリアが結晶格
子の散乱を受けずに熱電子速度で動くことのできる熱電
子放射型ＳＩＴが先に本願発明者等よって提案された。
この熱電子放射型ＳＩＴによれば、例えば、ＧａＡｓを
用いた場合、電位障壁の幅Ｗgを０．１μｍとしたとき
に、しゃ断周波数ｆｃは７８０ＧＨｚ程度にもなり、従
来に比べて上限周波数が高められ、素子の高速化が達成
される。In order to eliminate such a problem, the present inventors previously proposed a thermionic emission type SIT in which carriers can move at a thermoelectron velocity without being scattered by a crystal lattice.
According to this thermionic emission type SIT, for example, when GaAs is used and the width Wg of the potential barrier is 0.1 μm, the cut-off frequency fc becomes about 780 GHz, and the upper limit frequency is higher than that of the conventional one. Therefore, the speedup of the device is achieved.
しかし、更に高速のトランジスタを得ようとしたとき、
上記熱電子放射型ＳＩＴではしゃ断周波数が高々８００
Ｈｚ程度であり、それ以上の高速化を図ることが困難で
あった。However, when trying to get a faster transistor,
In the thermionic emission type SIT, the cutoff frequency is at most 800.
It was about Hz, and it was difficult to achieve higher speed.
また、従来の半導体集積回路はソース電極・ゲート電
極、ドレイン電極への配線が複雑となり、その取付けに
多くのスペースを要し、高集積化が困難であった。Further, in the conventional semiconductor integrated circuit, the wiring to the source electrode / gate electrode and the drain electrode is complicated, a lot of space is required for the attachment, and high integration is difficult.
本発明は、更に高速にして高集積化が容易な半導体集積
回路を提供することを目的とする。It is an object of the present invention to provide a semiconductor integrated circuit which can be further increased in speed and easily integrated.
本発明は、真性或いは半絶縁性基板の一部に第１導電型
の高不純物密度領域よりなる第１ドレイン領域を設け、
その第１ドレイン領域上に第１チャンネル領域、第１導
電型の第１トンネル注入領域及び第2導電型の第１ソー
ス領域を縦型に、また、前記第１チャンネル領域に接触
して前記第１チャンネル領域よりも禁制帯幅の大きい半
導体で第１ゲート領域を形成すると共に、真の第１ゲー
ト領域と第１ソース領域間の寸法をキャリアの平均自由
行程以下にしてノーマリオフ型の駆動用トンネル注入型
静電誘導トランジスタを形成する一方、この駆動用トン
ネル注入型静電誘導トランジスタに隣接する領域には前
記第１ドレイン領域を第２ソース領域としてこの第２ソ
ース領域上に第２チャンネル領域、第１導電型の第２ト
ンネル注入領域及び第２導電型の第２ドレイン領域を縦
型に、また、前記第２チャンネル領域に接触して前記第
２チャンネル領域よりも禁制帯幅の大きい半導体を用い
て前記第１ゲート領域よりも薄型の第２ゲート領域を形
成してノーマリオン型とした負荷抵抗用静電誘導トラン
ジスタを形成し、前記駆動用トンネル注入型静電誘導ト
ランジスタの第１ゲート領域に接して形成される電極に
信号入力端子、前記第１ソース領域に接して形成される
電極に接地端子、前記第１ドレイン領域に接して形成さ
れる電極に出力端子、更に前記負荷抵抗用静電誘導トラ
ンジスタの前記第２ドレイン領域に接して形成される電
極に電源端子をそれぞれ設けて集積回路を構成したこと
を特徴とする。The present invention provides a first drain region formed of a high-concentration impurity region of the first conductivity type in a part of an intrinsic or semi-insulating substrate,
A first channel region, a first conduction type first tunnel injection region, and a second conduction type first source region are vertically formed on the first drain region, and are in contact with the first channel region. The first gate region is formed of a semiconductor having a forbidden band width larger than that of the one-channel region, and the dimension between the true first gate region and the first source region is set to be equal to or smaller than the mean free path of carriers, so that a normally-off type driving tunnel is formed. An injection static induction transistor is formed, and a second channel region is formed on the second source region with the first drain region as a second source region in a region adjacent to the driving tunnel injection static induction transistor. The second tunnel injection region of the first conductivity type and the second drain region of the second conductivity type are vertically formed, and are in contact with the second channel region from the second channel region. A second gate region thinner than the first gate region is formed by using a semiconductor having a larger forbidden band width to form a normally-on type static induction transistor for load resistance, and the tunnel injection type for driving is formed. The electrode formed in contact with the first gate region of the static induction transistor has a signal input terminal, the electrode formed in contact with the first source region has a ground terminal, and the electrode formed in contact with the first drain region has an electrode. An integrated circuit is configured by providing a power supply terminal on each of the output terminal and an electrode formed in contact with the second drain region of the load resistance static induction transistor.
本願発明者等が提案したトンネル注入型ＳＩＴのしゃ断
周波数ｆｃは次式で与えられる。The cutoff frequency fc of the tunnel injection type SIT proposed by the inventors of the present application is given by the following equation.
ここで、τはトンネル遷移時間である。 Here, τ is the tunnel transition time.
トンネル遷移時間τは次式で与えられる。The tunnel transition time τ is given by the following equation.
ここで、 はプランク定数ｈを２πで除したもの（１．０５４６×
１０-34Ｊ・ｓｅｃ）、Ｅはトンネル接合の電界強度、
ａは格子定数である。 here, Is Planck's constant h divided by 2π (1.0546 ×
10-34 J · sec), E is the electric field strength of the tunnel junction,
a is a lattice constant.
格子定数ａとしてＧａＡｓの５．６５３３Åとしたとき
に、電界強度を１０6Ｖ／cm、５×１０6Ｖ／cm、１×１
０7Ｖ／cmとしたときのｆｃは前記（１）、（２）式よ
りそれぞれ１．３７×１０13Ｈｚ、６．８３×１０13Ｈ
ｚ、１．３７×１０14Ｈｚとなり、しゃ断周波数は１０
０ＴＨｚ程度にもなる。この値は本願発明者等が先に提
案した熱電子放射型ＳＩＴのおおよそ１００倍位であっ
て、熱電子注入よりも量子効果に基づくトンネル注入型
を用いれば、ＳＩＴのしゃ断周波数ｆｃを非常に高くし
得ることがわかる。When the lattice constant a is 5.6533Å of GaAs, the electric field strength is 10 6 V / cm, 5 × 10 6 V / cm, 1 × 1.
The fc at 0 7 V / cm is 1.37 × 10 13 Hz and 6.83 × 10 13 H from the equations (1) and (2), respectively.
z, 1.37 × 10 14 Hz, cutoff frequency is 10
It can be as high as 0 THz. This value is about 100 times that of the thermionic emission type SIT previously proposed by the inventors of the present application, and if the tunnel injection type based on the quantum effect rather than thermionic injection is used, the cut-off frequency fc of the SIT will be extremely high. You can see that it can be raised.
トンネル注入は雑音が小さいという特徴と、小さな電圧
で大きな電流が得られるので、ｇｍ（相互コンダクタン
ス）を大きくし易く電流駆動能力が高いという特徴があ
る。また、トンネル注入は温度上昇につれてよく生起す
るという特徴と有しているので、冷却する必要もないと
いうことになる。以上のことからトンネル注入型ＳＩＴ
は、集積回路用のトランジスタとして優れていることが
わかる。The tunnel injection has a feature that noise is small, and a large current can be obtained at a small voltage, so that gm (mutual conductance) can be easily increased and a current driving capability is high. In addition, since tunnel injection has a characteristic that it often occurs as the temperature rises, it means that cooling is not necessary. From the above, tunnel injection type SIT
Are excellent as transistors for integrated circuits.
以下、このトンネル注入型ＳＩＴを用いた集積回路につ
いて説明する。Hereinafter, an integrated circuit using this tunnel injection type SIT will be described.
第１図は本発明の一実施例に係る半導体集積回路の断面
図を示したものである。図において、１は真性半導体な
いしは半絶縁生のＧａＡｓ基板、２はドレイン領域とな
るべきｎ+領域、３はチャンネル領域のｎ層、４はトン
ネル注入層となるべく形成されたｎ+領域、５はトンネ
ル注入層となるべく形成されたｐ+領域でソース領域と
なるもの、６はＧａＡｓよりも禁制帯幅の大きいＧａ1
−ｘＡｌｘＡｓまたＧａ1−ｘＡｌｘＡｓ1−ｙＰｙ等の
ヘテロ接合ゲート領域で、トンネル注入層となるｐ+−
ｎ-領域に接して設けられているチャンネル領域３に接
して設ける。FIG. 1 is a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1 is an intrinsic semiconductor or semi-insulating GaAs substrate, 2 is an n + region that should be a drain region, 3 is an n layer of a channel region, 4 is an n + region formed to be a tunnel injection layer, and 5 is A p + region which is formed as a tunnel injection layer and serves as a source region, and 6 is Ga 1 having a larger forbidden band width than GaAs.
-XAlxAs or Ga 1 -xAlxAs 1 -yPy, etc. In the heterojunction gate region, p + − serving as a tunnel injection layer
It is provided in contact with the channel region 3 provided in contact with the n − region.
このチャンネル領域３中のソース領域近傍には電位障壁
のピークが生じるが、これを真のゲート領域とよんでい
る。チャンネル長（チャンネル領域中のソース領域とド
レイン領域間の寸法）が短い場合は、この真のゲート領
域の生じる位置は殆どドレイン電圧には影響されること
なく、ほぼソース領域５近傍にできる。従って、実質的
にソース領域５とゲート領域６との間の距離、即ちｎ+
トンネル注入領域４の厚みを平均自由行程以下にするこ
とにより、真のゲート領域とソース領域６間の寸法をキ
ャリアの平均自由行程以下とすることができ、また、こ
れによりトンネル注入構造の駆動ＳＩＴが得られる。A peak of the potential barrier occurs near the source region in the channel region 3, which is called a true gate region. When the channel length (the dimension between the source region and the drain region in the channel region) is short, the position where the true gate region is generated can be almost near the source region 5 without being affected by the drain voltage. Therefore, substantially the distance between the source region 5 and the gate region 6, that is, n +
By setting the thickness of the tunnel injection region 4 to be equal to or smaller than the mean free path, the dimension between the true gate region and the source region 6 can be set to be equal to or smaller than the mean free path of carriers. Is obtained.
この第１図の左側に形成される駆動用トンネル注入型Ｓ
ＩＴに隣接する領域に、前記ドレイン領域２をソース領
域とする負荷用トンネル注入型ＳＩＴが形成される。３
０はチャンネル領域３と同じ材料で形成されたｎ層のチ
ャンネル領域、４０はトンネル注入領域４と同様ｎ+層
に形成されたトンネル注入領域、５０はソース領域５と
同じ材料でｐ+トンネル注入層となるべく形成されたド
レイン領域である。また、６０はゲート領域６と同じ材
料で形成されたゲート領域であるが、ゲート領域６より
も薄く形成することによりノーマリオン動作型ＳＩＴと
している。Driving tunnel injection type S formed on the left side of FIG.
A tunnel tunneling type SIT for load having the drain region 2 as a source region is formed in a region adjacent to IT. Three
0 is an n-layer channel region made of the same material as the channel region 3, 40 is a tunnel injection region formed in the n + layer like the tunnel injection region 4, and 50 is a p + tunnel injection made of the same material as the source region 5. It is a drain region formed as a layer. Further, 60 is a gate region made of the same material as the gate region 6, but is formed to be thinner than the gate region 6 to form a normally-on operation type SIT.
９はゲート電極、１０はソース電極、１１は出力電極、
１２は電源を供給するドレイン電極、１３はＳｉ3Ｎ4、
ＳｉＯ2、ポリイミド樹脂等の絶縁物２０は入力端子、
２１はソース電極に設けた接地端子、２２は出力端子、
２３は電源端子である。9 is a gate electrode, 10 is a source electrode, 11 is an output electrode,
12 is a drain electrode for supplying power, 13 is Si 3 N 4 ,
The insulator 20 such as SiO 2 or polyimide resin is an input terminal,
21 is a ground terminal provided on the source electrode, 22 is an output terminal,
23 is a power supply terminal.
ｐ+層のソース領域５よりドレイン領域２までの不純物
密度分布は次のようにする。即ち、空乏層の拡がりＷは
次式で与えられる。The impurity density distribution from the source region 5 to the drain region 2 of the p + layer is as follows. That is, the spread W of the depletion layer is given by the following equation.
ここで、ＮA、ＮDはそれぞれｐ+層のソース領域５とｎ+
のトンネル注入領域４の不純物密度で均一としている。
εsは誘導率、qは単位電荷、Ｖｂｉは拡散電位、Ｖａは
印加電圧である。 Here, N A and N D are the source region 5 and n + of the p + layer, respectively.
The tunnel implant region 4 has a uniform impurity density.
εs is the inductivity, q is the unit charge, Vbi is the diffusion potential, and Va is the applied voltage.
ｎ層のチャンネル領域３が空乏化するために必要な電圧
Ｖは次式で与えられる。The voltage V required for depleting the channel region 3 of the n layer is given by the following equation.
ここで、Ｗ２はチャンネル長、Ｎはチャンネル領域の不
純物密度で均一であるとした。 Here, it is assumed that W 2 is a channel length and N is a uniform impurity density in the channel region.
ｐ+層のソース領域５の厚さＷｐ+は次式で与えられる。The thickness Wp + of the source region 5 of the p + layer is given by the following equation.
ここで、Ｗ1はｎ+層のトンネル注入領域４の厚さであ
る。 Here, W 1 is the thickness of the tunnel injection region 4 of the n + layer.
（３），（４），（５）式よりｐ+層のソース領域５、
ｎ+層のソース領域４，ｎ層のチャンネル領域３の不純
物密度と厚さを決めることができる。From the expressions (3), (4), and (5), the source region 5 of the p + layer,
The impurity density and thickness of the source region 4 of the n + layer and the channel region 3 of the n layer can be determined.
例として、（１）ＮA＝１×１０20cm-3，Ｗｐ+＝１０
Å，ＮD＝５×１０18cm-3，Ｗ1＝１００Å，Ｗ2＝２５
０Å，Ｎ＝１×１０18cm（２）ＮA＝１×１０20cm-3，
Ｗｐ+＝１５Å，ＮD＝１×１０18cm-3，Ｗ1＝８０Å，
Ｎ＝１×１０18cm，Ｗ2＝７５Åである。As an example, (1) N A = 1 × 10 20 cm −3 , Wp + = 10
Å, N D = 5 × 10 18 cm -3 , W 1 = 100 Å, W 2 = 25
0Å, N = 1 × 10 18 cm (2) N A = 1 × 10 20 cm -3 ,
Wp + = 15Å, N D = 1 × 10 18 cm -3 , W 1 = 80Å,
N = 1 × 10 18 cm and W 2 = 75Å.
これからトンネル注入層の電界強度は拡散電位だけで約
１ＭＶ／ｃｍ以上となる。この電界強度と（１）式及び
（２）式からｆｃは１．３７×１０13Ｍｚ（１３．７Ｔ
Ｈｚ）となり、またチャンネルｎ層の厚みも７５〜２０
０Åと薄いので、従来の熱電子放射型ＳＩＴの動作限界
周波数以上の領域で動作するトランジスタが得られる。From this, the electric field strength of the tunnel injection layer becomes about 1 MV / cm or more only by the diffusion potential. From this electric field strength and the expressions (1) and (2), fc is 1.37 × 10 13 Mz (13.7T).
Hz), and the thickness of the channel n layer is 75 to 20.
Since the thickness is as thin as 0Å, a transistor that operates in a region above the operating limit frequency of the conventional thermionic emission SIT can be obtained.
ゲートのヘテロ接合の組成はｘ＝０．３、ｙ＝０．０１
程度であり、ソース電極、出力および電源端子電極１
０，１１，１２はＡｕ−Ｇｅ，Ａｕ−Ｇｅ−Ｎｉ等の合
金、ゲート電極９はＡｌまたはＡｕ，Ｗ，Ｐｔ等の重金
属で形成されている。The composition of the gate heterojunction is x = 0.3, y = 0.01
Source electrode, output and power supply terminal electrode 1
0, 11, and 12 are alloys such as Au-Ge and Au-Ge-Ni, and the gate electrode 9 is formed from Al or heavy metal such as Au, W, and Pt.
第２図は第１図の等価回路を示したものである。FIG. 2 shows an equivalent circuit of FIG.
３１は第１図に示した半導体集積回路の断面図の左側に
形成された駆動用トンネル注入型ＳＩＴでノーマリオフ
特性を有するもの、３２は第１図の右側に形成され負荷
抵抗として用いるノーマリオン特性を有する負荷抵抗用
トンネル注入型ＳＩＴの等価回路を示している。２０，
２１，２２，２３はそれぞれ入力端子、接地端子、出力
端子、電源端子である。入力端子２０に印加される入力
信号が「ロー」のときは駆動用トンネル注入型ＳＩＴ３
１がオフで出力端子２２へは「ハイ」レベルが生じ、入
力信号が「ハイ」になると、駆動用トンネル注入型ＳＩ
Ｔ３１はオンして出力端子２２へは「ロー」レベルが生
じ、いわゆるインバータ動作をする。ここで、負荷抵抗
用トンネル注入型ＳＩＴ３２はノーマリオン動作とする
ことにより等価的に抵抗として機能させている。Reference numeral 31 is a tunnel injection type SIT for driving formed on the left side of the cross-sectional view of the semiconductor integrated circuit shown in FIG. 1 and having a normally-off characteristic, and 32 is a normally-on characteristic formed on the right side of FIG. 1 and used as a load resistance. 2 shows an equivalent circuit of a tunnel injection type SIT for load resistance having the above. 20,
Reference numerals 21, 22, and 23 are an input terminal, a ground terminal, an output terminal, and a power supply terminal, respectively. When the input signal applied to the input terminal 20 is "low", the drive tunnel injection type SIT3
When "1" is off and a "high" level is generated at the output terminal 22 and the input signal becomes "high", the drive tunnel injection type SI
T31 is turned on, a "low" level is generated at the output terminal 22, and a so-called inverter operation is performed. Here, the load resistance tunnel injection type SIT 32 functions as a resistance equivalently by the normally-on operation.
このように本実施例の集積回路は、トンネル注入型ＳＩ
Ｔが縦型構造であるので、チヤンネル長を容易に１００
０Å以下にでき、更に上部に形成されるソース電極、ゲ
ート電極への配線が容易であることによって、ソース電
極、ゲート電極、ドレイン電極の微細配線を要するＦＥ
ＴないしはＨＥＭＴによる集積回路に比べて製造が容易
となる。そめに配線部分に要する面積をおおよそ２／３
に減らせる結果、高集積化が実現できるようになる。As described above, the integrated circuit of the present embodiment is a tunnel injection type SI.
Since T has a vertical structure, the channel length can be easily set to 100.
FE which requires a fine wiring of the source electrode, the gate electrode, and the drain electrode because it can be made 0 Å or less and the wiring to the source electrode and the gate electrode formed on the upper portion is easy.
It is easier to manufacture than an integrated circuit using T or HEMT. The area required for the wiring part is approximately 2/3
As a result, high integration can be realized.
以上のように本発明によれば、ノーマリオフ特性の駆動
用トンネル注入型ＳＩＴにノーマリオン特性の負荷用ト
ンネル注入型ＳＩＴを直列に接続した集積回路を形成す
るようにしたので、わざわざ別に抵抗を作ること無く同
じ工程で効率よく集積回路が形成できる上、遮断周波数
が出願人が先に提案した熱電子放射型ＳＩＴよりも非常
に高速の半導体集積回路が容易に得られる。As described above, according to the present invention, the driving tunnel injection type SIT having the normally-off characteristic and the load tunnel injection type SIT having the normally-on characteristic are connected in series to form an integrated circuit. In this way, an integrated circuit can be efficiently formed in the same process without using the semiconductor device, and a semiconductor integrated circuit having a cutoff frequency much higher than that of the thermionic emission SIT proposed by the applicant can be easily obtained.
第１図は本発明の一実施例に係る半導体集積回路の断面
図、第２図はその等価回路図である。 １……基板、２……駆動用トンネル注入型ＳＩＴのドレ
イン領域兼負荷抵抗用トンネル注入型ＳＩＴのソース領
域、３、３０……チヤンネル領域、４、４０……トンネ
ル注入領域、５……ソース領域、５０……ドレイン領
域、６、６０……ゲート領域、２０……入力端子、２１
……接地端子、２２……出力端子、２３……電源端子。FIG. 1 is a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. 1 ... Substrate, 2 ... Drain region of driving tunnel injection type SIT and source region of load injection tunnel injection type SIT, 3, 30 ... Channel region, 4, 40 ... Tunnel injection region, 5 ... Source Area, 50 ... drain area, 6, 60 ... gate area, 20 ... input terminal, 21
...... Grounding terminal, 22 …… Output terminal, 23 …… Power supply terminal.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 本谷 薫 宮城県仙台市米ヶ袋２丁目１番９号406 (56)参考文献 特開 昭57−186374（ＪＰ，Ａ) 昭和50年電気四学会連合大会講演論文集 第537〜540頁 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaoru Motoya 2-9-9 Yonegabukuro, Sendai-shi, Miyagi 406 (56) Reference JP-A-57-186374 (JP, A) Proceedings of the Federation Conference, pp. 537-540
Claims (2)
型の高不純物密度領域よりなる第１ドレイン領域を設
け、その第１ドレイン領域上に第１チャンネル領域、第
１導電型の第１トンネル注入領域及び第２導電型の第１
ソース領域を縦型に、また、前記第１チャンネル領域に
接触して前記第１チャンネル領域よりも禁制帯幅の大き
い半導体で第１ゲート領域を形成すると共に、真の第１
ゲート領域と第１ソース領域間の寸法をキャリアの平均
自由行程以下にしてノーマリオフ型の駆動用トンネル注
入型静電誘導トランジスタを形成する一方、この駆動用
トンネル注入型静電誘導トランジスタに隣接する領域に
は前記第１ドレイン領域を第２ソース領域としてこの第
２ソース領域上に第２チャンネル領域、第１導電型の第
２トンネル注入領域及び第２導電型の第２ドレイン領域
を縦型に、また、前記第２チャンネル領域に接触して前
記第２チャンネル領域よりも禁制帯幅の大きい半導体を
用いて前記第１ゲート領域よりも薄型の第２ゲート領域
を形成してノーマリオン型とした負荷抵抗用トンネル注
入型静電誘導トランジスタを形成し、前記駆動用トンネ
ル注入型静電誘導トランジスタの第１ゲート領域に接し
て形成される電極に信号入力端子、前記第１ソース領域
に接して形成される電極に接地端子、前記第１ドレイン
領域に接して形成される電極に出力端子、更に前記負荷
抵抗用トンネル注入型静電誘導トランジスタの前記第２
ドレイン領域に接して形成される電極に電源端子をそれ
ぞれ設けて集積回路を構成したことを特徴とする半導体
集積回路。1. A first drain region formed of a high impurity density region of the first conductivity type is provided in a part of an intrinsic or semi-insulating substrate, and a first channel region and a first conductivity type are provided on the first drain region. First tunnel injection region and first of second conductivity type
The source region is formed vertically, and the first gate region is formed by contacting the first channel region with a semiconductor having a forbidden band width larger than that of the first channel region.
A region between the gate region and the first source region is equal to or smaller than the mean free path of carriers to form a normally-off driving tunnel injection static induction transistor, and a region adjacent to the driving tunnel injection static induction transistor. A second channel region, a second tunnel injection region of the first conductivity type, and a second drain region of the second conductivity type are vertically formed on the second source region using the first drain region as a second source region. A normally-on type load is formed by contacting the second channel region and forming a second gate region thinner than the first gate region by using a semiconductor having a forbidden band width larger than that of the second channel region. An electrode that forms a tunnel injection static induction transistor for resistance and is formed in contact with the first gate region of the drive tunnel injection static induction transistor. A signal input terminal, a ground terminal for an electrode formed in contact with the first source region, an output terminal for an electrode formed in contact with the first drain region, and the tunnel injection static induction transistor for load resistance. Second
A semiconductor integrated circuit comprising an electrode formed in contact with a drain region, each of which is provided with a power supply terminal to form an integrated circuit.
ンネルＧａＡｓ、ゲート領域がＧａ１−ｘＡｌｘＡｓな
いしＧａ１−ｘＡｌxＡｓ1-yＰyで形成されてなる半導
体集積回路。2. A semiconductor integrated circuit according to claim 1, wherein the channel GaAs and the gate region are formed of Ga 1-x Al x As or Ga 1-x Al x As 1-y P y .
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59180447A JPH0614535B2 (en) | 1984-08-31 | 1984-08-31 | Semiconductor integrated circuit |
| GB08519851A GB2163002B (en) | 1984-08-08 | 1985-08-07 | Tunnel injection static induction transistor and its integrated circuit |
| FR858512117A FR2569056B1 (en) | 1984-08-08 | 1985-08-07 | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
| DE19853528562 DE3528562A1 (en) | 1984-08-08 | 1985-08-08 | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND COMPREHENSIVE INTEGRATED CIRCUIT |
| GB08723051A GB2194677B (en) | 1984-08-08 | 1987-10-01 | Tunnel injection static induction transistor integrated circuit |
| US07/147,656 US4870469A (en) | 1984-08-08 | 1988-01-25 | Tunnel injection type static transistor and its integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59180447A JPH0614535B2 (en) | 1984-08-31 | 1984-08-31 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6159877A JPS6159877A (en) | 1986-03-27 |
| JPH0614535B2 true JPH0614535B2 (en) | 1994-02-23 |
Family
ID=16083387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59180447A Expired - Lifetime JPH0614535B2 (en) | 1984-08-08 | 1984-08-31 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0614535B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411774A (en) * | 1987-07-06 | 1989-01-17 | Honda Motor Co Ltd | Running gear |
| KR101874414B1 (en) * | 2012-04-05 | 2018-07-04 | 삼성전자주식회사 | High side gate driver, switching chip, and power device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57186374A (en) * | 1981-05-12 | 1982-11-16 | Semiconductor Res Found | Tunnel injection type travelling time effect semiconductor device |
-
1984
- 1984-08-31 JP JP59180447A patent/JPH0614535B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| 昭和５０年電気四学会連合大会講演論文集第５３７〜５４０頁 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6159877A (en) | 1986-03-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4364072A (en) | Static induction type semiconductor device with multiple doped layers for potential modification | |
| US4907053A (en) | Semiconductor integrated circuit | |
| US4994872A (en) | Insulated gate static induction transistor and integrated circuit including same | |
| US5631483A (en) | Power device integrated structure with low saturation voltage | |
| JPS6352475B2 (en) | ||
| JPH0439770B2 (en) | ||
| US4839703A (en) | High speed and power transistor | |
| US4317127A (en) | Static induction transistor and integrated circuit utilizing same | |
| US5032880A (en) | Semiconductor device having an interposing layer between an electrode and a connection electrode | |
| US5359220A (en) | Hybrid bipolar/field-effect power transistor in group III-V material system | |
| JPH0230588B2 (en) | ||
| US5117268A (en) | Thermionic emission type static induction transistor and its integrated circuit | |
| US4700213A (en) | Multi-drain enhancement JFET logic (SITL) with complementary MOSFET load | |
| US5086330A (en) | Bipolar semiconductor switching device | |
| US4870469A (en) | Tunnel injection type static transistor and its integrated circuit | |
| US4903091A (en) | Heterojunction transistor having bipolar characteristics | |
| JPH11168099A (en) | Semiconductor device | |
| JPH0614535B2 (en) | Semiconductor integrated circuit | |
| JPH0680832B2 (en) | Semiconductor device | |
| US4178603A (en) | Schottky transistor with low residual voltage | |
| US4450468A (en) | Gallium arsenide ISL gate with punched-through bipolar driver transistor | |
| Nishizawa | Junction field-effect devices | |
| JP3107325B2 (en) | Semiconductor coupled superconducting element | |
| JPH0614534B2 (en) | Semiconductor integrated circuit | |
| JPH045274B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |