JPS6159877A - Semiconductor integrate circuit - Google Patents
Semiconductor integrate circuitInfo
- Publication number
- JPS6159877A JPS6159877A JP59180447A JP18044784A JPS6159877A JP S6159877 A JPS6159877 A JP S6159877A JP 59180447 A JP59180447 A JP 59180447A JP 18044784 A JP18044784 A JP 18044784A JP S6159877 A JPS6159877 A JP S6159877A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- integrated circuit
- gate
- drain
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000006698 induction Effects 0.000 claims abstract description 3
- 230000003068 static effect Effects 0.000 claims abstract description 3
- 238000002347 injection Methods 0.000 claims description 23
- 239000007924 injection Substances 0.000 claims description 23
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 230000010354 integration Effects 0.000 abstract description 4
- 241001640034 Heteropterys Species 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910017401 Au—Ge Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910004613 CdTe Inorganic materials 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明はトンネル注入型静電誘導トランジスタを用いた
半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit using a tunnel injection type static induction transistor.
［先行技術とその問題点コ
Ｉｌｐｌルミ誘導型トランジスタ下、 ＳＩＴと略す）
は。[Prior art and its problems] Ilpl lumi-induced transistor (abbreviated as SIT)
teeth.
ゲートとゲートの間で空乏層がつながって生じている電
位障壁の高さを変化させてソース・ドレイン間の電流を
制御するトランジスタである。このとき、ａ！位の制御
が空乏層の静電容量を通して行なわれることがら、バイ
ポーラトランジスタにおけるベース層の蓄積容量がない
ものに相当し。This is a transistor that controls the current between the source and drain by changing the height of the potential barrier created by connecting the depletion layers between the gates. At this time, a! Since the level is controlled through the capacitance of the depletion layer, this corresponds to a bipolar transistor without the storage capacitance of the base layer.
ＦＥＴと比べてみても非常に高速、低雑音で動作すると
いう優れた特性を有している。Compared to FETs, they have excellent characteristics of operating at extremely high speeds and with low noise.
しかし、従来のＳＩＴはソース・ドレイン間、特にソー
ス・ゲート間の寸法が割合と大きな構造になっていたた
め、キャリアが結晶格子の散乱を受け、上限周波数が制
限される問題点があった。However, the conventional SIT has a structure in which the dimensions between the source and the drain, particularly between the source and the gate, are relatively large, so that carriers are scattered by the crystal lattice, which limits the upper limit frequency.
このような問題点を除去するために、キャリアが結晶格
子の散乱を受けずに熱電子速度で動くことのできる熱電
子放射型ＳＩＴが先に本願発明者等によって提案された
。この熱電子放射型ＳＩＴによれば、例えば、ＧａＡｓ
を用いた場合、電位障壁の幅Ｗｇを０．１μｍとしたと
きに、しゃ断周波数ｆｃは７８０ＧＨｚ程度にもなり、
従来に比べて上限周波数が高められ、素子の高速化が達
成される。In order to eliminate such problems, the inventors of the present invention previously proposed a thermionic emission type SIT in which carriers can move at thermionic velocity without being subjected to scattering by the crystal lattice. According to this thermionic emission type SIT, for example, GaAs
When using , when the potential barrier width Wg is 0.1 μm, the cutoff frequency fc is about 780 GHz,
The upper limit frequency is increased compared to the conventional technology, and the speed of the device is increased.
しかし、更に高速のトランジスタを得ようとしたとき、
上記熱電子放射型ＳＩＴではしゃ断周波数が高々８００
Ｇ）Ｉｚ程度であり、それ以上の高速化を図ることが困
難であった。However, when trying to obtain even faster transistors,
In the thermionic emission type SIT mentioned above, the cutoff frequency is at most 800.
G) It was about Iz, and it was difficult to achieve higher speed.
また、従来の半導体集積回路はソース・ゲート。Also, conventional semiconductor integrated circuits are source-gate.
ドレインの配線が複雑となり、その取付けに多くのスペ
ースを要し、高集積化が困難であった。Drain wiring became complicated and required a lot of space for installation, making it difficult to achieve high integration.
［発明の目的］
本発明は、更に高速にして高集積化が容易な半導体集積
回路を提供することを目的とする。[Object of the Invention] It is an object of the present invention to provide a semiconductor integrated circuit that can be made faster and more easily integrated.
［発明の概要コ
このため本発明は、ゲートをチャンネルよりも禁制帯幅
の大きい半導体で構成したトンネル注入型ＳＩＴのゲー
トに信号入力端子、ソースに接地端子１、ドレインに出
力端子、更にドレインに抵抗を接続して電源端子を設け
て集積回路を構成したことを特徴としている。[Summary of the Invention] Therefore, the present invention provides a tunnel injection type SIT in which the gate is made of a semiconductor whose forbidden band width is larger than that of the channel. It is characterized in that an integrated circuit is constructed by connecting a resistor and providing a power supply terminal.
［発明の実施例］
本願発明者等が先に提案したトンネル注入型ＳＩＴのし
ゃ断周波数ｆｃは次式で与えられる。[Embodiments of the Invention] The cutoff frequency fc of the tunnel injection type SIT previously proposed by the inventors of the present application is given by the following equation.
ｆｃ＝ ・・・・・・（１）２
πτ
ここで、ではトンネル遷移時間である。fc= ・・・・・・(1)2
πτ Here, is the tunnel transition time.
トンネル遷移時間は次式で与えられる。The tunnel transition time is given by the following equation.
ｇＥａ °−°−（２）
ここで、にはブランク定数りを２πで除したもの（１，
０５４６Ｘ１０−３４Ｊ−ｓｅｃ）、Ｅはトンネル接合
の電界強度、ａは格子定数である。gEa °−°−(2) Here, is the blank constant divided by 2π (1,
0546 x 10-34 J-sec), E is the electric field strength of the tunnel junction, and a is the lattice constant.
格子定数ａとしてＧａＡｓのｓ、６５３３Ａとしたとき
に。When the lattice constant a is s of GaAs and 6533A.
電界強度を１０’ Ｖ／ｃａ、５Ｘ１０’ Ｖ／ｃｍ、
ｌＸｌ０’ Ｖ／ｃ＋ｎとしたときのｆｃは前記（１）
、 （２）式よりそれぞれ１．３７ＸｌＯ” ３
Ｈｚ、６．８３Ｘ１０１３ Ｈｚ、１．３７Ｘ１０″
１）１ｚとなり、しゃ断周波数はＩＱＯＴ）Ｉｚ程度に
もなる。Electric field strength is 10' V/ca, 5X10' V/cm,
When lXl0' V/c+n, fc is the above (1)
, (2), each 1.37XlO" 3
Hz, 6.83X1013 Hz, 1.37X10''
1) 1z, and the cutoff frequency is about IQOT)Iz.
この値は本願発明者等が先に提案した熱電子放射型ＳＩ
Ｔのおおよそ１００倍位であって、熱電子注入よりも量
子効果に基づくトンネル注入を用いれば、ＳＩＴのしゃ
断周波数ｆｃを非常に高くし得ることがわかる。This value is based on the thermionic emission type SI proposed earlier by the inventors.
It can be seen that the cutoff frequency fc of the SIT can be made very high by using tunnel injection which is approximately 100 times T and is based on quantum effects rather than hot electron injection.
トンネル注入は雑音が小さいという特徴と、小さな電圧
で大きな電流が得られるので、ｇｏ＋（相互コンダクタ
ンス）を大きくし易く電流駆動能力が高いという特徴が
ある。また、トンネル注入は温度上昇につれてよく生起
するという特徴を有しているので、冷却する必要もない
ということになる。Tunnel injection has the characteristics of low noise, and because a large current can be obtained with a small voltage, it is easy to increase go+ (mutual conductance) and has a high current driving ability. Further, since tunnel injection has the characteristic that it occurs more frequently as the temperature rises, there is no need for cooling.
以上のことからトンネル注入型ＳＩＴは、集積回路用の
トランジスタとして優れていることがわかる。From the above, it can be seen that the tunnel injection type SIT is excellent as a transistor for integrated circuits.
以下、このトンネル注入型ＳＩＴを用いた集積回路につ
いて説明する。An integrated circuit using this tunnel injection type SIT will be explained below.
第１図は本発明の一実施例に係る半導体集積回路の断面
図を示したものである。図において、１は真性半導体な
いしは半絶縁性のＧａＡｓ基板、２はドレインとなるべ
きｎ中領域、３はチャンネルのｎ層、４はトンネル注入
層となるべく形成されたｎ＋領領域５はトンネル注入層
とななるべく形成されたｐ＋領領域ソース領域となるも
の、６はＧａＡｓよりも禁制帯幅の大きいＧａ１−ｘＡ
ＱｘＡｓまたはＧａ ｓ −ｘＡＱｘＡｓ ｓ −ｙＰ
ｙ等のへテロ接合ゲート領域。FIG. 1 shows a cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1 is an intrinsic semiconductor or semi-insulating GaAs substrate, 2 is an n-type region to become a drain, 3 is an n-type channel layer, and 4 is an n+ region formed to be a tunnel injection layer 5 is a tunnel injection layer. 6 is Ga1-xA which has a larger forbidden band width than GaAs.
QxAs or Ga s -xAQxAs s -yP
Heterojunction gate region such as y.
７は抵抗負荷となるｎ領域、８はｎ領域７の抵抗負荷へ
の電極となるｎ中領域、９はゲート電極、１０はソース
電極、１１は出力電極、１２は電源を供給する電極、１
３はＳｉ３Ｎ４．ＳｉＯ２，ポリイミド樹脂等の絶縁物
、２０は入力端子、２１はソース端子で接地点、２２は
出力端子、２３は電源端子である。7 is an n region that serves as a resistive load, 8 is an n middle region that is an electrode for the resistive load of n region 7, 9 is a gate electrode, 10 is a source electrode, 11 is an output electrode, 12 is an electrode that supplies power, 1
3 is Si3N4. An insulator such as SiO2 or polyimide resin, 20 is an input terminal, 21 is a source terminal and a ground point, 22 is an output terminal, and 23 is a power supply terminal.
ソースのｐ中層５よりドレインまでの不純物導度分布は
次のようにすればよい、即ち、空乏層の拡がりは次式で
与えられる。The impurity conductivity distribution from the p-middle layer 5 of the source to the drain may be determined as follows, that is, the spread of the depletion layer is given by the following equation.
ここで、ＮＡ、ＮＤはそれぞれＰ＋十層とｎ＋十層の不
純密度で均一であるとしている。１５は誘電率、ｑは単
位電荷、Ｖｂｉは拡散電位、Ｖａは印加電圧である。Here, NA and ND are assumed to have uniform impurity densities of 10 P+ layers and 10 n+ layers, respectively. 15 is a dielectric constant, q is a unit charge, Vbi is a diffusion potential, and Va is an applied voltage.
チャンネルの０Ｍ３が空乏化するために必要な電圧Ｖは
次式で与えられる。The voltage V required to deplete 0M3 of the channel is given by the following equation.
ここで、Ｗ２はチャンネルの長さ、Ｎはチャンネルの不
純物密度で均一であるとした。Here, W2 is the length of the channel, and N is the impurity density of the channel, which is uniform.
ｐ中層５の厚さＷＰ＋は次式で与えられる。The thickness WP+ of the p-type intermediate layer 5 is given by the following equation.
ここで、Ｗ＋はｎ中層４の厚さである。Here, W+ is the thickness of the n-middle layer 4.
（３） 、 （４） 、 （５）式より２十層５．ｎ÷
層４．チャンネルの１層３の不純物密度と厚さを決める
ことができる。From equations (3), (4), and (5), 20 layers5. n÷
Layer 4. The impurity density and thickness of layer 3 of the channel can be determined.
例として、 （１） Ｎ Ａ ：ｌＸ１０２’ （Ｊｌ
−’ 、 Ｗｐ”＝１０人ｒ Ｎｏ＝５Ｘ１０” Ｃｍ
−’ 、Ｗｔ＝１００Ａ。As an example, (1) N A :lX102' (Jl
-', Wp”=10 peopler No=5X10” Cm
-', Wt=100A.
Ｗ ２ ＝２５０Ａ、 Ｎ＝ＩＸ１０” ’ ｃｍ、（
２）ＮＡ＝ＩＸ１０” ’ ａｒｒ −’ ＋ Ｗ’ｐ
÷＝１５Ａ、 Ｎ Ｄ ＝１ｘｘｏ１ｇａｎ−’ 、
Ｗｔ ＝ｓｏＡ、 Ｎ＝ＩＸ１０１” ０１１１． Ｗ
２ ＝７５人である。W 2 = 250A, N = IX10'' cm, (
2) NA=IX10"'arr-'+W'p
÷=15A, N D =1xxo1gan-',
Wt=soA, N=IX101” 0111.W
2 = 75 people.
ゲートのへテロ接合の組成はｘ ＝ ０ 、３、ｙ＝ｏ
、ｏｔ程度であり、ソース、出力および電源端子の電極
１０．１１．１２はＡｕ−Ｇｅ、Ａｕ−Ｇｏ−Ｎｉ等の
合金、ゲート電極９はＡＱまたはＡｕ、Ｗ、ＰＬ等の重
金属、７は抵抗で１０１２〜１０”ａｍ−’程度の不純
物密度を有する。The composition of the gate heterojunction is x = 0, 3, y = o
, ot, the source, output and power terminal electrodes 10, 11 and 12 are made of an alloy such as Au-Ge or Au-Go-Ni, the gate electrode 9 is made of AQ or a heavy metal such as Au, W, or PL, and 7 is made of an alloy such as Au-Ge or Au-Go-Ni. It has an impurity density of about 1012 to 10"am-' in terms of resistance.
第２図は第１図の等価回路を示したものである。FIG. 2 shows an equivalent circuit of FIG. 1.
３０はトンネル注入型ＳＩＴでノーマリオフ特性を有す
るもの、３１は前記トンネル注入型５ＩＴ３０の負荷抵
抗、 ２０，２１，２２．２３はそれぞれ入力端子、接
地端子、出力端子、電源端子である。入力がローのとき
はトンネル注入型５ＩＴ３０がオフで出力端子２２へは
ハイレベルが生じ、入力がハイになると、トンネル注入
型ＳＩＴはオンして出力端子２２へはローレベルが生じ
、いわゆるインバータ動作をする。ここで、流れる電流
はトンネル注入型ＳＩＴのオン抵抗が小さいので、おお
よそ負荷抵抗３１の値によって決定される０例えば、ｖ
ＤＤが０．１■で負荷抵抗が１００にΩであれば、電流
はおおよそ１μ＾となる。30 is a tunnel injection type SIT having normally-off characteristics, 31 is a load resistance of the tunnel injection type 5IT 30, and 20, 21, 22, and 23 are an input terminal, a ground terminal, an output terminal, and a power supply terminal, respectively. When the input is low, the tunnel injection type 5IT30 is off and a high level is generated at the output terminal 22. When the input is high, the tunnel injection type SIT is turned on and a low level is generated at the output terminal 22, resulting in so-called inverter operation. do. Here, since the on-resistance of the tunnel injection type SIT is small, the flowing current is approximately determined by the value of the load resistance 31, for example, 0.
If DD is 0.1■ and the load resistance is 100Ω, the current will be approximately 1μ^.
第３図は本発明の別の実施例を示したもので、負荷抵抗
をディプレッションモードのトンネル注入型ＳＩＴで構
成したものである。ここでは負荷となるトランジスタの
ゲート領域４０をノーマリオフのトランジスタよりも薄
く形成して、ノーマリオン動作とすることにより等価的
に抵抗としているので、特に第１図のように抵抗を作る
ことなしに。FIG. 3 shows another embodiment of the present invention, in which the load resistor is constructed of a depletion mode tunnel injection type SIT. Here, the gate region 40 of the transistor serving as a load is formed thinner than that of a normally-off transistor, and is operated in normally-on operation, thereby equivalently serving as a resistor, so that there is no need to create a resistor as shown in FIG.
インバータ動作をさせることができる。Inverter operation is possible.
ゲート領域４０は直接ソース領域５および４のｎ＋層へ
接触していてもかまわない、 ′負荷抵抗としての
トランジスタは、トンネル注入型ＳＩＴの他に、熱電子
放射型ＳＩＴ、通常のＳＩＴまたはＦＥＴであってもよ
い。The gate region 40 may be in direct contact with the n+ layer of the source regions 5 and 4. 'The transistor serving as the load resistor may be a thermionic emission type SIT, a normal SIT, or a FET in addition to a tunnel injection type SIT. There may be.
第４図は、第３図の等価回路を示したものである。FIG. 4 shows an equivalent circuit of FIG. 3.
３２はノーマリオン型のトランジスタによる抵抗である
。このインバータ回路の動作は第２図に述べた回路と同
様であるので、詳しい説明は省略する。32 is a resistor made of a normally-on type transistor. Since the operation of this inverter circuit is similar to the circuit described in FIG. 2, detailed explanation will be omitted.
以上の実施例では、ヘテロ接合型のゲート構造のものを
示したが、絶縁ゲート、ショットキーゲート、ｐｎ接合
ゲートであってもよいことは言う迄もない。In the above embodiments, a heterojunction type gate structure is shown, but it goes without saying that an insulated gate, a Schottky gate, or a pn junction gate may be used.
このように本実施例の集積回路は、トンネル注入型ＳＩ
Ｔが縦型構造であるので、チャンネル長を容易に１００
０Å以下にでき、更に上部に形成されるソース、ゲート
の配線が容易であることによって。In this way, the integrated circuit of this embodiment is a tunnel injection type SI
Since T has a vertical structure, the channel length can be easily reduced to 100
The thickness can be reduced to 0 Å or less, and the wiring for the source and gate formed on the top is easy.
ソース、ゲート、ドレインの微細配線を要するＦＥＴな
いしはＨＥＭＴによる集積回路に比べて製造が容易とな
る。そのために配線部分に要する面積をおおよそ２／３
に減らせる結果、高集積化が実現できるようになる。It is easier to manufacture than integrated circuits using FETs or HEMTs, which require fine wiring for sources, gates, and drains. Therefore, the area required for the wiring part is approximately 2/3
As a result, high integration can be realized.
尚１以上の実施例において、電源、アース、入出力の配
線は、プレーナ構造、絶縁物を介した２ＮＩ配線等の周
知の技術を用いることができる。材料はＧａＡｓに限ら
ず、ＳＬ 、 ＩｎＰ 、 ＩｎＡａ 、 ＩｎＳｂま
たはＩＩ−Ｖｌ族の化合物半導体でもよい、また、 Ｈ
ｇＴｅ、ＣｄＴｅとＨｇ Ｉ−ｘｃｄｘＴｅとの組み合
わせによることもできることは勿論である。In one or more embodiments, power supply, ground, and input/output wiring may use well-known techniques such as a planar structure or 2NI wiring via an insulator. The material is not limited to GaAs, but may also be SL, InP, InAa, InSb or II-Vl group compound semiconductors, or H
Of course, it is also possible to use a combination of gTe, CdTe and HgI-xcdxTe.
また、前記の集積回路は、本発明者等の開発による分子
層ないしは光分子層エピタキシャル成長法、あるいは、
気相成長、液相成長、ＭＯＣＶＤ法。Further, the above-mentioned integrated circuit can be produced using a molecular layer or photomolecular layer epitaxial growth method developed by the present inventors, or
Vapor phase growth, liquid phase growth, MOCVD method.
ＭＢＥ法、イオン注入、拡散、フォトリングラフィ。MBE method, ion implantation, diffusion, photolithography.
プラズマエツチング、化学エツチング、更には。Plasma etching, chemical etching, and even.
各種の真空蒸着法の組み合わせ等により形成できる。It can be formed by a combination of various vacuum deposition methods.
［発明の効果］
以上のように本発明によれば、トンネル注入型ＳＩＴと
負荷抵抗を直列接続した集積回路を形成する。ようにし
たので、超高速、低消費電力、低雑音な室温動作で高集
積化可能な半導体集積回路が得られる。[Effects of the Invention] As described above, according to the present invention, an integrated circuit in which a tunnel injection type SIT and a load resistor are connected in series is formed. As a result, it is possible to obtain a semiconductor integrated circuit that is ultra-high speed, has low power consumption, operates at room temperature with low noise, and can be highly integrated.
第１図は本発明の一実施例に係る半導体集積回路の断面
図、第２図はその等価回路、第３図は本発明の他の実施
例に係る半導体集積回路の断面図。
第４図はその等価回路である。
１・・・基板、２・・・ ドレ°イン、３・・・チャン
ネル、５・・・ ソース、４，５・・・ トンネル注入
領域、６・・・ゲート、２０・・・入力端子、２１・・
・接地端子。
２２・・・出力端子、２３・・・１！源端子。
第１図
第２図FIG. 1 is a cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is an equivalent circuit thereof, and FIG. 3 is a cross-sectional view of a semiconductor integrated circuit according to another embodiment of the present invention. FIG. 4 shows its equivalent circuit. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Drain, 3... Channel, 5... Source, 4, 5... Tunnel injection region, 6... Gate, 20... Input terminal, 21・・・
・Ground terminal. 22...output terminal, 23...1! source terminal. Figure 1 Figure 2
Claims (4)
の両側に接触して形成されるトンネル注入領域を有する
ソース領域およびドレイン領域と、前記チャンネルの一
部に接触して形成されたゲート領域を具備したトンネル
注入型静電誘導トランジスタのゲートに信号入力端子、
ソースに接地端子、ドレインに出力端子、更にそのドレ
インに抵抗を介して電源端子をそれぞれ設けて集積回路
を構成したことを特徴とする半導体集積回路。(1) A semiconductor region serving as a channel, a source region and a drain region having tunnel injection regions formed in contact with both sides of the channel, and a gate region formed in contact with a part of the channel. A signal input terminal is connected to the gate of the tunnel injection type static induction transistor.
1. A semiconductor integrated circuit characterized in that the integrated circuit is configured by providing a ground terminal at a source, an output terminal at a drain, and a power supply terminal at the drain via a resistor.
領域が前記チャンネルよりも禁制帯幅の大きい半導体よ
り形成される半導体集積回路。(2) A semiconductor integrated circuit according to claim 1, wherein the gate region is formed of a semiconductor having a larger forbidden band width than the channel.
、前記抵抗をノーマリオン型のトランジスタより形成し
て成る半導体集積回路。(3) A semiconductor integrated circuit according to claim 1 or 2, wherein the resistor is formed of a normally-on transistor.
、チャンネルがＧａＡｓ、ゲート領域がＧａ＿１＿−＿
ｘＡｌ＿ｘＡｓないしはＧａ＿１＿−＿ｘＡｌ＿ｘＡｓ
＿１＿−＿ｙＰ＿ｙで形成されて成る半導体集積回路。(4) In claim 2 or 3, the channel is made of GaAs and the gate region is made of Ga_1_-_
xAl_xAs or Ga_1_-_xAl_xAs
A semiconductor integrated circuit formed of _1_-_yP_y.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59180447A JPH0614535B2 (en) | 1984-08-31 | 1984-08-31 | Semiconductor integrated circuit |
| GB08519851A GB2163002B (en) | 1984-08-08 | 1985-08-07 | Tunnel injection static induction transistor and its integrated circuit |
| FR858512117A FR2569056B1 (en) | 1984-08-08 | 1985-08-07 | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
| DE19853528562 DE3528562A1 (en) | 1984-08-08 | 1985-08-08 | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND COMPREHENSIVE INTEGRATED CIRCUIT |
| GB08723051A GB2194677B (en) | 1984-08-08 | 1987-10-01 | Tunnel injection static induction transistor integrated circuit |
| US07/147,656 US4870469A (en) | 1984-08-08 | 1988-01-25 | Tunnel injection type static transistor and its integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59180447A JPH0614535B2 (en) | 1984-08-31 | 1984-08-31 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6159877A true JPS6159877A (en) | 1986-03-27 |
| JPH0614535B2 JPH0614535B2 (en) | 1994-02-23 |
Family
ID=16083387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59180447A Expired - Lifetime JPH0614535B2 (en) | 1984-08-08 | 1984-08-31 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0614535B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411774A (en) * | 1987-07-06 | 1989-01-17 | Honda Motor Co Ltd | Running gear |
| JP2013220016A (en) * | 2012-04-05 | 2013-10-24 | Samsung Electronics Co Ltd | High side gate driver, switching chip, and power device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57186374A (en) * | 1981-05-12 | 1982-11-16 | Semiconductor Res Found | Tunnel injection type travelling time effect semiconductor device |
-
1984
- 1984-08-31 JP JP59180447A patent/JPH0614535B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57186374A (en) * | 1981-05-12 | 1982-11-16 | Semiconductor Res Found | Tunnel injection type travelling time effect semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411774A (en) * | 1987-07-06 | 1989-01-17 | Honda Motor Co Ltd | Running gear |
| JP2013220016A (en) * | 2012-04-05 | 2013-10-24 | Samsung Electronics Co Ltd | High side gate driver, switching chip, and power device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0614535B2 (en) | 1994-02-23 |
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