JPH0614271A - Pulse generator - Google Patents

Abstract

PURPOSE:To arbitrarily set the charge storage time of a solid image pickup element by a simple circuit constitution. CONSTITUTION:This device is equipped with a first pulse generating circuit 50 constituted of a horizontal counter control circuit 6, horizontal counter 7, and horizontal decoder 8, an SSUB pulse control circuit 9, a second pulse generating circuit 60 constituted of an SUB counter control circuit 10 and an SUB counter 11, and an SUB pulse control circuit 12. The first pulse generating circuit 50 generates an SSUB pulse (d) at every horizontal retrace blanking period based on a horizontal synchronizing signal (b). The SSUB pulse control circuit 9 outputs the SSUB pulse (d) as an output pulse (e) for a prescribed period of time based on a control signal (c). The second pulse generating circuit 60 detects the edge of the control signal (c) in each vertical retrace blanking period, and generates an output pulse (g) at the detection timing. The SUB pulse control circuit 12 composes the output pulse (e) and the output pulse (g), and outputs an SUB pulse (h).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator for driving a solid-state image pickup device.

[0002]

2. Description of the Related Art Recently, video cameras and surveillance cameras are
The focus of development is on small size, light weight, high functionality, and low price. A video camera, a surveillance camera, etc. have a built-in solid-state image sensor (CCD), and this solid-state image sensor is driven by a pulse generator.

This conventional pulse generator for driving a solid-state image sensor will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a conventional pulse generator. As shown in FIG. 3, the conventional pulse generator includes a counter control circuit 100, a counter 200, a decoder 300, and a SU.
And a B pulse control circuit 400. The horizontal synchronizing signal B is input to the counter control circuit 100. The SUB pulse control circuit 400 has a control signal C from an external microcomputer or the like and an output pulse D of the decoder 300 (hereinafter referred to as “SS
UB pulse ”. ) Is entered, which causes SU
The B pulse control circuit 400 outputs a pulse E for driving the solid-state image sensor (hereinafter, referred to as “SUB pulse”).

The operation of the conventional pulse generator thus constructed will be described with reference to FIG. FIG. 4 is a timing chart showing each signal waveform of the conventional pulse generator. In FIG. 4, (a) is a composite blanking signal which is one of the television signals, (b) is a horizontal synchronizing signal B, (c) is a control signal C, (d) is an SSUB pulse D,
(E) shows a SUB pulse E, and (f) shows one of four-phase pulses (hereinafter referred to as “φV pulse”) applied to the CCD for vertical transfer of the solid-state image sensor. The vertical direction is voltage level, and the horizontal direction is time.

Each time the high level of the horizontal synchronizing signal B is input to the counter control circuit 100, the counter 200
Operates and outputs the output value of the counter 200 to the decoder 30.
By decoding with 0, the SSUB pulse D is output from the decoder 300 to the SUB pulse control circuit 400. Further, a control signal C is input to the SUB pulse control circuit 400 from the outside. In the SUB pulse control circuit 400 to which the SSUB pulse D and the control signal C have been input, the SUB pulse E is output by performing a logical operation of the logical product with respect to the SSUB pulse D and the control signal C.

In this way, the SUB pulse E output from the pulse generator is converted into a voltage signal of Vp-p = about 20 [V] through a booster circuit (not shown) and the like, and a solid-state image pickup device (not shown). ) Is applied to the substrate constituting the substrate. Hig
When the voltage signal of the h level is applied, the electric charge accumulated in the photodiode constituting the solid-state image sensor is discharged to the substrate.

Then, when viewed in the time axis direction, the SUB pulse E
After the high-level voltage signal by the final pulse E1 is applied to the substrate, charge accumulation in the photodiode is started again. This charge accumulation is caused by φV pulse (Fig. 4 (f)
The charge read pulse 5) is applied to the gate of the vertical CCD, and the accumulated charge is transferred from the photodiode to the vertical CCD by the charge read pulse 5 and is output through the charge detector of the horizontal CCD. It

That is, the charge accumulation period is a period from the output of the final pulse E1 of the SUB pulse E to the output of the charge read pulse 5, and the output timing of the final pulse E1 of the SUB pulse E by the control signal C. By setting, the charge accumulation period can be set.
In case of NTSC system, 1/60 second to 1/1600
The charge storage time can be set in 1/16000 second increments within a range of 0 second.

[0009]

However, in the conventional pulse generator configured as described above, the SUB pulses E are output at predetermined intervals, and the charge storage time cannot be set arbitrarily. was there. One of the solutions is to change the application timing of the charge read pulse 5, but in this case, it is necessary to change the application timing of the charge read pulse 5 for each horizontal scanning period, and the circuit configuration is very complicated. There was a problem of becoming.

An object of the present invention is to solve the above problems, and to provide a pulse generator capable of arbitrarily setting the charge storage time of a solid-state image pickup device with a simple circuit configuration.

[0011]

A pulse generator according to the present invention includes a first pulse generating circuit for generating a first pulse for each horizontal blanking period based on a horizontal synchronizing signal of a television signal, and an external circuit. A first pulse control circuit that outputs a first pulse for a predetermined period based on a control signal input from the second pulse generation circuit that detects an edge of the control signal and generates a second pulse at this detection timing. The circuit includes a circuit, and a second pulse control circuit that outputs a combined output pulse of the first pulse control circuit and an output pulse of the second pulse generation circuit.

[0012]

According to the structure of the present invention, the first pulse control circuit outputs the first pulse generated by the first pulse generation circuit for a predetermined period, and the second pulse generation circuit outputs the edge of the control signal. Is detected, and a second pulse is generated by this detection tamming. Then, the output pulse of the first pulse control circuit and the output pulse of the second pulse generation circuit are combined by the second pulse control circuit. Thus, the final pulse of the output pulse of the second pulse control circuit, which is the start point of the charge accumulation period, can be set at the output timing of the second pulse by the second pulse generation circuit. Since the output tamming of the second pulse can be arbitrarily set at the timing of the edge of the control signal, the charge accumulation period can be arbitrarily set by the control signal.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing the configuration of a pulse generator according to an embodiment of the present invention. In FIG. 1, 6 is a horizontal counter control circuit, 7 is a horizontal counter, 8 is a horizontal decoder, 9 is an SSUB pulse control circuit, 10 is a SUB counter control circuit, and 11 is a SUB.
A counter, 12 is a SUB pulse control circuit, b is a horizontal synchronizing signal, c is a control signal, d is an output pulse of the horizontal decoder 8 (hereinafter referred to as "SSUB pulse") which is the first pulse, and e is an SSUB pulse control circuit. 9 output pulses,
g is the output pulse of the SUB counter 11 which is the second pulse, h is the output pulse of the SUB pulse control circuit 12 (hereinafter referred to as “SUB pulse”), i is the vertical blanking signal,
j indicates an output pulse of the SUB counter control circuit 10.

As shown in FIG. 1, the pulse generator includes a first pulse generating circuit 50 including a horizontal counter control circuit 6, a horizontal counter 7 and a horizontal decoder 8 and an SSUB pulse control serving as a first pulse control circuit. Circuit 9 and SU
A second pulse generation circuit 60 including a B counter control circuit 10 and a SUB counter 11 and a SUB pulse control circuit 12 serving as a second pulse control circuit are provided.

The first pulse generation circuit 50 generates an SSUB pulse d for each horizontal blanking period based on the horizontal synchronizing signal b of the television signal. SSUB
The pulse control circuit 9 outputs the SSUB pulse d as an output pulse e for a predetermined period based on a control signal c input from the outside. Second pulse generation circuit 60
Detects the edge of the control signal c during the vertical blanking period,
The output pulse g is generated at this detection timing.

The SUB pulse control circuit 12 combines the output pulse e output from the SSUB pulse control circuit 9 and the output pulse g output from the second pulse generation circuit 60 to obtain S.
The UB pulse h is output. The operation of the pulse generator configured as above will be described with reference to FIGS. 1 and 2.

FIG. 2 is a timing chart showing each signal waveform of the pulse generator according to the embodiment of the present invention. In FIG. 2, (a) is a composite blanking signal which is one of the television signals, (b) is a horizontal synchronizing signal b, (c) is a control signal c, (d) is an SSUB pulse d, and (e). Is an output pulse e of the SSUB pulse control circuit 9, and (f) is a four-phase pulse applied to the vertical transfer CCD of the solid-state image sensor (hereinafter, “φV
"Pulse". ) One pulse, (g) SU
Output pulse of B counter 11, (h) is SUB pulse h
Indicates. The vertical direction is voltage level, and the horizontal direction is time.

Each time the high level of the horizontal synchronizing signal b is input to the counter control circuit 6, the counter 7 operates and the decoder 8 decodes the output value of the counter 7 to convert the SSUB pulse d into the SUB pulse control circuit. Output to 9. A control signal c is input to the SUB pulse control circuit 9 from the outside. In the SUB pulse control circuit 9 to which the SSUB pulse d and the control signal c have been input,
The logical operation of the logical product is executed on the pulse d and the control signal c, and the output pulse e is output.

Further, the SUB counter control circuit 10 detects the falling edge of the control signal c in the vertical blanking period and outputs the detection signal j to the SUB counter 11. As a result, the SUB counter 11 outputs the output pulse g at the timing of detecting the falling edge of the control signal c. S
In the SUB pulse control circuit 12 to which the output pulse e of the SUB pulse control circuit 9 and the output pulse g of the SUB counter 11 are input, the output pulse e and the output pulse g
The logical operation of the logical sum is executed with respect to and the SUB pulse h is output.

The SUB pulse h thus obtained by the pulse generator is converted into a voltage signal of Vp-p = about 20 [V] through a booster circuit (not shown) or the like, and a solid-state image pickup device (not shown). ) Is applied to the substrate. Hi
When a gh level voltage signal is applied, the electric charge accumulated in the photodiode forming the solid-state image sensor is discharged to the substrate.

Then, when viewed in the time axis direction, the SUB pulse h
After the high-level voltage signal by the final pulse h1 is applied to the substrate, the charge accumulation in the photodiode is started again. This charge accumulation is caused by the φV pulse (see FIG.
(f)) is applied until the charge read pulse 13 is applied to the gate of the vertical CCD, and the accumulated charge is transferred from the photodiode to the vertical CC by the charge read pulse 13.
It is transferred to D and output through the charge detector of the horizontal CCD.

That is, the charge accumulation period is a period from the output of the final pulse h1 of the SUB pulse h by the SUB pulse control circuit 12 to the application of the charge read pulse 13 to the gate of the vertical CCD. Therefore, the charge accumulation period can be set at the output timing of the final pulse h1 of the SUB pulse h, the output timing of this final pulse h1 can be set at the output timing of the output pulse g, and the output timing of this output pulse g is It can be set at the timing when c is the falling edge. Since the timing of the falling edge of the control signal c can be set arbitrarily, the charge accumulation period can be set arbitrarily by the control signal c.

By setting the charge storage period by the control signal c in this manner, the charge storage period of the solid-state image pickup device can be arbitrarily set by one control line from the outside.
In the case of the C method, it can be set in the range of 1/60 second to 1 / ∞ second. Thus, according to the embodiment, S
The SUB pulse control circuit 9 includes a first pulse generation circuit 50.
The SSUB pulse d generated by is output as the output pulse e for a predetermined period, the second pulse generation circuit 60 detects the edge of the control signal c, and the output pulse g is generated at this detection timing. Then, the SUB pulse control circuit 1
2 combines the output pulse e of the SSUB pulse control circuit 9 and the output pulse g of the second pulse generation circuit 60 to obtain S
The UB pulse h is output. As a result, the final pulse h1 of the SUB pulse h output from the SUB pulse control circuit 12, which is the start point of the charge accumulation period, can be set at the output timing of the output pulse g of the second pulse generation circuit 60. Since the output timing of the output pulse g can be arbitrarily set at the timing of the edge of the control signal c, the charge accumulation period can be arbitrarily set by the control signal c.

As a result, it is possible to obtain a pulse generator having a simple circuit structure and capable of arbitrarily setting the charge storage time of the solid-state image pickup device. Also, during the vertical blanking period, SU
By applying the B pulse h, noise generation can be prevented. Applying the SUB pulse h during the video period causes noise.

Further, the counter 7 and the SUB counter 1
1 is configured separately, but this is normally a counter 7
This is because not only the SUB pulse but also other solid-state image pickup element driving pulses are generated in timing, so that they cannot be freely operated. In this embodiment, the SUB pulse h is generated when the logic level of the control signal c is High level, but the logic level is arbitrary. Similarly, the logic levels of other signals are also arbitrary.

[0026]

According to the pulse generator of the present invention, the first pulse control circuit outputs the first pulse generated by the first pulse generation circuit for a predetermined period, and the second pulse generation circuit The edge of the control signal is detected, and a second pulse is generated by this detection tamming. Then, the output pulse of the first pulse control circuit and the output pulse of the second pulse generation circuit are combined by the second pulse control circuit. Thus, the final pulse of the output pulse of the second pulse control circuit, which is the start point of the charge accumulation period, can be set at the output timing of the second pulse by the second pulse generation circuit. Since the output tamming of the second pulse can be arbitrarily set at the timing of the edge of the control signal, the charge accumulation period can be arbitrarily set by the control signal.

As a result, it is possible to obtain a pulse generator having a simple circuit structure and capable of arbitrarily setting the charge storage time of the solid-state image pickup element, and its practical effect is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a pulse generator according to an embodiment of the present invention.

FIG. 2 is a timing chart showing each signal waveform of the pulse generator according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional pulse generator.

FIG. 4 is a timing diagram showing each signal waveform of a conventional pulse generator.

[Explanation of symbols]

50 First pulse generation circuit 9 SSUB pulse control circuit (first pulse control circuit) 60 Second pulse generation circuit 12 SUB pulse control circuit (second pulse control circuit) b Horizontal synchronization signal c Control signal d SSUB pulse (First pulse) e Output pulse g Output pulse (second pulse) h SUB pulse

Claims (1)

[Claims] 1. A first pulse generating circuit for generating a first pulse every horizontal blanking period based on a horizontal synchronizing signal of a television signal, and the first pulse generating circuit based on a control signal input from the outside. A first pulse control circuit that outputs the pulse of a predetermined period, a second pulse generation circuit that detects an edge of the control signal and generates a second pulse at this detection timing, and the first pulse control circuit Second output pulse of the second pulse generation circuit and the output pulse of the second pulse generation circuit
Pulse control circuit with the pulse control circuit of.