JPH0614266A - Superimpose device - Google Patents

Abstract

PURPOSE:To obtain a superimpose device at a low cost by which a character or the like can be inserted into the desired area of an input image-just like a telop, and the above mentioned character or the like can be exactly inserted into the desired position of the input image. CONSTITUTION:Character data in plural lines are stored in a memory 16, the above mentioned character is successively read at the desired position of the input image at every line by the signal of a timing generating circuit 26, and synthesized into an input image signal (input video signal) by a superimpose generating circuit 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superimposing apparatus for displaying an image stored in storage means at a desired position of an input image.

[0002]

2. Description of the Related Art Recently, there has been a growing need for an editing technique for editing scenes, inserting titles, and inserting characters' names one by one like a telop when editing a videotape.

The technique of sequentially inserting the names of the characters like a telop can be realized by preparing equipment used in a broadcasting station.

On the other hand, a camera-integrated video tape recorder (hereinafter referred to as a video camera) binarizes an input image signal from the camera unit and stores it in a memory, and then inputs the stored information as an image of an arbitrary color. Many devices have a superimpose function that superimposes on an image.

This superimpose function takes in handwritten pictures and characters from the camera unit, binarizes them, and superimposes them as a title, so that anyone can easily insert a title.

[0006]

However, the equipment used in the broadcasting station is very expensive and difficult to operate, so that it is not easy for anyone to use. There is.

In the superimpose function of the video camera, there is a problem that the stored binarized information can be displayed as only one picture, and the names of the characters are sequentially inserted like a telop. It is not possible.

The present invention has been made in view of the above problems, and provides an inexpensive superimposing device that allows characters or the like to be easily inserted like a telop in a desired area of an input image. That is the purpose.

[0009]

In order to achieve the above-mentioned object, the present invention provides a superimposing device having the following (1),
It is configured as in (2).

(1) storage means for storing image data,
An image data dividing unit that divides the image data of the storage unit according to a plurality of required image areas, and a signal of the input image so that the images of the plurality of image areas are sequentially displayed at desired positions of the input image. A superimposing apparatus comprising: an image data synthesizing unit for sequentially synthesizing the image data segmented by the image data segmenting unit.

(2) The method further comprising: marker signal generating means for generating a marker signal for indicating boundaries of a plurality of image areas; and image data synthesizing means for synthesizing the marker signal with a signal of an input image. ) Superimposing device described.

[0012]

With the configurations (1) and (2) described above, images in a plurality of areas of the image in the storage means are sequentially displayed at desired positions in the input image. In the configuration of (2), the boundaries of the plurality of image areas are indicated by the markers.

[0013]

EXAMPLES The present invention will be described in detail below with reference to examples. (Embodiment 1) FIG. 1 is a block diagram showing the configuration of the "superimposing apparatus" of the first embodiment. In the figure, 10
Is a binarization circuit for binarizing the input video signal 30, 12 is a sync separation circuit for separating a horizontal sync signal (Hsync) and a vertical sync signal (Vsync) from the input video signal, 14
Is an A / D converter for sampling the output of the binarization circuit 10 and converting it to a digital signal, and 16 is a memory (storage means) of n rows × m columns for storing the A / D-converted binarized data. ) And 18 are horizontal sync signals (Hsync) and vertical sync signals (Vsn) output from the sync separation circuit 12.
yc) a clock generation circuit for generating a write clock and a read clock of the memory 16, a row address control circuit 20 for controlling a row address of the memory 16, and a column address control circuit 22 for controlling a column address of the memory 16. , 24 is a superimpose circuit that superimposes the data read from the memory 16 to an input video signal (signal of the input image) as an image of an arbitrary color, and 26 is a control of writing and reading of the memory 16. , And a timing generation circuit for outputting a row address reset signal and a column address reset signal to the row address control circuit 20 and the column address control circuit 22,
Reference numeral 28 is a microcomputer (hereinafter referred to as a microcomputer) that outputs a control signal to the timing generation circuit 26.

Next, the memory 16 consisting of n rows × m columns is
B1 = k1 rows × m columns, B2 = k2 rows × m columns, ... Bi =
The operation in the case of dividing into i blocks of ki rows × m columns (where k1 + k2 + ... + ki ≦ n) and sequentially performing superimpose will be described.

First, the write operation will be described. The clock generation circuit 18 generates a write clock for the memory 16 and a sampling clock for sampling in the A / D converter 14 in synchronization with the horizontal synchronization signal (Hsync) output from the synchronization separation circuit 12. At this time,
The memory 16 can be effectively used by determining the clock frequency so that the video signal portion in one horizontal period corresponds to one row of the memory.

The column address control circuit 22 generates a column address control signal from the clock signal output from the clock generation circuit 18 and the column address reset signal output from the timing generation circuit 26, and outputs the column address control signal to the memory 16. To do. In addition, the row address control circuit 20
Then, the horizontal sync signal (H
sync) and a row address reset signal which is an output signal of the timing generation circuit 26, and generates a row address control signal and outputs it to the memory 16.

As shown in FIG. 2, when a subject is photographed by a video camera or the like, the input video signal is a binarization circuit 10.
After being binarized in, the data is input to the A / D converter 14, sampled by the sampling clock output from the clock generation circuit 18, and quantized to be digital data. Next, this digital data is sequentially stored in the address designated by the column address control signal and the row address control signal of the memory 16 of n rows × m columns. In this way, the binarized data of the input video signal is stored in the memory 16 for one field.

Next, the read operation will be described. n rows x
When the data stored in the memory 16 of m columns is divided into i blocks of B1 = k1 rows × m columns, B2 = k2 rows × m columns, ... Bi = ki rows × m columns (see FIG. 3) ), In order to superimpose the data of each block to a predetermined position of the input video signal, the timing of the row address reset signal input to the row address control circuit 20 is set as follows (see FIG. 4). ).

R1 = S-k1-α R2 = S- (k1 + k2) -α: Ri = S- (k1 + k2 + ... + ki) -α S: Number of scanning lines (NTSC ... 262.5) (PAL ... 312) .5) α: Offset value for superimposing at a predetermined position of the input video signal. A mask signal for preventing an extra signal from appearing on the screen is M1 = S−k1−α to S. Other than -α section M2 = S-k2-α to other than S-α section: Mi = S-ki-α to S-α Other than the section, the mask signal is set in the timing generation circuit 26. Then, row address reset signals (R1, R2, ... Ri), mask signals (M1, M2,
...... Set to output Mi) sequentially at predetermined time intervals.

First, the case of superimposing the data of the B1 block (see FIG. 3) will be described. The row address reset signal is input to the memory 16 at the position of the scanning line of R1 = S-k1-α of the input video signal, and the reading is started from this position. Further, since the mask signal is output from the read position of the memory except the section of k1, only the signal of the B1 block of the memory is output to the superimpose circuit 24 and superimposed on the input video signal.

Next, when a control signal is output from the microcomputer 28 after the lapse of a predetermined time, the row address reset signal output from the timing generation circuit 26 is scanned by R2 = S- (k1 + k2) -α of the input video signal. The line position is set (see FIG. 5). On the other hand, the mask signal is K2 from the position where the data of the block B2 of the memory is read.
Since it is output in a section other than the section, only the signal of the B2 block of the memory is output to the superimposing circuit 24 and superimposed on the input video signal. Similarly, B3
The data up to the block ... Bi block is sequentially output and superimposed on the input video signal.

By setting the row address reset signal and the mask signal output from the timing generation circuit 26 as described above, the data of each block divided into i pieces from the memory 16 (corresponding to i image areas) Image data) to be output at a predetermined time interval in the order of B1, B2, ... Bi, and the superimpose generation circuit 24
In, in a predetermined position (S-α) of the input video signal (signal of the input image), that is, in the lateral direction, the images can be combined (superimposed).

(Embodiment 2) In Embodiment 1, the memory 16 consisting of n rows × m columns is provided with k1 rows × m columns, k2 rows × m columns, ...
… Ki rows × m columns (where k1 + k2 + …… + ki ≦
In the above, the case of dividing into i blocks of n) and sequentially superimposing at the set position of the input video signal has been described. However, the row address reset signal output from the timing generation circuit 26 and the value of α of the mask signal Is incremented or decremented by one every predetermined time, the data of each block is changed to B1, B2, ... B.
In the order of i, superimposing can be performed while scrolling to the input video signal at predetermined time intervals.

(Embodiment 3) In Embodiments 1 and 2, n
The memory 16 consisting of rows × m columns is stored in k1 rows × m columns, k2 rows × m columns, ... Ki rows × m columns (where k1 + k2 + ...
Although a case has been described in which the blocks are divided into blocks of + ki ≦ n) and sequentially superimposed, the memory 16 consisting of n rows × m columns is divided into n rows × j1 columns, n rows × j2 columns, ... N rows × ji. It is also possible to divide into i blocks in a column (where j1 + j2 + ... ji ≦ m) and perform superimposing sequentially.

In this case, the column address control circuit 2
The timing of the column address reset signal input to 2 is set as follows.

R1 = m-j1-α R2 = m- (j1 + j2) -α: Ri = m- (j1 + j2 + ... + ji) -α α: Offset value for superimposing at a predetermined position of the input video signal Further, a mask signal for preventing an unnecessary signal from appearing on the screen is set as follows: M1 = m-j1-α to m-α other than section M2 = m-j2-α to m-α other than section: Mi = m The mask signal is set in the timing generation circuit 26 so as to be output except in the section from -ji-α to m-α. Then, column address reset signals (R1, R2, ... Ri) and mask signals (M1, M2,
...... Set to output Mi) sequentially at predetermined time intervals.

By setting the column address reset signal and the mask signal output from the timing generation circuit 26 as described above, the data of each block divided into i pieces from the memory 16 is B1, B2, ... Bi
In the superimpose generation circuit 24, superimposing is performed at a predetermined position (m-α) of the input video signal (input image signal), that is, in the vertical direction. You can

(Embodiment 4) Even in the case of Embodiment 3,
Similar to the second embodiment, the value of α is increased or decreased one by one at every predetermined time so that the data of each block is in the order of B1, B2, ... Bi at every predetermined time. You can superimpose while scrolling to the input video signal.

(Embodiment 5) In each of the above embodiments, the image data is divided into i blocks and sequentially superimposed. However, in this method, although the memory is divided into i blocks, the positions of the i blocks are not known when the subject is photographed and captured in the memory. There is a problem that the photographer does not know at which position on the screen the user is looking at. For example, as shown in FIG. 6, when the characters of the subject are written with a slight shift to the upper part of the memory when stored in the memory, only a part of the character is stored in each block of the memory, so that the superimposing is performed. When you do, the characters will be strange.

The present embodiment further solves such a problem. FIG. 7 is a block diagram of this embodiment.

In FIG. 7, 10 is a binarizing circuit for binarizing the input video signal 30, and 12 is a horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsyn) from the input video signal.
a sync separation circuit for separating c), 14 is the binarization circuit 1
An A / D converter for sampling the output of 0 and converting it into a digital signal, 16 a memory of n rows × m columns for storing A / D-converted binarized data, and 18 of the sync separation circuit 12. A clock generation circuit that generates a write clock and a read clock of the memory 16 from a horizontal synchronization signal (Hsync) and a vertical synchronization signal (Vsync) that are outputs, 20 is a row address generation circuit that controls a row address of the memory 16, 22 Is a column address generation circuit for controlling the column address of the memory 16, 23 is a switch for turning off the data read from the memory 16 when not in the mask section or superimposing, and 24-1 is the memory From the data read from 16, superimpose on the input video signal as an image of any color The first of the superimposed circuit, 26
Is a timing generation circuit that controls writing and reading of the memory 16 and outputs a row address reset signal and a column address reset signal to the row address generation circuit 20 and the column address generation circuit 22, and 28 is a control signal to the timing generation circuit 26. A microcomputer that outputs
Reference numeral 8 is a marker generation circuit that creates a marker signal 54 for indicating the boundary of each block from the row address reset signal and the column address reset signal output from the timing generation circuit 26, and 6 is the marker generation circuit 8 described above.
Is a second superimposing circuit for superimposing the output signal of the input signal on the input video signal, and 4 is an electronic viewfinder (EVF).

Next, the operation of this embodiment will be described with reference to a memory having n rows × m columns, B1 = k1 rows × m columns, B2 = k2 rows ×
m columns, ..., Bi = ki rows × m columns (k1 + k2 + ... k
A case will be described in which the blocks are divided into i blocks of i ≦ n) and the superimposing is sequentially performed.

When the memory 16 of n rows × m columns is set to be divided into i blocks of B1 = k1 rows × m columns, B2 = k2 rows × m columns, ... Bi = ki rows × m columns , Markers indicating the boundaries of the respective blocks are k1, k2, and k2 in the video signal section of the input video signal, as shown in FIG.
......, Ki Generates a pulse that becomes high level only for one horizontal synchronizing signal section for each horizontal synchronizing signal section, and synthesizes (superimposes) the input video signal in the second superimposing circuit 6 to obtain an electronic viewfinder. Display on 4. As shown in FIG. 9, the photographer moves the camera while looking at the markers 56 displayed on the electronic viewfinder 4 so that the characters of the subject are between the markers 56, and then takes in the characters into the memory 16. Memory 1
Since the characters captured in 6 are captured in substantially the center of each block, the characters superimposed when the blocks are sequentially read can be arranged neatly. The operation of the first superimposing circuit 24-1 is the same as that of the first embodiment, and the description thereof is omitted here.

In each of the above embodiments, the binarized data is combined with the input image data. However, the present invention is not limited to this, and the multivalued data may be combined. it can.

In each of the embodiments, an image signal is input, stored in the storage means, and combined. However, the invention is not limited to this, and the image data stored in advance in a memory card or the like is used for combination. It can also be implemented.

[0036]

As described above, according to the present invention,
The image data stored in the storage means is divided according to the plurality of image areas, and the input image signal is combined so that the images of the plurality of image areas are sequentially displayed at desired positions of the input image. Thus, it is possible to provide an inexpensive superimposing device in which characters or the like can be easily inserted into a desired position of an input image like a telop. According to the second aspect of the present invention, it is possible to further insert a marker at the boundary of the plurality of image areas, and it is possible to accurately capture an image such as a character stored in the storage means.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is an explanatory diagram when storing an input image signal in a memory.

FIG. 3 is an explanatory diagram for dividing the image data in the memory into a plurality of blocks.

FIG. 4 is an explanatory diagram (1) of superimpose in the first embodiment.

FIG. 5 is an explanatory diagram of the superimpose in the first embodiment (part 2).

FIG. 6 is an explanatory diagram of Example 5.

FIG. 7 is a block diagram of a fifth embodiment.

[Fig. 8] Time chart of input video signal and marker signal

[Figure 9] Diagram showing how to use markers

[Explanation of symbols]

 16 memory (storing means) 24 superimpose generation circuit 26 timing generation circuit 28 microcomputer

Claims (2)

[Claims] 1. Storage means for storing image data, image data dividing means for dividing the image data of the storage means according to a plurality of required image areas, and the plurality of image areas at desired positions of an input image. Image data synthesizing means for sequentially synthesizing the image data segmented by the image data segmenting means with the signal of the input image so that the images are sequentially displayed. 2. A marker signal generating means for generating a marker signal for indicating a boundary between a plurality of image areas, and an image data combining means for combining the marker signal with a signal of an input image. The superimposing device according to claim 1.