JPH06140909A - Output driver circuit - Google Patents

Abstract

PURPOSE:To provide the output driver circuit in which power noise is reduced with simple circuit configuration. CONSTITUTION:The output driver circuit has an output buffer 100 of CMOS configuration comprising MOSFETs 111, 112 and is provided with a timing control circuit 140 controlling on/off of the two MOSFETs 111, 112. AMOSFET 121 is connected to an output section 131 of the output buffer 100 and the output driver circuit is provided with an additional MOS control circuit 150 controlling on/off of the MOSFET 121. A power supply voltage Vref lower than the power supply voltage VDD is given to the M0SFET121 and outputs the voltage V,., just before the leading and the trailing of the output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output driver circuit of a semiconductor integrated circuit, and more particularly to an output driver circuit having a CMOS output buffer.

[0002]

2. Description of the Related Art Conventionally, an output driver circuit is required to have a higher driving capability as an interface circuit used for connection between devices and the like, and is designed to meet the demand. . However, due to the high drive capacity, troubles such as power supply noise may occur in other circuits inside the device.
It is described in Japanese Patent Application Laid-Open No. 64-27092.

The output driver circuit proposed here includes a timing control circuit 540, as shown in FIG.
A delay circuit 511 delays the input pulse DATA to form output buffers 201 and 202.
By sequentially turning on or off T211, 212, 213, and 214, it is intended to make the rise and fall of the driver output OUTPUT dull. This reduces the dI / dt of the driver output to take measures against troubles such as power supply noise.

[0004]

However, if such a circuit structure is adopted, not only the control of the divided output section becomes complicated, but also the circuit for this control becomes large in scale, and the circuit becomes large. It was a big obstacle to the miniaturization of the whole.

The present invention has been made to solve such a problem, and an object thereof is to reduce such power supply noise with a simple circuit configuration.

[0006]

An output driver circuit according to the present invention is a CMO in which a P-channel MOS transistor and an N-channel MOS transistor are connected in a complementary manner.
An output buffer having an S configuration and an additional MOS transistor connected to the output section of the output buffer and having a power supply voltage set to a value lower than the power supply voltage of the output buffer are provided.

Further, it has a timing control circuit for controlling the two MOS transistors forming the output buffer. In this timing control circuit, when the input pulse given from the outside changes, on-off control is performed on one of the two MOS transistors of the output buffer with a preset timing shift according to the direction of the change. When the input pulse changes, the two MOS transistors forming the output buffer are both turned off for a certain period.

Further, an additional MOS control circuit for turning on the additional MOS transistor at the timing formed by the timing control circuit is provided.

[0009]

When the input pulse changes, the timing control circuit forms a state in which, in accordance with the direction of this change, the two MOS transistors of the CMOS structure that form the output buffer are both turned off for a certain period. When the additional MOS transistor is turned on at the timing when both are turned off, the power supply voltage of the additional MOS transistor is output from the output buffer only during this period.

Accordingly, the two MOS transistors of the output buffer are both turned off by the timing control circuit, and the additional MOS control circuit turns on the additional MOS transistor at this timing. By such control, the output of the additional MOS transistor is given to the output terminal of the output buffer immediately before the rising and falling of the output of the output buffer, and the output buffer of the CMOS structure is provided immediately after the additional MOS transistor is turned off. Turns on.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an output driver circuit according to this embodiment.
It shows in (a). This output driver circuit has two MOS
The output buffer 100 has a CMOS structure in which FETs 111 and 112 are connected in a complementary manner.
A timing control circuit 140 for on / off controlling the 111 and 112 is provided. Also, this output buffer 100
The output section 131 of the
121 is connected to the additional MOS control circuit 150 according to the timing formed by the timing control circuit 140.
The on / off control of the MOSFET 121 is performed by.

The output buffer 100 uses V _DD as a power supply voltage.
Since one MOSFET 111 is a P-channel type, it is off when its gate input is high and on when its gate input is low. Also, the other MOSFE
Since T112 is an N-channel type, it is on when its gate input is high and off when its gate input is low.

The MOSFET 121 is a P-channel type, and the supplied power supply voltage V _ref is set to an intermediate voltage value between the power supply voltage V _DD and GND of the output buffer 100, and this voltage is externally or internally applied. Has been given.

The timing control circuit 140 branches a given input pulse A, one directly and the other directly in the delay circuit 1.
41 through a NAND gate 142 and a NOR gate, respectively.
This NAND gate 1 is provided to the gate 143.
The output C of 42 is given to the gate of the MOSFET 111, and the output D of the NOR gate 143 is given to the MOSFET 112.
Given to the gate of.

The additional MOS control circuit 150 uses the Ex-NO
The NAND gate 142 is composed of the R gate 151.
2 and the output D of the NOR gate 143 are given. Therefore, when one of the outputs C and D is high and the other is low, the output E of the Ex-NOR gate 151 is low, and when the values of the outputs C and D are at the same level, the output E is high. Becomes The output of the Ex-NOR gate 151 is given to the gate of the MOSFET 121.

The operation of the output driver circuit thus constructed will be described. As an output control signal of this output driver circuit, an input pulse A as shown in FIG. 1B is input.

First, the input pulse A is input to the timing control circuit 140. Here, NAND gate 1
The input pulse A is directly applied to one input of 42, and the output B delayed by t ₁ time is applied to the other input of the delay circuit 141. The two signals are also applied in parallel to the NOR gate 143.

Therefore, first, the NOR gate 143 is
At the timing of the rising edge a ₁ of the input pulse A, its output D changes from high to low. And the NAND gate 14
2 has its output C changed from high to low by the rise a _{2 of the} output B delayed by t ₁ time from the rise a ₁ of this input pulse A. Therefore, the NAND gate 14
The output C of 2 changes to low with a delay of t ₁ time from the output D of the NOR gate 143. Therefore, during this t ₁ time, the P-channel type MOS whose input is high
The FET 111 is off, and the N-channel type MOSFET 112 whose input is low is also off. Therefore, the output from the output buffer 100 is in a high impedance state.

On the other hand, E to which the same outputs C and D are given
Thus, the output E of the x-NOR gate 151 changes to low only during the period in which the values of the outputs C and D are different from each other, that is, during the time t ₁ . MOSFET receiving this output E
The 121 is turned on only for this t ₁ time. At this time, since the MOSFET 112 is in the off state, the MOS
The power supply voltage V _{ref of the} FET 121 is given to the load capacitance 132 of the output unit 131, and as a result, the output buffer 100
The voltage V _ref lower than the power supply voltage V _{DD of}
For t ₁ hours.

After the elapse of this t ₁ time, the outputs C and D become low with respect to each other, so that the output E of the Ex-NOR gate 151 becomes high, which causes the MOSFET 121.
Is turned off. At the same time, since the outputs C and D are both low, the MOSFET 112 is in the off state and the MOSFET 111 is in the on state, and the power supply voltage V _DD is given to the load capacitance 132 and output from the output unit 131.

Further, at the falling edge a ₃ of the input pulse A, this signal is delayed by the delay circuit 141 for t ₂ (= t ₁ ) time. Therefore, the NAND pulse is generated at the same timing as the falling edge a ₃ of the input pulse A. the output C of the gate 142 changes from low to high, the output D of NOR gate 143 changes from low to high with a delay of t ₂ hours. Therefore, during this period, the output C is high and thus the MOSFET 111 is off, and the output D is low, so that the MOSFET 112 is also off. Therefore, the output from the output buffer 100 is in a high impedance state.

On the other hand, E to which the same outputs C and D are given
x-NOR gate 151 is thus output C, different periods of D of one another, only during the words t ₂ hours, its output E is changed to the low. MOSFET receiving this output E
The 121 is in the ON state for this t ₂ hours. At this time, since the MOSFET 112 is in the off state, the MOS
The power supply voltage V _{ref of the} FET 121 is given to the load capacitance 132 of the output unit 131, and as a result, the output buffer 100
The voltage V _ref lower than the power supply voltage V _{DD of}
For t ₂ hours.

After the elapse of this t ₂ time, the outputs C and D both become high, so that the output E of the Ex-NOR gate 151 becomes high, which turns off the MOSFET 121. At the same time, since the outputs C and D are high, the MOSFET 111 is in the off state and the MO
The SFET 112 is turned on. Therefore, load capacity 1
The charge stored in 32 is the MOSFET 112.
Is discharged through the output terminal 131 and the output part 131 becomes the same potential as GND.

As described above, the output driver circuit is as shown in FIG.
As in the waveform indicated by “OUT” in (b), the voltage V _ref having a value lower than the voltage V _DD can be output immediately before the rising and falling of the output. In this way, since the output voltage is changed in two steps, the amount of change in the voltage can be suppressed to a low level, thereby reducing the amount of charge charged in the load capacitance 132 and reducing the charging / discharging current during switching. You can The value of the power supply voltage V _ref is set to V _DD and GND in order to reduce the potential difference at the time of switching.
, And an intermediate voltage value in between is preferable.

Since the power supply voltage V _ref of the MOSFET 121 shown in this embodiment can be given by changing this value externally, the noise level can be controlled externally.

Further, the MOSFET 121 as the additional MOS shown in this embodiment may be of N-channel type, and in this case, the additional MOS control circuit may be constituted by Ex-OR. Furthermore, this additional MOS
The control circuit and the timing control circuit are not limited to the circuit configuration using the illustrated elements, and can of course be configured using other elements as long as they perform similar circuit operations.

[0028]

As described above, according to the present invention,
An additional MOS transistor whose power supply voltage is set to a value lower than the power supply voltage of the output buffer is connected to the output section of the output buffer, and the timing control circuit and the additional MOS control circuit are used to rise and rise the output of the output buffer. A circuit is constructed in which the output of the additional MOS transistor is applied to the output terminal of the output buffer immediately before the fall.

Therefore, since the output voltage applied to the output terminal can be increased / decreased in two steps with such a simple circuit configuration, the amount of change in the charging / discharging current per unit time at the time of switching is reduced. This makes it possible to reduce power supply noise caused by the rapid change in the charge / discharge current.

[Brief description of drawings]

FIG. 1A is a circuit configuration diagram showing an output driver circuit according to the present invention, and FIG. 1B is a timing chart showing the operation of the output driver circuit.

FIG. 2 is a circuit configuration diagram showing an example of a conventional noise reduction type output driver circuit.

[Explanation of symbols]

100 ... Output buffer, 111, 112 ... MOSFE
T, 121 ... MOSFET (additional MOS), 131 ... Output unit, 140 ... Timing control circuit, 150 ... Addition MO
S control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 Z 8941-5J

Claims (1)

[Claims] 1. A CM in which a P-channel MOS transistor and an N-channel MOS transistor are connected in a complementary form.
An output buffer having an OS configuration, an additional MOS transistor connected to the output section of the output buffer and having a power supply voltage set to a value lower than the power supply voltage of the output buffer, and a change of an externally applied input pulse Sometimes, depending on the direction of this change, the two MOs that make up the output buffer are
One of the S transistors is on-off controlled with a preset timing shift, and when the input pulse changes, a timing is formed in which two MOS transistors forming the output buffer are both turned off for a certain period. An output driver circuit comprising a timing control circuit and an additional MOS control circuit for turning on the additional MOS transistor at a timing formed by the timing control circuit.