JPH06140637A - Field effect transistor - Google Patents

Abstract

PURPOSE:To provide a field effect transistor whose high frequency characteristics are superior even in low current situations. CONSTITUTION:A source electrode 3 and a drain electrode 4 are created on a substrate 1 made of GaAs having semi-insulating characteristics. A number of multilayer bodies having a fine line structure 6, 6... in which an operation layer and an insulating layer are formed are formed to extend between the source and drain electrodes 3 and 4. A gate electrode 7 is created at the center of the source and drain electrodes 3 and 4 so as to cross the multilayer bodies 6, 6... at right angles.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having excellent high frequency characteristics even at low current.

[0002]

2. Description of the Related Art FIG. 1 is a schematic sectional view showing the structure of a conventional field effect transistor. An operating layer (n layer) 2 is laminated on the entire surface of a substrate 1 made of semi-insulating GaAs, and a source electrode 3 and a drain electrode 4 are formed on the operating layer 2. A gate electrode 5 having a gate length of about 0.5 μm is formed between the source and drain electrodes 3 and 4. In the field effect transistor having such a structure, when a voltage is applied to the gate, the spread of the depletion layer 2a immediately below the gate electrode is controlled, and the source,
The current flowing between the drain electrodes 3 and 4 is determined.

[0003]

FIG. 2 shows a gate-source voltage when a constant voltage is applied to the drain electrode 4 of the field effect transistor shown in FIG. 1 and a negative voltage is gradually applied to the gate electrode 5. 6 is a graph showing the relationship between V _GS and source / drain current I _DS . When the electron concentration of impurities in the operating layer 2 is constant, the square root of the source / drain current I _DS should theoretically decrease linearly as the gate / source voltage V _GS increases, as shown by the broken line in FIG. However, in reality, the decrease is gentle as shown by the solid line. Therefore, in the low current region, the transconductance showing the performance of the field effect transistor is rapidly deteriorated.

The reason for this is as follows. That is, since the operating layer 2 is made of GaAs like the substrate 1, there is no large barrier at the interface between the operating layer 2 and the semi-insulating substrate 1. Therefore, the depletion layer expands as the voltage applied to the gate electrode increases, and the operating layer 2 expands toward the substrate 1 accordingly. That is, when the gate electrode is made larger, the current flows to the substrate side. Such a phenomenon becomes more prominent as the gate length becomes shorter, which is a cause of no effect even if the gate length is shortened in order to improve the performance of the field effect transistor. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a high-performance field-effect transistor by making the operating layer a thin wire structure and reducing the electron concentration of the operating layer on the substrate side. And

[0005]

A field-effect transistor according to the present invention is a field-effect transistor including an operating layer containing an impurity and a source, drain and gate electrodes on a substrate, a part of which is the above-mentioned. An operating layer having a fine line structure extending between the source and drain electrodes is provided, and the operating layer and the gate electrode are in contact with each other only on both sides of the fine line structure portion of the operating layer, and the impurities in the operating layer are included. The concentration is low from the upper side to the substrate side.

[0006]

In the present invention, since the operating layer between the source and the drain has a thin wire structure, the source and drain current flows through this portion. Since the contact between the gate electrode and the operating layer is limited to both sides of the operating layer in the thin wire structure part, the depletion layer that extends to the operating layer and restricts the source / drain current should spread laterally from both sides. Therefore, it is possible to prevent the operating layer from entering the substrate side as in the conventional case. At this time, the impurity concentration in the operating layer is high on the upper side and low on the lower side (substrate side).
Most of the current flows on the upper side, and the current flowing on the substrate side is extremely small. Therefore, even when a high voltage is applied to the gate electrode, the current hardly flows to the substrate side. In addition, since the gate width is the same as that of the conventional structure, excellent high frequency characteristics can be obtained.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 3 is a perspective view showing a field effect transistor according to the present invention. A source electrode 3 and a drain electrode 4 are formed on a substrate 1 made of semi-insulating GaAs. A large number of thin-layer structure laminated bodies 6, 6 ... In which operation layers and insulating layers described later are laminated are formed so as to extend between the source and drain electrodes 3 and 4, and the center between the source and drain electrodes 3 and 4 is formed. A gate electrode 7 is formed in the portion so as to vertically intersect with the stacked bodies 6, 6. In this figure, the longitudinal direction of the source / drain electrodes 3 and 4 is the x-axis direction, the longitudinal direction of the laminate 6 is the y-axis direction, and the thickness direction of each layer is the z-direction.

FIG. 4 is a sectional view (xz) taken along line IV-IV in FIG.
FIG. The laminated body 6 has an insulating layer 62 formed on an operating layer 61, and the operating layer 61 is in contact with the gate electrode 7 only on both side surfaces. In the field effect transistor having such a structure, when a voltage is applied to the gate electrode 7, the depletion layer 61a expands from both side surfaces in contact with the gate electrode 7 toward the center. At this time, the gate electrode 7 in the portion in contact with the insulating layer 62 does not perform any gate operation due to the presence of the insulating layer 62.

FIG. 5 is a graph showing the electron concentration distribution of the operating layer 61 shown in FIG. As shown in FIG. 5, the electron concentration of impurities in the operating layer 61 is high on the upper side (insulating layer 62 side) and low on the lower side (substrate 1 side). Therefore, even when the applied voltage is high, the current hardly flows to the substrate side.

FIG. 6 shows a gate-source voltage V when a constant voltage is applied to the drain electrode 4 of the field effect transistor shown in FIG. 3 and a negative voltage is gradually applied to the gate electrode 7.
₆ is a graph showing the relationship between _GS and the source / drain current I _DS . The decrease in the square root of the source / drain current I _DS is closer to a theoretical linear decrease than in the conventional case.
The pinch-off characteristic is remarkably good. Therefore, the transconductance at a low current is hardly reduced.

Next, a method for manufacturing the device of the present invention having the above-described structure will be described. 7 and 8 are explanatory views showing this step. First, 500 on undoped GaAs substrate 1.
The SiO ₂ film 62a of Å is formed by CVD, the SiO ₂
Si is ion-implanted into the film 62a at an acceleration voltage of 100 KeV and annealed to form the operating layer 61 (FIG. 7A). At this time
Since the through injection is performed on the SiO ₂ film 62a, the GaAs surface (SiO 2
The electron concentration at the interface with the ₂ film 62a is the highest, and is 2 × 10 ¹⁸ cm ⁻³ after annealing. Further, the film thickness of the operating layer 61 defined where the electron concentration becomes 1 / e of the peak concentration is about 1000Å.

Next, the SiO ₂ film 62a in the region where the source and drain electrodes 3 and 4 are formed is removed by RIE (reactive ion etching), and Au + Ge / Ni / Au is deposited to 2000 Å at this position.
Alloying is performed at 450 ° C. to form the source electrode 3 and the drain electrode 4. FIG. 7B shows the yz plane at this time. Here, the distance between the source and drain 3 and 4 electrodes is 1 μm or less in order to reduce the source resistance.

Further, in order to reduce the fringing capacity, which is largely related to the FET characteristics, a 1500 Å SiO ₂ film is further added as a C
An insulating layer 62 is formed by deposition by the VD method (FIG. 7 (c)).
After that, the electron beam negative resist 8 is spin-coated at 5000 Å, and 1000 line / space patterns of 0.2 μm are formed at the formation position of the laminated body 6 by an electron beam with an acceleration voltage of 50 KeV. Figure 8 (d) shows the xz plane (cross section) and x at this time.
-Shows the y-plane (plane). The pattern width of 0.2 μm is about 0.1 μm where the depletion layer can be easily controlled.
It is because

Then, the insulating layer 62 and the operating layer are formed by the RIE method using CF ₄ gas with the electron beam negative resist 8 as a mask.
61 is selectively removed, and the substrate 1 is selectively removed by 2000 Å by the RIE method using a mixed gas of CCl ₂ F ₂ + He with the electron beam negative resist 8 as a mask (FIG. 8E). After removing the electron beam negative resist 8, remove the electron beam positive resist 1
After the spin coating is performed by μm, a pattern of the gate electrode 7 having a gate length of 0.2 μm is formed by an electron beam with an accelerating voltage of 50 KeV. Then, Ti / Al is lifted off to form a gate electrode 7 of 5000 Å, and the remaining electron beam negative resist is removed. The xz plane (cross section) and xy in this case are shown in FIG.
A plane (plane) is shown.

The gate width and fringing capacitance of the field effect transistor manufactured by the above method are calculated as follows. Gate width = 0.1 (operating layer thickness 61) x 2 (both sides) x 1000
(Number) = 200 μm Fringing capacity = 8.85 × 10 ^-12 (ε ₀ ) × 4 (SiO ₂
Ε _r ) × 1000 (number) × 0.2 μm (gate length) × 0.2
μm (fine line dimension) /0.2 μm (insulating layer film thickness) = 7 fF As described above, the gate width is the same as the conventional one, the fringing capacitance is very small, and the high frequency characteristics are good.

[0016]

As described above, the field-effect transistor according to the present invention has a thin wire structure having a large number of operating layers so as to extend between the source and drain electrodes. Since the upper layer is in contact with the electrodes and the electron concentration of the operating layer is higher than that of the substrate side, the present invention has excellent effects such as good high frequency characteristics without decreasing transconductance even at low current. Play.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing the structure of a conventional field effect transistor.

FIG. 2 is a graph showing the relationship between gate-source voltage and source-drain current in the conventional device shown in FIG.

FIG. 3 is a perspective view showing a field effect transistor according to the present invention.

FIG. 4 is a schematic cross-sectional view of the device of the present invention shown in FIG.

FIG. 5 is a graph showing an electron concentration distribution of the n layer shown in FIG.

6 is a graph showing the relationship between gate-source voltage and source-drain current in the device of the present invention shown in FIG.

FIG. 7 is an explanatory view showing a manufacturing process of the device of the present invention shown in FIG.

FIG. 8 is an explanatory view showing a manufacturing process of the device of the present invention shown in FIG.

[Explanation of symbols]

 1 Substrate 2, 61 Operation Layer 3 Source Electrode 4 Drain Electrode 5, 7 Gate Electrode 6 Laminated Body 62 Insulation Layer

Claims (1)

[Claims] 1. A field effect transistor having an operating layer containing impurities, a source, a drain and a gate electrode on a substrate, and an operation having a fine line structure such that a part of the field effect transistor extends between the source and the drain electrodes. A layer, wherein the operating layer and the gate electrode are in contact with each other only on both side surfaces of the thin line structure portion of the operating layer, and the impurity concentration in the operating layer decreases from the upper side to the substrate side. Characteristic field effect transistor.