JPH06140564A - Semiconductor device including electrostatically protecting chip - Google Patents
Semiconductor device including electrostatically protecting chipInfo
- Publication number
- JPH06140564A JPH06140564A JP4290985A JP29098592A JPH06140564A JP H06140564 A JPH06140564 A JP H06140564A JP 4290985 A JP4290985 A JP 4290985A JP 29098592 A JP29098592 A JP 29098592A JP H06140564 A JPH06140564 A JP H06140564A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electrostatic protection
- semiconductor device
- semiconductor chip
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体技術さらには半
導体チップを静電破壊から保護する技術に適用して特に
有効な技術に関し、例えばＤＲＡＭ等の集積回路が形成
された半導体装置の静電保護に利用して有用な技術に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly to a technology which is particularly effective when applied to a technology for protecting a semiconductor chip from electrostatic damage. Related to useful technology for protection.
【０００２】[0002]
【従来の技術】従来より、ＤＲＡＭ等の集積回路が形成
された半導体チップには、これを静電破壊から保護する
ための静電保護回路が設けられている。この静電保護回
路は、一般には、該半導体チップのボンディングパッド
の周辺に形成されて、ボンディングパッドに過大な電圧
が印加されたときに、当該電流をアース等の定電圧電源
側に放電して当該半導体チップ上の素子の静電破壊を防
止するものである。2. Description of the Related Art Conventionally, a semiconductor chip on which an integrated circuit such as a DRAM is formed is provided with an electrostatic protection circuit for protecting it from electrostatic breakdown. This electrostatic protection circuit is generally formed around the bonding pad of the semiconductor chip, and discharges the current to a constant voltage power source side such as ground when an excessive voltage is applied to the bonding pad. This is to prevent electrostatic breakdown of elements on the semiconductor chip.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体チップのように集積回路と同一チップ上に静
電保護回路を設けられていると、発生した静電気やサー
ジ電圧による影響が、当該保護回路の周辺に配置された
他の回路部分に及んでこれを破壊する虞がある。又、集
積回路と同一チップ上に形成された静電保護回路は、あ
る程度の大きさを必要とするため、ＬＳＩチップのアク
ティブエリアが狭まって当該集積回路の高集積化を妨げ
る要因となる。本発明はかかる事情に鑑みてなされたも
ので、ＬＳＩチップの実効面積を小さくすることなく、
静電保護回路機能を半導体装置に設け、静電気やサージ
電圧が印加されたときに集積回路部分にその影響が及ば
ないようにした半導体装置を提供することを目的とす
る。However, when the electrostatic protection circuit is provided on the same chip as the integrated circuit like the above-mentioned conventional semiconductor chip, the influence of the generated static electricity or surge voltage is applied to the protection circuit. There is a possibility that it may damage other circuit parts arranged around the circuit. Further, since the electrostatic protection circuit formed on the same chip as the integrated circuit requires a certain size, the active area of the LSI chip is narrowed, which becomes a factor to prevent high integration of the integrated circuit. The present invention has been made in view of the above circumstances, and it is possible to reduce the effective area of an LSI chip without reducing the effective area.
An object of the present invention is to provide a semiconductor device in which an electrostatic protection circuit function is provided in a semiconductor device so that the integrated circuit portion is not affected when static electricity or a surge voltage is applied.
【０００４】[0004]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を説明すれば、下記のと
おりである。即ち、本発明では半導体チップを実装する
に当たって、静電保護回路を、集積回路が形成された主
半導体チップとは別の半導体チップ上に形成し、主半導
体チップが搭載されるリードフレームの一主面に当該静
電保護用の半導体チップを搭載し、前記主半導体チップ
のボンディングパッドと前記リードフレームの外部ピン
との間を、上記静電保護用チップを介してボンディング
ワイヤのような配線部材にて導電接続させたものであ
る。The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the present invention, in mounting a semiconductor chip, the electrostatic protection circuit is formed on a semiconductor chip different from the main semiconductor chip on which the integrated circuit is formed, and the main part of the lead frame on which the main semiconductor chip is mounted is mounted. A semiconductor chip for electrostatic protection is mounted on the surface, and a wiring member such as a bonding wire is provided between the bonding pad of the main semiconductor chip and the external pin of the lead frame via the electrostatic protection chip. Conductive connection.
【０００５】[0005]
【作用】静電保護回路が主半導体チップから離されてい
るので、静電気やサージ電圧による当該集積回路への影
響がなくなる。又、静電保護回路が別個の半導体チップ
上に形成されているので、主半導体チップのアクティブ
エリアが狭められることなく集積度が向上する。特に、
ＬＳＩチップの上面をリードフレームの下面に接合させ
てこれを支持するようにしたＬＯＣ構造（Lead On Chi
p）に適用した場合には、当該リードフレームの上面に
上記静電保護用のチップを搭載することにより、半導体
装置（パッケージ）全体を大きくすることなく上記２つ
の半導体チップをパッケージに封入することができる。Since the electrostatic protection circuit is separated from the main semiconductor chip, the influence of static electricity or surge voltage on the integrated circuit is eliminated. Further, since the electrostatic protection circuit is formed on a separate semiconductor chip, the degree of integration is improved without narrowing the active area of the main semiconductor chip. In particular,
An LOC structure (Lead On Chi) in which the upper surface of the LSI chip is joined to the lower surface of the lead frame to support the same.
When applied to p), by mounting the chip for electrostatic protection on the upper surface of the lead frame, the two semiconductor chips can be enclosed in the package without enlarging the entire semiconductor device (package). You can
【０００６】[0006]
【実施例】以下、本発明の一実施例を添付図面を参照し
て説明する。図１は本発明に係る静電保護チップとＬＳ
Ｉチップとが搭載された半導体装置の内部構成を示す斜
視図であり、図２はその縦断面図である。尚、これらの
図ではプラスチックモールド前の状態が示されている。
図１，図２に示すように、本実施例の半導体装置１０
は、ＤＲＡＭ等の集積回路が形成されたＬＳＩチップ
（第１の半導体チップ）１、静電保護回路が形成された
静電保護チップ（第２の半導体チップ）２Ａ，２Ｂ、リ
ードフレーム３を具えている。この半導体装置１０は、
ＬＳＩチップ１の上面がリードフレーム３の下面に絶縁
フィルム５を介して接合されてこれに支持された、所謂
リード・オン・チップ構造（以下「ＬＯＣ構造」と称す
る。）となっている。上記静電保護チップ２Ａ，２Ｂ
は、上記リードフレーム３を構成する複数の外部ピン３
１，３２，３３，３４，…の上面にこれらを橋渡しする
ように配設され、絶縁フィルム６を介して接合されてい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows an electrostatic protection chip and an LS according to the present invention.
FIG. 2 is a perspective view showing an internal configuration of a semiconductor device mounted with an I chip, and FIG. 2 is a vertical sectional view thereof. In these figures, the state before plastic molding is shown.
As shown in FIGS. 1 and 2, the semiconductor device 10 of the present embodiment.
Is an LSI chip (first semiconductor chip) 1 on which an integrated circuit such as a DRAM is formed, electrostatic protection chips (second semiconductor chips) 2A and 2B on which an electrostatic protection circuit is formed, and a lead frame 3. I am. This semiconductor device 10 is
The LSI chip 1 has a so-called lead-on-chip structure (hereinafter referred to as “LOC structure”) in which the upper surface of the LSI chip 1 is joined to and supported by the lower surface of the lead frame 3 via an insulating film 5. The electrostatic protection chips 2A, 2B
Is a plurality of external pins 3 that constitute the lead frame 3.
Are arranged on the upper surfaces of 1, 32, 33, 34, ... so as to bridge them, and are joined via an insulating film 6.
【０００７】又、リードフレーム３を構成する信号用外
部ピン３１，３２，…は、その電極部３１ａ，３２ａ，
…がＬＳＩチップ１に設けられた所定のボンディングパ
ッド１１，１２，１３…に、ボンディングワイヤ（配線
部材）４１ａ，４１ｂ，４２ａ，４２ｂ，…にて電気的
に接続されるようになっており、その途中に、静電保護
チップ２Ａ，２Ｂ上に形成された静電保護回路（図中破
線に示す領域に形成されている）２１，２２，２３…が
介在されるようになっている。上記ボンディングワイヤ
４１ａ，４２ａの一端は保護回路の入力端子ＩＮとなる
パッドに、４１ｂ，４２ｂは出力端子ＯＵＴとなるパッ
ドに接続される。尚、静電保護回路は、２つの静電保護
チップ２Ａ，２Ｂに、ＬＳＩチップのパッド数に応じて
所定個数設けられている。ただし、静電保護チップ２
Ａ，２Ｂに、汎用性を持たせるため、上記半導体チップ
のパッド数よりも多い数の静電保護回路を形成しておい
て、これを使用するようにしてもよい。Further, the signal external pins 31, 32, ... Constituting the lead frame 3 have their electrode portions 31a, 32a ,.
Are electrically connected to predetermined bonding pads 11, 12, 13 provided on the LSI chip 1 by bonding wires (wiring members) 41a, 41b, 42a, 42b ,. The electrostatic protection circuits (formed in the regions shown by the broken lines in the figure) 21, 22, 23, ... Formed on the electrostatic protection chips 2A, 2B are interposed in the middle thereof. One ends of the bonding wires 41a and 42a are connected to a pad serving as an input terminal IN of the protection circuit, and 41b and 42b are connected to a pad serving as an output terminal OUT. The electrostatic protection circuits are provided in a predetermined number on the two electrostatic protection chips 2A and 2B according to the number of pads of the LSI chip. However, electrostatic protection chip 2
In order to give versatility to A and 2B, a larger number of electrostatic protection circuits than the pads of the semiconductor chip may be formed and used.
【０００８】上記リードフレームの、定電圧電源Ｖｃｃ
に接続された電源用外部ピン（図示例ではピン３３）
は、ボンディングワイヤ４３ａ，４３ｂにより静電保護
チップ２Ａ，２Ｂに夫々形成されたＶｃｃラインに導電
接続され、このＶｃｃラインによって、全ての静電保護
回路に定電圧Ｖｃｃが供給されるようになっている。ま
た、複数の外部ピンのうち定電圧電源Ｖｓｓに接続され
た外部ピン（ピン３４）は、ボンディングワイヤ４４
ａ，４４ｂにより静電保護チップ２Ａ，２Ｂ上に夫々形
成されたＶｓｓラインに導電接続され、このＶｓｓライ
ンによってアース（Ｖｓｓ）が全ての静電保護回路に接
続されるようになっている。又、チップがｐ形半導体の
場合、定電圧Ｖｓｓはチップ２Ａ，２Ｂの基体にも供給
され、基板電位を与えるようになっている。Constant voltage power supply Vcc of the lead frame
External pin for power supply connected to (pin 33 in the illustrated example)
Is conductively connected to Vcc lines formed on the electrostatic protection chips 2A and 2B by bonding wires 43a and 43b, respectively, and the Vcc line supplies a constant voltage Vcc to all electrostatic protection circuits. There is. Further, among the plurality of external pins, the external pin (pin 34) connected to the constant voltage power supply Vss is the bonding wire 44.
a and 44b are conductively connected to the Vss lines formed on the electrostatic protection chips 2A and 2B, respectively, and the ground (Vss) is connected to all electrostatic protection circuits by the Vss lines. Further, when the chip is a p-type semiconductor, the constant voltage Vss is also supplied to the base bodies of the chips 2A and 2B to give a substrate potential.
【０００９】図３は、静電保護チップに形成された静電
保護回路の一例を示す回路図である。この図に示すよう
に静電保護回路は、ｐ形半導体基板に形成されたｎＭＯ
ＳトランジスタＴｒ１と２つのｐｎｐ形バイポーラトラ
ンジスタＴｒ２，Ｔｒ３にて構成されており、外部ピン
に接続される入力端子ＩＮとＬＳＩチップのパッドに接
続される出力端子ＯＵＴが接続されたノードｎ１には、
ｎＭＯＳトランジスタＴｒ１のドレイン端子が接続され
ている。そしてｎＭＯＳトランジスタＴｒ１のソース端
子とゲート端子は定電圧電源Ｖｓｓに接続されている。
前記ノードｎ１には更に２つのｐｎｐ形トランジスタＴ
ｒ２，Ｔｒ３の一端が接続されている。そして、トラン
ジスタＴｒ２の他端は定電圧電源Ｖｃｃに、トランジス
タＴｒ３の他端は定電圧電源Ｖｓｓに夫々接続されてい
る。尚、図中Ｒ1，Ｒ2，Ｒ3は寄生抵抗である。このよ
うな回路構成を取ることによって、正のサージ電圧が外
部ピン３１又は３２に発生したときには、トランジスタ
Ｔｒ３がオンしてサージ電流が、図１の保護チップ２Ａ
又は２Ｂ、及び外部ピン３４を介して定電圧電源Ｖｓｓ
側に流れ、負のサージ電圧が発生したときにはトランジ
スタＴｒ１，Ｔｒ２がオンしてサージ電流が、外部ピン
３３及び、保護チップ２Ａ又は２Ｂを介して定電圧電源
Ｖｃｃ側から外部ピン３１又は３２へ流れ、半導体チッ
プ上の素子の静電破壊が防止される。FIG. 3 is a circuit diagram showing an example of the electrostatic protection circuit formed on the electrostatic protection chip. As shown in this figure, the electrostatic protection circuit includes an nMO formed on a p-type semiconductor substrate.
A node n1 which is composed of an S transistor Tr1 and two pnp bipolar transistors Tr2 and Tr3, and to which an input terminal IN connected to an external pin and an output terminal OUT connected to a pad of an LSI chip are connected,
The drain terminal of the nMOS transistor Tr1 is connected. The source terminal and the gate terminal of the nMOS transistor Tr1 are connected to the constant voltage power supply Vss.
Two more pnp type transistors T are provided at the node n1.
One ends of r2 and Tr3 are connected. The other end of the transistor Tr2 is connected to the constant voltage power supply Vcc, and the other end of the transistor Tr3 is connected to the constant voltage power supply Vss. In the figure, R1, R2 and R3 are parasitic resistances. By adopting such a circuit configuration, when a positive surge voltage is generated in the external pin 31 or 32, the transistor Tr3 is turned on and a surge current is generated.
Alternatively, a constant voltage power supply Vss is supplied via 2B and the external pin 34.
When a negative surge voltage is generated, the transistors Tr1 and Tr2 are turned on and the surge current flows from the constant voltage power supply Vcc side to the external pin 31 or 32 through the external pin 33 and the protection chip 2A or 2B. Electrostatic breakdown of elements on the semiconductor chip is prevented.
【００１０】尚、上記構成では、ＬＯＣ構造を採用して
いるため、静電保護チップを接続させるためのボンディ
ングワイヤを短くすることが可能であり、入力インピー
ダンスの増加を最低限に抑えることができる。In the above structure, since the LOC structure is adopted, the bonding wire for connecting the electrostatic protection chip can be shortened and the increase in input impedance can be suppressed to the minimum. .
【００１１】以上説明したように本実施例のＬＳＩチッ
プの実装構造では、静電保護回路をＬＳＩチップとは別
個の静電保護チップに形成し、リードフレームとＬＳＩ
チップの間に介在させたので、静電気やサージ電圧によ
る当該ＬＳＩチップ上の回路への影響がなくなる。又、
静電保護回路によってＬＳＩチップのアクティブエリア
が狭められることなく、その集積度が向上する。特に、
ＬＯＣ構造（Lead On Chip）に適用したので、当該リー
ドフレームの上面側に上記静電保護チップを搭載して半
導体装置全体を大きくすることなく２つの半導体チップ
を実装することができる。As described above, in the mounting structure of the LSI chip of this embodiment, the electrostatic protection circuit is formed on an electrostatic protection chip separate from the LSI chip, and the lead frame and the LSI are mounted.
Since it is interposed between the chips, the influence of static electricity or surge voltage on the circuit on the LSI chip is eliminated. or,
The electrostatic protection circuit does not narrow the active area of the LSI chip and improves the degree of integration. In particular,
Since it is applied to the LOC structure (Lead On Chip), two semiconductor chips can be mounted without mounting the electrostatic protection chip on the upper surface side of the lead frame and enlarging the entire semiconductor device.
【００１２】以上本発明者によってなそれた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。例えば、本
実施例では、ＬＳＩチップ、静電保護チップ、リードフ
レームの接続をボンディングワイヤを用いて行ったが、
ＴＡＢ（TAPE AUTOMATED BONDING）を使用することで、
静電保護回路を別チップで形成することに伴う入力容量
の増加を抑えるようにしてもよい。又、本実施例では、
１つの静電保護チップに複数の静電保護回路を形成した
例を示したが、これに限ることなく、唯一つの入力保護
回路が形成されたチップを外部ピン１つ当り又はボンデ
ィングパッド１つ当り、１つ宛設けてもよい。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in this embodiment, the LSI chip, the electrostatic protection chip, and the lead frame were connected using the bonding wire,
By using TAB (TAPE AUTOMATED BONDING),
You may make it suppress the increase of the input capacitance accompanying forming an electrostatic protection circuit by another chip. Also, in this embodiment,
Although an example in which a plurality of electrostatic protection circuits are formed on one electrostatic protection chip has been shown, the present invention is not limited to this, and a chip having only one input protection circuit may be provided for each external pin or bonding pad. You may provide one address.
【００１３】[0013]
【発明の効果】本発明によれば、静電気やサージ電圧の
発生による、ＬＳＩの周辺回路の破壊のおそれがなくな
り、また、ＬＳＩチップの高集積化が図られる。According to the present invention, there is no risk of the peripheral circuits of the LSI being destroyed due to the generation of static electricity or surge voltage, and the LSI chip can be highly integrated.
【図１】本発明に係る静電保護チップとＬＳＩチップと
が搭載された半導体装置の内部構成を示す斜視図であ
る。FIG. 1 is a perspective view showing an internal configuration of a semiconductor device on which an electrostatic protection chip according to the present invention and an LSI chip are mounted.
【図２】図１に示す半導体装置の縦断面図である。FIG. 2 is a vertical sectional view of the semiconductor device shown in FIG.
【図３】静電保護チップに形成された保護回路の回路図
である。FIG. 3 is a circuit diagram of a protection circuit formed on an electrostatic protection chip.
１ ＬＳＩチップ（第１の半導体チップ） ２Ａ，２Ｂ静電保護チップ（第２の半導体チップ） ３ リードフレーム １１，１２，１３ ボンディングパッド ３１，３２，３３，３４ 外部ピン ４１ａ，４１ｂ，４２ａ，４２ｂ ボンディングワイヤ
（配線部材）1 LSI chip (first semiconductor chip) 2A, 2B Electrostatic protection chip (second semiconductor chip) 3 Lead frame 11, 12, 13 Bonding pad 31, 32, 33, 34 External pin 41a, 41b, 42a, 42b Bonding wire (wiring member)
Claims (3)
プと、外部ピンを有し前記第１の半導体チップが搭載さ
れるリードフレームと、前記第１の半導体チップに設け
られたボンディングパッドと前記外部ピンとを導電接続
させる配線部材とを具えてなる半導体装置において、前
記リードフレームには静電保護回路が形成された第２の
半導体チップが搭載され、当該静電保護回路を介して前
記ボンディングパッドと外部ピンとが前記配線部材にて
導電接続されてなることを特徴とする静電保護チップを
具えた半導体装置。1. A first semiconductor chip on which an integrated circuit is formed, a lead frame having external pins on which the first semiconductor chip is mounted, and a bonding pad provided on the first semiconductor chip. In a semiconductor device comprising a wiring member for electrically conductively connecting to the external pin, a second semiconductor chip having an electrostatic protection circuit formed thereon is mounted on the lead frame, and the bonding is performed via the electrostatic protection circuit. A semiconductor device comprising an electrostatic protection chip, wherein a pad and an external pin are conductively connected by the wiring member.
有し、前記静電保護回路は前記外部ピンと同数又はそれ
より多く設けられ、これら複数の静電保護回路は１つの
半導体チップ上に複数個形成されていることを特徴とす
る請求項１に記載の半導体装置。2. The lead frame has a plurality of external pins, the electrostatic protection circuits are provided in the same number as or more than the external pins, and a plurality of these electrostatic protection circuits are provided on one semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is formed.
体チップは夫々前記リードフレームの異なる面に接合さ
れていることを特徴とする請求項１又は２に記載の静電
保護回路を具えた半導体装置。3. The electrostatic protection circuit according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are bonded to different surfaces of the lead frame, respectively. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4290985A JPH06140564A (en) | 1992-10-29 | 1992-10-29 | Semiconductor device including electrostatically protecting chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4290985A JPH06140564A (en) | 1992-10-29 | 1992-10-29 | Semiconductor device including electrostatically protecting chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06140564A true JPH06140564A (en) | 1994-05-20 |
Family
ID=17762974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4290985A Pending JPH06140564A (en) | 1992-10-29 | 1992-10-29 | Semiconductor device including electrostatically protecting chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06140564A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100309525B1 (en) * | 1997-09-12 | 2001-12-17 | 가네꼬 히사시 | Semiconductor device with protection circuit |
-
1992
- 1992-10-29 JP JP4290985A patent/JPH06140564A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100309525B1 (en) * | 1997-09-12 | 2001-12-17 | 가네꼬 히사시 | Semiconductor device with protection circuit |
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