JPH06140525A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06140525A JPH06140525A JP30946492A JP30946492A JPH06140525A JP H06140525 A JPH06140525 A JP H06140525A JP 30946492 A JP30946492 A JP 30946492A JP 30946492 A JP30946492 A JP 30946492A JP H06140525 A JPH06140525 A JP H06140525A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- resin
- metal layer
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に樹脂封止型半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来の半導体装置では、図２に示すよう
に、リードフレーム５のアイランド６上にＡｇペースト
等のマウント材７でチップ３をマウントし、チップ３上
のパッドとリードフレーム５のステッチとをＡｕ等のボ
ンディングワイヤー４で接続した後、樹脂９で封止する
構造が主である。2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 2, a chip 3 is mounted on an island 6 of a lead frame 5 with a mount material 7 such as Ag paste, and the pads on the chip 3 and the lead frame 5 are The main structure is to connect the stitch with a bonding wire 4 such as Au and then seal with a resin 9.
【０００３】[0003]
【発明が解決しようとする課題】従来は、チップ３の下
方部分がＡｇペースト等のマウント材７及びリードフレ
ーム５のアイランド６であり、その周囲を樹脂９で封止
しているため、半導体装置を基板等に実装する際の熱ス
トレスにより、封止樹脂９にクラックが生じたり、チッ
プ３上のカバー膜（パッシベーション膜）にクラックを
生じ、その後の耐湿性強度が低下するという問題があっ
た。Conventionally, since the lower portion of the chip 3 is the mount material 7 such as Ag paste and the island 6 of the lead frame 5 and the periphery thereof is sealed with the resin 9, the semiconductor device. There is a problem that the sealing resin 9 is cracked or the cover film (passivation film) on the chip 3 is cracked due to the thermal stress when mounting the substrate on a substrate or the like, and the moisture resistance strength thereafter is lowered. .
【０００４】そこで、この発明は、封止樹脂にクラック
が生じ難くすることができ、耐湿性強度を向上させるこ
とができる半導体装置を提供することを目的とする。Therefore, an object of the present invention is to provide a semiconductor device in which cracks are unlikely to occur in the encapsulating resin and the moisture resistance strength can be improved.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、本発明による半導体装置は、ＩＣチップに複数のリ
ードを形成し、該ＩＣチップを樹脂封止した半導体装置
において、前記ＩＣチップを金属で囲むとともにこの金
属と前記ＩＣチップとの間を中空にしたものである。In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device in which a plurality of leads are formed on an IC chip, and the IC chip is resin-sealed. It is surrounded by a metal and the space between the metal and the IC chip is hollow.
【０００６】[0006]
【作用】本発明によれば、チップの周囲を中空構造とす
ることで、実装時等に周囲からチップに加わる熱ストレ
スによる応力がなくなり、従来に比べて封止樹脂のクラ
ックやチップ上のカバー膜のクラック等を生じ難くな
る。また、中空部の内側に金属層を設けたことにより、
外部からの水分侵入を防止し、耐湿性強度も向上するこ
ととなる。According to the present invention, by forming a hollow structure around the chip, stress due to thermal stress applied to the chip from the surroundings at the time of mounting is eliminated, and cracks in the sealing resin and the cover on the chip are reduced compared to the conventional case. It is difficult to cause cracks in the film. Also, by providing a metal layer inside the hollow part,
It prevents moisture from entering from the outside and also improves the moisture resistance strength.
【０００７】[0007]
【実施例】本発明の実施例を図１に示す。なお、図２と
同一の部分には、同一の符号を付してその説明を省略す
る。FIG. 1 shows an embodiment of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.
【０００８】図１（ａ）に示すように、ＩＣチップ３の
周囲を中空部８とし、封止樹脂１の内壁にチップ３を四
方から囲むように金属層２を設けることで、外部からの
水分侵入を防止する。チップ３は、図１（ｂ）に示すよ
うに、リードフレーム５の吊りピン部分で支える。この
ような構造とすることにより、実装時等にチップ３へ周
囲から加わる応力が従来に比べて非常に少なくなる。As shown in FIG. 1 (a), a hollow portion 8 is formed around the IC chip 3 and a metal layer 2 is provided on the inner wall of the sealing resin 1 so as to surround the chip 3 from all sides. Prevents ingress of water. The chip 3 is supported by the hanging pin portion of the lead frame 5, as shown in FIG. With such a structure, the stress applied from the periphery to the chip 3 at the time of mounting or the like becomes much smaller than that in the conventional case.
【０００９】[0009]
【発明の効果】以上説明したように本発明によれば、封
止樹脂のクラックやチップ上のカバー膜のクラック等を
生じ難くなり、耐湿性強度が向上する。As described above, according to the present invention, cracks in the sealing resin and the cover film on the chip are less likely to occur, and the moisture resistance strength is improved.
【図１】本発明の一実施例による半導体装置を示す図で
あり、（ａ）はその正面視状態の断面図、（ｂ）はその
側面視状態の断面図である。1A and 1B are views showing a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a sectional view in a front view state and FIG. 1B is a sectional view in a side view state.
【図２】従来の半導体装置の正面視状態の断面図であ
る。FIG. 2 is a sectional view of a conventional semiconductor device in a front view.
１ 封止樹脂 ２ 金属層 ３ ＩＣチップ ４ ボンディングワイヤー ５ リードフレーム（リード） ６ アイランド ７ マウント材 ８ 中空部 1 Sealing Resin 2 Metal Layer 3 IC Chip 4 Bonding Wire 5 Lead Frame (Lead) 6 Island 7 Mount Material 8 Hollow Part
Claims (1)
ＩＣチップを樹脂封止した半導体装置において、 前記ＩＣチップを金属で囲むとともにこの金属と前記Ｉ
Ｃチップとの間を中空にしたことを特徴とする半導体装
置。1. A semiconductor device in which a plurality of leads are formed on an IC chip, and the IC chip is resin-sealed, the IC chip is surrounded by a metal, and the metal and the I
A semiconductor device having a hollow between the C chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30946492A JPH06140525A (en) | 1992-10-23 | 1992-10-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30946492A JPH06140525A (en) | 1992-10-23 | 1992-10-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06140525A true JPH06140525A (en) | 1994-05-20 |
Family
ID=17993311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30946492A Withdrawn JPH06140525A (en) | 1992-10-23 | 1992-10-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06140525A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100448432B1 (en) * | 1997-10-28 | 2004-11-16 | 삼성전자주식회사 | Mold for fabricating air-cavity plastic package to improve reliability and reduce production cost |
| US7192801B2 (en) | 2002-06-26 | 2007-03-20 | Sony Corporation | Printed circuit board and fabrication method thereof |
-
1992
- 1992-10-23 JP JP30946492A patent/JPH06140525A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100448432B1 (en) * | 1997-10-28 | 2004-11-16 | 삼성전자주식회사 | Mold for fabricating air-cavity plastic package to improve reliability and reduce production cost |
| US7192801B2 (en) | 2002-06-26 | 2007-03-20 | Sony Corporation | Printed circuit board and fabrication method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000104 |