JPH06139789A - Shift register - Google Patents

Abstract

PURPOSE:To improve integration while to enable reducing power consumption by transferring held data of first self holding circuit section to a second self holding circuit section. CONSTITUTION:Emitter electrodes of a first and a second transistors(Tr) Q31, Q32 are commonly connected, further, a collector electrode of the Tr Q31 is connected to a base electrode of the Tr Q32, and a first self holding circuit 32 is constituted. Also, emitter electrodes of a third and a forth Tr Q33, Q34 are commonly connected, further, a collector electrode of the Tr Q33 is connected to a base electrode of the Tr Q34, and a second self holding circuit 33 is constituted. And a switching means 34 which switches operation of the circuit 32 and 33 with clock signals CP, ICP applied to bases of differential pair Tr Q35, Q36 is provided. A threshold value VTH is given to bases of the Tr Q31, Q33 in the circuit 32, 33, and an input signal IN is applied to a collector of the Tr Q31 and a commonly connected terminal of the Tr Q33. Thereby, held data of the circuit 32 is transferred to the circuit 33 by a current flowing from a collector of the Tr Q33 to a collector of the Tr Q,32 at the time of transferring data.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIG. 3) Problem to be Solved by the Invention (FIG. 3) Means for Solving the Problem (FIGS. 1 and 2) Action (FIG. 1) Example (FIGS. 1 and 2) ) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register,
In particular, it is suitable for application to a shift register using an emitter coupling logic circuit.

[0003]

2. Description of the Related Art Conventionally, in a signal processing integrated circuit (hereinafter referred to as a signal processing IC) that processes an analog signal, a signal processing mode is set based on various control data output as serial data from a microprocessor. There is a way.

For example, in the case of a vehicle-mounted stereo device, a touch-type input key is used by setting various functions such as tone control and a fader by the serial data and the balance of the volume reproduced by the left and right speakers. The reproduction of the reproduced sound based on the control and the setting information selected by the user immediately before is realized.

At this time, the shift register for receiving the serial data is an essential function for realizing these functions, and its logic circuit is a bipolar IC.
In such a case, it is realized by an emitter coupling logic element (hereinafter referred to as an ECL logic circuit), an IIL (Integrated Injection Logic) circuit, or the like. Here, the shift register constituted by the ECL logic circuit is characterized in that it is very fast as a logic circuit made of silicon and is excellent in coexistence with an analog circuit.

As shown in FIG. 3, this shift register is constructed by cascade connection of two flip-flops FF1 and FF2. The flip-flop FF1 is a transfer gate 2 including a differential pair of transistors Q1 and Q2.
And a latch gate 3 including load resistors R1 and R2 and transistors Q3 and Q4.
Similarly, the flip-flop FF2 includes a transfer gate 12 including a differential pair of transistors Q11 and Q12,
It comprises load resistors R11 and R12 and a latch gate 13 composed of transistors Q13 and Q14.

The operating states of the transfer gates 2 and 12 and the latch gates 3 and 13 are set to the transistors Q5 and Q6.
, And switching gates 4 and 14 formed by a differential pair of Q15 and Q16. A current source 5 is connected to the switching gate 4.

[0008]

However, an EC in which such flip-flops FF1 and FF2 are connected in series is provided.
In a shift register having an L logic circuit configuration, about 24 elements are required for each stage, and for example, when a shift register having 50 stages is configured, about 1200 elements are required, resulting in a very large circuit scale. There was a problem.
Further, when the shift register is configured by an IIL circuit, there is a problem that the processing speed becomes slow, the manufacturing process becomes complicated, and the logic design is difficult.

The present invention has been made in consideration of the above points, and proposes a shift register capable of reducing the number of elements and further reducing the circuit scale while maintaining the conventional high speed and coexistence with an analog circuit. Is what you are trying to do.

[0010]

In order to solve such a problem, in the present invention, the first and second transistors Q are used.
The self-holding circuit portion 32 is formed by connecting the emitter electrodes of 31 and Q32 in common, and connecting the base electrode of the second transistor Q32 to the collector electrode of the first transistor Q31, and to the base electrode of the first transistor Q31. The first and second threshold voltages are received while receiving a predetermined threshold voltage VTH.
A signal input from the common connection end of the collector electrode of the first transistor Q31 and the base electrode of the second transistor Q32 by receiving a predetermined current at a predetermined timing at the common connection end of the emitter electrodes of the transistors Q31 and Q32. IQM (N) is connected to the second transistor Q32
The output is inverted from the collector electrode of.

Further, in the present invention, the first and second transistors Q31 and Q3, to which the emitter electrodes are commonly connected.
And a third self-holding circuit section 32 in which the collector electrode of the first transistor Q31 is connected to the base electrode of the second transistor Q32, and a third and fourth transistor Q33 in which the emitter electrodes are commonly connected. And Q34, and a fourth electrode is formed on the collector electrode of the third transistor Q33.
Second self-holding circuit portion 33 to which the base electrode of the transistor Q34 of
A differential pair of 35 and Q36, each collector electrode of which is connected to the common emitter of the first and second transistors Q31 and Q32 and the common emitter of the third and fourth transistors Q33 and Q34, and is supplied to the base electrode. Switching means 34 for alternately switching the operating states of the first and second self-holding circuit sections 32 and 33 based on the clock signals CP and ICP, and the first and second self-holding circuit sections 32 and 33 are The base electrodes of the first and third transistors Q31 and Q33 receive a predetermined threshold voltage VTH, and an input signal IIN is applied to a common connection terminal of the collector electrode of the first transistor Q31 and the base electrode of the second transistor Q32. When the data is transferred by receiving the data, the second transistor is transferred from the collector electrode of the third transistor Q33. First self-holding circuit portion 32 so as to transfer the data held in the second self holding circuit 33 on the basis of the collector current drawn to the collector electrode of Q32.

Further, in the present invention, the collector electrode is connected to the signal input terminal of the first self-holding circuit portion 32, and the base electrode receives the predetermined input signal IN and the seventh transistor Q51 and the base electrode receive the predetermined input signal IN. The emitter electrode of the eighth transistor Q52 for inputting the threshold voltage VTH is commonly connected, and the input signal IN is input from the collector electrode of the seventh transistor Q51 to the first self-holding circuit section 32.
An inverted signal forming means 53 for outputting an inverted signal IIN which is inverted with respect to the collector electrode, and a collector electrode connected to a common connection end of the emitter electrodes of the seventh and eighth transistors Q51 and Q52 and a first electrode connected to the base electrode. A fifth transistor Q54 for inputting the clock signal CP and a tenth transistor Q53 for commonly inputting a second clock signal ICP to the base and an emitter electrode commonly connected to the ninth transistor Q54. A switching means 52 for ON / OFF controlling the seventh and eighth transistors Q51 and Q52 based on the first and second clock signals CP and ICP, and the seventh and eighth transistors based on the switching operation of the switching means 52. By controlling on / off of Q51 and Q52, the first self-holding circuit from the inverted signal forming means 53. So as to output the inverted signal IIN at a predetermined timing section 32.

[0013]

Operation: First and second transistors Q31 and Q32
And the second self-holding circuit 3 including the third and fourth transistors Q33 and Q34.
3 and the first and second self-holding circuits 32
And a switching circuit 34 that alternately switches the operating states of 33, and when transferring data, the third transistor Q3
The data held by the first self-holding circuit unit 32 is transferred to the second self-holding circuit unit 33 based on the collector current drawn from the collector electrode of the third transistor Q32 to the collector electrode of the second transistor Q32. It is possible to realize the shift register 31 that can be configured with a number of elements less than half that of the conventional one, the degree of integration can be further improved, and the power consumption can be significantly reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 30 denotes an ECL type shift register as a whole, which has a configuration in which shift register stages 31 and 41 each composed of 10 elements are connected in cascade. Here, 1 of the shift register 30
Shift register stages 31 and 4 forming the second stage and the second stage
1 has the same structure. That is, the shift register stage 31 is composed of two sets of latch gates 32 and 33, a switching gate 34, and a constant current source 35, and the shift register stage 41 is composed of two sets of latch gates 42 and 43, a switching gate 44, and a constant current. Source 45
It is composed by.

The shift register stage 31 will be described below. The latch gates 32 and 33 are composed of NPN-type bipolar transistors Q31, Q32 and Q33, Q34 in which the emitters are commonly connected. Here, the bases of the collector-grounded transistors Q32 and Q34 located in the rear of the pair of transistors are connected to the collectors of the base-grounded transistors Q31 and Q33 located in the front, and the connection point and the ground potential (GND). A resistor R31 for generating a logical amplitude between
And R32 are connected.

The latch gate 32 receives the logic output IQM (N) of the inverted input signal IIN and also receives the latch gate 3.
3 inputs the logic output QS (N) of the latch gate 32, and turns on any one of the transistors Q31 and Q32 and Q33 and Q34 based on the comparison result with the threshold voltage VTH input to the bases of the transistors Q31 and Q33. It is designed to switch to the state.

The switching gate 34 is composed of a differential pair of transistors Q35 and Q36, and switches the latch gate 32 to the ON state when a clock signal of logic "H" is input from the clock input terminal CP. At the same time, when the inverted clock signal of logic “H” is input from the inverted clock input terminal ICP, the latch gate 33 is provided.
Is switched on and the operating state is switched.

The switching gate 34 receives the inverted input signal IIN when the potential at the clock input terminal CP is logic "H".
Hold the logical value of the logical output IQM (N) of. The resistance R32 of the latch gate 33 in the inactive state at the subsequent stage
It is switched whether or not the collector current is drawn in via a logic output, and a logic output QS having a logic value opposite to that of the logic output IQM (N).
(N) is generated in the resistor R32.

At this time, since the potential of the inverting clock input terminal ICP becomes the logic "L", the switching gate 34 determines the logic value of the logic output QS (N) generated in the resistor R32 by the latch gate 33 in the subsequent stage. To hold. Then, it is switched whether or not the collector current is drawn through the resistor R41 of the latch gate 42 of the subsequent shift register stage 41 in the inactive state, and the logical output IQM (N + 1) having a logical value opposite to the logical output QS (N). Is generated in the resistor R41.

At this time, the logical output IQM (N + 1) output from the output terminal of the shift register stage 31 and the logical output IQM (N) input to the input terminal are in phase, and the shift register stage 31 is based on the clock pulse CP. The logical output IQM (N) given to the input terminal is sequentially transferred to the subsequent shift register stage 41.

In the case of this embodiment, the clock pulse CP is applied to the latch gate 32 at the first stage of the shift register stage 31.
Has no function of fetching the inverted input signal IIN when the signal is logic "H", the signal I inverted to the input signal IN is input to the latch gate 32 by the gate drive circuit described below.
It is designed to give IN.

As shown in FIG. 2, the gate drive circuit 50 is composed of a current source 51, a switching gate 52 and a differential amplification stage 53. The switching gate 52 is composed of a differential pair of transistors Q53 and Q54. The base of the transistor Q54 receives the clock signal CP and the base of the transistor Q53 receives the inverted clock signal ICP. The collector of the transistor Q53 is grounded. Differential amplification stage 53
Is composed of a differential pair of transistors Q51 and Q52, and the input signal IN is applied to the base of the transistor Q51.
The threshold voltage VTH is received at the base of the transistor Q52. Also transistors Q51 and Q5
The two common emitters are connected to the collector of the transistor Q54. Further, the collector of the transistor Q51 is connected to the common connection end of the collector of the transistor Q31 and the gate of the transistor Q32 in the latch gate 32 (FIG. 1) in the subsequent stage. As a result, the switching gate 52 of the gate drive circuit 50 switches the operation state of the differential amplification stage 53 based on the clock signal CP and the inverted clock signal ICP, and the latch gate 32 in the subsequent stage inverts the input signal IN to the inverted input signal. It is designed to give IIN.

In the case of the embodiment, the latch gates 32, 33,
Transistors Q31, Q33, Q in front of 42 and 43
The value of the threshold voltage VTH supplied to 41 and Q43 is set to -0.2 [V], and the transistor Q31 or Q32 is set based on the threshold voltage VTH and the voltage value of the inverted input signal IIN. , The transistor Q33 or Q34, the transistor Q41 or Q42, and the transistor Q43 or Q44 are turned on and the other is turned off.

In the above configuration, the shift register 30
When the input of the input signal IN consisting of serial data is started, the data is transferred based on the clock pulse CP. At this time, the clock pulse CP is logic "L",
A case where the logic outputs QS (N) and QS (N + 1) of the first and second shift register stages 31 and 41 are logic “H” and “L” will be described.

At this time, the switching gates 34 and 44
Since the transistors Q36 and Q46 of FIG. 2 are turned on respectively, the latch gates 33 and 43 in the subsequent stage operate as a latch circuit and hold the logical values of the logical outputs QS (N) and QS (N + 1). On the other hand, the second shift register stage 4
Since the latch gate 42 forming the preceding stage of 1 is inactive at this time, the logical output IQM of the latch gate 33 is
The logical value of (N + 1) is determined by the collector current drawn by the transistor Q34. Where shift register stage 3
Since the logical value of the logical output QS (N) of 1 is logical “H”, the logical “L” that is the inverted logical output QS (N) is transferred as the logical output IQM (N + 1).

Next, when the clock pulse CP rises to logic "H", the switching gate 3 is reversed, contrary to the above case.
The transistors Q35 and Q45 of 4 and 44 are turned on, respectively, and the latch gates 32 and 42 in the preceding stage operate as a latch circuit to hold the logic outputs IQM (N) and IQM (N + 1), respectively.

As a result, the transistors Q34 and Q44 are
Output QS of shift register stages 31 and 41 via
(N) and QS (N + 1) are not transferred to the latch gates 33 and 43 in the subsequent stage, but the other latch gate 32.
And 42 shift to the active state and hold the newly set state immediately before.

For example, when the logic value of the immediately preceding inverted input signal IIN is logic "H", the latch gate 32 holds this logic value and the transistor Q32 is turned on, so that the logic output QS ( N) falls to the opposite logic value, that is, logic "L". The latch gate 42 of the shift register 41 at the next stage holds the logical value "L" of the logical output IQM (N + 1) and the transistor Q41 is turned on to prevent the collector current from flowing through the resistor R42.
A logic "H" is output as S (N + 1).

As a result, at the end of one cycle of the clock pulse CP, the logic outputs QS (N) and QS (N + 1) of the shift register stages 31 and 41 change from logic "H" and logic "L" to logic "L". The logic value becomes "H" and the immediately preceding logic value is transferred to the subsequent stage. The same applies to clock pulse C
Each time P falls and rises, the logical value of serial data is sequentially transferred to the subsequent stage, and the shift register 30 functions as a shift register.

According to the above configuration, the shift register stage 3
1. A transistor Q31 whose base is grounded in the latch portion of 1,
Q33 and collector-grounded transistors Q32 and Q3
4 and the signal is transferred by the collector current flowing in the collector-grounded transistors Q32 and Q34, whereby the transfer gates 2 and 12 (FIG. 3) can be omitted and the latch gate 32 and the latch gate 32 in the preceding stage can be omitted. The following latch gate 33 is replaced by one switching gate 34.
Can be operated by. As a result, the shift register stage 31 or 41 can be configured with the number of elements less than half that of the conventional shift register stage 1, and the degree of integration can be further improved.

This achieves a degree of integration almost equal to that of the IIL, and is faster than the IIL and does not have a special manufacturing process, which is advantageous when used for processing serial data. Further, since the transfer gate can be omitted, the power consumption can be reduced to about half that of the conventional shift register.

In the above embodiment, the case where the shift register has a two-stage configuration has been described, but the present invention is not limited to this, and can be widely applied to a case where three or more stages are connected. Further, in the above-mentioned embodiment, the threshold voltage is −0.
Although the case of 2 [V] has been described, the present invention is not limited to this and may be set to another value.

[0034]

As described above, according to the present invention, the first self-holding circuit section including the first and second transistors and the third self-holding circuit section are provided.
And a second self-holding circuit formed of a fourth transistor, and a switching circuit that alternately switches the operating states of the first and second self-holding circuits. When transferring data, the third transistor Second from the collector electrode of
By transferring the data held by the first self-holding circuit unit to the second self-holding circuit unit based on the collector current drawn into the collector electrode of the transistor
The shift register can be configured with a half or less number of elements, the degree of integration can be further improved, and the power consumption can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of a shift register according to the present invention.

FIG. 2 is a connection diagram of the input stage.

FIG. 3 is a connection diagram showing a configuration of a conventional shift register.

[Explanation of symbols]

1, 30 ... Shift register, 2, 12 ... Transfer gate, 3, 13, 32, 33, 42, 43 ... Latch gate, 4, 14, 34, 44, 52 ... Switching gate, 5, 15, 35, 45, 51 ... Current source, 50 ...
Gate drive circuit, 53 ... Differential amplification stage.

Claims (3)

[Claims] 1. A self-holding circuit section, wherein the emitter electrodes of the first and second transistors are commonly connected, and the collector electrode of the first transistor is connected to the base electrode of the second transistor. The base electrode of the first transistor receives a predetermined threshold voltage, and the common connection end of the emitter electrodes of the first and second transistors receives a predetermined current at a predetermined timing, whereby the first transistor Of the collector electrode of the second transistor and a signal input from the common connection end of the base electrode of the second transistor are inverted and output from the collector electrode of the second transistor. 2. A first self-holding circuit section comprising first and second transistors having emitter electrodes commonly connected, wherein a collector electrode of the first transistor is connected to a base electrode of a second transistor. The emitter electrode is composed of third and fourth transistors commonly connected, and the collector electrode of the third transistor has a fourth electrode.
A second self-holding circuit portion connected to the base electrode of the transistor and a differential pair of the fifth and sixth transistors, each collector electrode of which is the common emitter of the first and second transistors and the first and second transistors. Switching means that is connected to a common emitter of the third and fourth transistors and that alternately switches the operating states of the first and second self-holding circuit portions based on a clock signal applied to the base electrode. And the second self-holding circuit section receives a predetermined threshold voltage on the base electrodes of the first and third transistors, and the collector electrodes of the first transistor and the base electrode of the second transistor. When data is transferred by receiving an input signal at the common connection terminal, the collector electrode of the third transistor is connected to the transistor of the second transistor. Shift register, wherein the transfer of data to the first self-holding circuit portion held on the basis of the collector current drawn Kuta electrode to the second self holding circuit section. 3. A collector electrode is connected to a signal input terminal of the first self-holding circuit portion, and a predetermined threshold voltage is input to a base electrode and a seventh transistor for inputting a predetermined input signal. Inversion signal formation in which the emitter electrode of the eighth transistor is commonly connected, and an inversion signal obtained by inverting the input signal is output from the collector electrode of the ninth transistor to the first self-holding circuit section. A ninth transistor having a collector electrode connected to a common connection end of the emitter electrodes of the seventh and eighth transistors and inputting a first clock signal to the base electrode,
And an emitter electrode connected in common to the ninth transistor, and a tenth transistor for inputting a second clock signal to the base electrode, and the seventh transistor based on the first and second clock signals. And an on / off switching means for controlling the on / off of the eighth transistor, and by controlling on / off of the seventh and eighth transistors based on the switching operation of the switching means, the inversion signal forming means can control the first self The shift register according to claim 2, wherein the inversion signal is output to the holding circuit section at a predetermined timing.