JPH06139069A - Internal register for microprocessor - Google Patents

Abstract

PURPOSE:To effectively utilize more register areas without being restricted by the number of registers to constitute an internal register. CONSTITUTION:For instance, eight pieces of 32-bit registers 22(0) to 22(7) are quartered by every 8 bits, and each output line of a first divided part 23a to a fourth divided part 23d in each register 22(0) to 22(7) is connected to a 32-bit data bus 11 through gates G0 to G3, and the first to the eighth registers 22(0) to 22(7) are selected and designated by register designate signals R0 to R3 from an address generator 24, and simultaneously, the outputs of the first to the fourth divided parts 23a to 23d in each register 22(0) to 22(7) are selected by output enable signals S0 to S3 for each gate G0 to G3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal register of a microprocessor used in electronic equipment.

[0002]

2. Description of the Related Art For example, various command data are stored in an internal register of a microprocessor, and by addressing according to a preset microprogram, a command stored in a register corresponding to the addressing position is stored. The data is read and the desired control is executed.

FIG. 4 is a block diagram showing a structure around an internal register in a conventional microprocessor. When instruction data including an execution address field fetched from a data bus 11 is latched in an instruction latch section 12, its execution is executed. The address field is transferred to the address generator 13 and the address for the internal register 14 is generated.

Here, the internal register 14 has a structure of, for example, 32 bits × 8 lines, and the data length is designated by a byte “8 bits”, a word “16 bits”, and a long word “32 bits”.

FIG. 5 is a diagram showing the structure of the execution address field included in the instruction data.
The upper 2 digits are the data length designation area and the lower 3 digits are the register designation area.

That is, the register designation area "000"-
"111" specifies any of the 8 registers,
Further, the data length designation areas "01", "11", and "10" respectively designate the read data length from the designated register as byte, word, or longword.

FIG. 6 is a diagram showing the configuration of a conventional addressing circuit for the internal register of the microprocessor. For the internal register 14 of 32 bits × 8, the address generator 13 outputs the execution address field A 3-bit register designating signal R corresponding to the register designating information is generated, and the lower 8-bit output buffer G1, the lower 16-bit output buffer G2 and the 32-bit output buffer G3 interposed between the data bus 11 and The lower 8-bit output enable signal S1 corresponding to the data length designation information of the execution address field,
Lower 16-bit output enable signal S2 and 32-bit output enable signal S3 are generated.

That is, "0" is written in the data length designation area of the execution address field given to the address generator 13.
If "1" and "000" are set in the register designating area, the register designating signal R becomes "000" to designate the internal register 14 (0) and the lower 8 bit output enable signal. S1 is output, and the lower 8-bit byte data in the internal register 14 (0) is transferred to the data bus 11 via the lower 8-bit output buffer G1.
Read to.

Further, the data length designation area of the execution address field given to the address generator 13 has "1".
When "1" and "010" are set in the register designating area, the register designating signal R becomes "010" to designate the internal register 14 (2) and the lower 16-bit output enable signal. S2 is output, and the lower 16-bit word data in the internal register 14 (2) is read out to the data bus 11 via the lower 16-bit output buffer G2.

Further, "1" is set in the data length designation area of the execution address field given to the address generator 13.
If "0" and "111" are set in the register specifying area, the register specifying signal R becomes "111" and the internal register 14 (7) is specified, and the 32-bit output enable signal S3 is specified. Is output, and the 32-bit longword data in the internal register 14 (7) is transferred to the data bus 11 via the 32-bit output buffer G3.
Read to.

Here, in the case of the conventional addressing circuit for the internal register of the above microprocessor, the designated data length is 8 bytes from the lower side for both bytes and words.
Since only the bits or 16 bits are designated and read, when the byte is designated, the remaining 24-bit area cannot be designated in the same register, and when the word is designated, the remaining 16-bit area is designated in the same register. The area cannot be specified.

FIG. 7 shows a conventional addressing state for the internal registers of the microprocessor. FIG. 7A shows a byte designation state for all registers D0 to D7, and FIG. 7B shows all register D0. The word designation state for D7 to D7 is shown in FIG.
The longword designation state for D7 is shown.

[0013]

Therefore, in the internal register of the conventional microprocessor, only one data can be designated to each of the eight registers D0 to D7 constituting the internal register 14.
For example, if 8 register areas in bytes or 8 register areas in words are secured on the microprogram, an unused area as indicated by the diagonal line x is left.

Therefore, for example, when it is desired to secure a register area for 4 bytes, a register area for 4 words, and a register area for 4 long words, there is no problem in capacity, but any register area for 4 registers is required. Cannot be secured at the same time, and there is a problem that an efficient program cannot be built such as temporary data saving processing.

The present invention has been made in view of the above problems,
An object of the present invention is to provide an internal register of a microprocessor that can effectively use a larger number of register areas without being restricted by the number of registers that form the internal register.

[0016]

That is, the internal register of the microprocessor according to the present invention is addressed according to the execution address field included in the instruction data, and L number of M bits is divided into N. Register, N gate means provided on the output line for each M bits of the L registers, and a register for the L registers according to the register designation information and the data length designation information of the execution address field. Address generating means for generating a designating signal and generating a gate selection signal for the N gate means are provided.

[0017]

That is, of the above L registers, each M bit data divided into N can be selectively read out through the gate means to one register. For example, one register secures a register area for four bytes or two words.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of the internal register of the microprocessor.
Eight registers 22 (0) to 22 (7) with 2 bits are provided, and each of the registers 22 (0) to 22 (7) has 4 bits for every 8 bits.
Will be divided.

The address generator 2 is provided in each of the first to fourth division parts 23a to 23d of the registers 22 (0) to 22 (7).
Register designating signals R0 to R3 each consisting of 4 bits and 3 bits
Is given, and the registers 22 (0) to 22 (7) in the respective division units 23a to 23d are designated.

Further, output gates G0 to G3 are individually interposed in the 8-bit output lines of the first division section 23a to the fourth division section 23d in the registers 22 (0) to 22 (7), respectively, and 32 bits are provided. It is connected to the data bus 11.

Then, for each of the output gates G0 to G3 from the address generator 24, a first division section 23a is provided.
Output enable signal S0 for the second division unit 23b, an output enable signal S2 for the third division unit 23c, and an output enable signal S3 for the fourth division unit 23d.

Here, the register designating signals R0 to R3 and the output enable signal S from the address generator 24 are provided.
0 to S3 are set and output according to the execution address field included in the instruction data, and the first register 22 in the register designating signals R0 to R3.
(0) If specified, "000", second register 22 (1)
In the case of designation, "001", in the case of designation of the third register 22 (2) "010", in the case of designation of the fourth register 22 (3), "011", in the designation of the fifth register 22 (4) In the case of "100", when the sixth register 22 (5) is specified, it is "101", and in the case of the seventh register 22 (6) is specified, "1"
10 ", if the eighth register 22 (7) is specified," 11 "
1 "is output.

Further, when the byte is designated by the designation registers 22 (0) to 22 (7) by the register designation signals R0 to R3, any one of the four output enable signals S0 to S3 is output to designate the word. At the time of, either the output enable signal (S0, S1) or (S2, S3) is output, and at the time of specifying the long word, the output enable signals (S0 to S3) are also output. Next, the operation of the internal register of the microprocessor having the above configuration will be described.

FIG. 2 shows each register designation address R0 for designation of byte, word and longword in the address generator 24 of the internal register of the microprocessor.
It is a figure which shows the truth value state of output enable signal S0-S3 with respect to -R3.

FIG. 3 shows an address designation state for the internal register of the microprocessor. FIG. 3A shows a byte designation state, FIG. 3B shows a word designation state, and FIG. Indicates a longword designation state.

That is, when the byte designation of the register "0" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "000", and the first register 22. (0) is specified and the first division unit 2
Only the output enable signal S0 for 3a is output, and the byte data D0B is read from the first dividing section 23a of the first register 22 (0) to the data bus 11 via the gate G0.

Further, when the byte designation of the register "1" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "000" like the above, and the first The register 22 (0) is designated, and only the output enable signal S1 for the second division unit 23b is output, and the byte data D1B from the second division unit 23b of the first register 22 (0) is transferred to the data bus 11 via the gate G1. Read to.

Further, when the byte designation of the register "4" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "001", and the second
The register 22 (1) is specified and the first division unit 23
Only the output enable signal S0 for a is output.
The byte data D4B is read from the first division unit 23a of the register 22 (1) to the data bus 11 via the gate G0.

That is, the byte data in the register designation "0" to "7" of the execution address field is secured by being divided into four in the first register 22 (0) and the second register 22 (1), and the gates G0 to G3. Will be read from any of the above.

On the other hand, when the word designation of the register "0" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "000" and the first register 22. (0) is specified and the first division unit 23a
And the output enable signal S0 to the second division unit 23b.
, S1 is output, and the word data D0W is read out from the first and second dividing sections 23a and 23b of the first register 22 (0) to the data bus 11 via the gates G0 and G1.

When the word designation of the register "1" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "000" as in the above, and the first The register 22 (0) is designated, and only the output enable signals S2 and S3 to the third division unit 23c and the fourth division unit 23d are output, and the first register 22 (0)
The word data D1W is read out from the third and fourth division sections 23c and 23d of the above into the data bus 11 through the gates G2 and G3.

Further, when the byte designation of the register "4" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "010", and the third
The register 22 (2) is specified and the first division unit 23
a and the output enable signal S for the second division unit 23b
Only 0 and S1 are output, and the word data D4W is read from the first and second dividing sections 23a and 23b of the third register 22 (2) to the data bus 11 via the gates G0 and G1.

That is, the word data in the register designations "0" to "7" of the execution address field are secured by being divided into two in the first register 22 (0) to the fourth register 22 (3), respectively, and the gate G0, G1 or G2,
It will be read from any of G3.

Next, when the long word designation of the register "0" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "000",
The first register 22 (0) is designated, and the output enable signals S0 to S3 to the first division unit 23a to the fourth division unit 23d are output, and the first register 22 (0)
Long word data D0L from the fourth division units 23a to 23d
Are read out to the data bus 11 through the gates G0 to G3.

When a long word designation of the register "1" is given in the execution address field of the instruction data, the register designation signals R0 to R3 from the address generator 24 become "001",
The second register 22 (1) is designated and the output enable signals S0 to S3 to the first division unit 23a to the fourth division unit 23d are output, and the first to the first registers of the second register 22 (1) are output.
Long word data D1L from the fourth division units 23a to 23d
W is read onto the data bus 11 through the gates G0 to G3.

Further, in the execution address field of the instruction data, when the long word designation of the register "4" is given, the address generator 24
The register designation signals R0 to R3 from "0" become "100", the fifth register 22 (4) is designated, and the output enable signals S0 to S3 to the first division unit 23a to the fourth division unit 23d are output, The long word data D4L is read from the first to fourth division parts 23a to 23d of the 5-register 22 (4) to the data bus 11 via the gates G0 to G3.

That is, the longword data in the register designation "0" to "7" of the execution address field is
It is secured in the first register 22 (0) to the eighth register 22 (7), respectively, and is read from the gates G0 to G3.

Therefore, according to the internal register of the microprocessor having the above-mentioned structure, for example, eight 32-bit registers 22 (0) to 22 (7) are arranged in 4 bits for each 8 bits.
The output lines of the first division unit 23a to the fourth division unit 23d in each of the registers 22 (0) to 22 (7) are connected to the 32-bit data bus 11 via the gates G0 to G3 to generate an address. Signal R0 from register 24
.About.R3 select and designate the first to eighth registers 22 (0) to 22 (7), and the output enable signals S0 to S3 to the respective gates G0 to G3 enable the respective registers 22.
(0) to 22 (7) in the first to fourth division parts 23a to 23
Since the output of d is selected, the register area for 8 bytes, 4 words, or 2 long words can be secured by using, for example, two 32-bit registers, and a substantial register area can be secured. It is possible to effectively secure the necessary register area and build an efficient program without expanding the.

[0040]

As described above, according to the present invention, an address is designated according to the execution address field included in the instruction data, and L registers divided into N every M bits and the above L registers. The N gate means provided on the output line for every M bits of the register, and the register specifying signals for the L registers according to the register specifying information and the data length specifying information of the execution address field, Since the address generating means for generating the gate selection signal for the N gate means is provided, it is possible to effectively utilize a larger number of register areas without being restricted by the number of registers forming the internal register. Will be possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of internal registers of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a truth value state of output enable signals S0 to S3 with respect to respective register designation addresses R0 to R3 for designation of byte, word and longword in an address generator of an internal register of the microprocessor.

3A and 3B show an address designation state for an internal register of the microprocessor, FIG. 3A shows a byte designation state, FIG. 3B shows a word designation state, and FIG. Shows a longword designation state.

FIG. 4 is a block diagram showing a configuration around an internal register in a microprocessor.

FIG. 5 is a diagram showing a configuration of an execution address field included in instruction data.

FIG. 6 is a diagram showing a configuration of a conventional addressing circuit for an internal register of a microprocessor.

7A and 7B show a conventional addressing state for an internal register of a microprocessor. FIG. 7A is a diagram showing a byte designation state, FIG. 7B is a diagram showing a word designation state, and FIG. ) Is a diagram showing a longword designation state.

[Explanation of symbols]

11 ... 32-bit data bus, 21 ... Internal register, 2
2 (0) to 22 (7) ... Registers, 23a to 23d ... 1st to 1st
Fourth division unit, 24 ... Address generator, R0-R3 ... Register designation signal, S0-S3 ... Output enable signal, G0
~ G3 ... gate.

Claims (1)

[Claims] 1. An internal register of a microprocessor which is addressed according to an execution address field included in instruction data, wherein L registers are divided into N every M bits, and every M bits of the above L registers. N gate means provided on the output line of the control circuit, and the N gate means for generating register designating signals for the L registers in accordance with the register designating information and the data length designating information of the execution address field. And an address generating unit for generating a gate selection signal for the internal register of the microprocessor.