JPS62133544A - Memory device - Google Patents

Abstract

PURPOSE:To shorten the processing time of an instruction by executing the shift processing of a data extending over two optional continuous addresses, in the course of an access. CONSTITUTION:When there is the instruction of a shift to an address A, an access is executed simultaneously extending over one address of the front or the rear address by the address A shown by an address signal applied to an address register 3, and the instruction contents of the shift. A data extending over two optional continuous addresses is sent to a switching circuit 2. and a data which has executed a shift processing in th course of an access is outputted. Accordingly, by a memory access of once, the write and read-out of a memory 100 can be executed extending over two optional continuous address.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory device used in a data processing device or the like.

[Conventional technology]

Conventionally, no memory device of this type has a function of reading or writing data while shifting the data across two consecutive addresses. Even in some memory devices equipped with a shift function, only the data at the lowest location specified by the read address is used for shifting.

[Problem that the invention seeks to solve]

Therefore, the conventional memory device described above has two consecutive memory devices.
When shifting data that is registered across addresses, it is necessary to access the target data twice to read it into registers for two addresses, and then shift it using a shifter, which increases processing time. Another drawback is that when data for one address is shifted and written across two addresses, it is necessary to write at least twice, which also takes a long processing time. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device that can perform a specified shift using data for two consecutive locations and read out the data for one location by one memory access. It is in.

Another object of the present invention is to provide a memo I system that can write across any two consecutive addresses in one memory access without shifting the data for one address. The goal is to provide M.

[Means for solving problems]

The memory device of the present invention comprises a memory that is composed of a plurality of memory blocks that are accessed by individual address signals, these memory blocks are sequentially allocated to each address, and shifting is performed in units of these memory blocks; If there is no instruction, the address signal for the memory is output as is to each memory block, and in the case of a shift instruction or leftward direction, the address signal is output to the memory block constituting the upper bits equal to the number of bits of the shift. The address signal added by 1 is output, and the address signal is output as is to other memory blocks, and in the case of a shift instruction or right direction, the address signal is output to the memory block constituting the lower bits equal to the number of bits of the shift. output an address signal obtained by subtracting 1 from the address signal,
For other memory blocks, there is an address generation circuit that outputs the address signal as is, and when there is no shift instruction, the data of each memory block read from the memory is output as is, and when there is a shift instruction, the address generation circuit outputs the address signal as is. It has a switching circuit that edits the data of each memory block read from the memory according to the specified shift contents and outputs the edited data.

Another memory device of the present invention is a memory that is composed of a number of memory blocks accessed by individual address signals, these memory blocks are sequentially allocated to each address, and shifting is performed in units of these memory blocks. , If there is no shift instruction, the address signal for the memory is output as is to each memory block, and if the shift instruction is in the left direction, the memory block that constitutes the upper bits equal to the number of bits of the shift is output to each memory block. outputs an address signal that is added or subtracted by 1 to the address signal in response to reading or writing, and outputs the address signal as is to other memory blocks, and if the shift instruction is in the right direction, it outputs an address signal that is added or subtracted by 1 to the address signal. For the memory block constituting the lower bits equal to the number of bits of
An address generation circuit that outputs the calculated or added address signal and outputs the address signal as it is to other memory blocks, and an address generation circuit that outputs the address signal as it is to other memory blocks, and an address generation circuit that outputs the data of each memory block successively from the memory when there is no shift instruction. There is a switching circuit that outputs the data as is, and when there is a shift instruction, edits and outputs the data of each memory block successively retrieved from the memory with the instructed shift contents, and when there is no shift instruction, the input memory It has a switching circuit that outputs the write data as it is, and when there is a shift instruction, edits the write data with the instructed shift contents and outputs the edited data.

In this way, if there is no shift instruction, only the address indicated by the given address signal is accessed, and if there is a shift instruction, the address indicated by the given address signal and the shift instruction are accessed. According to the contents of the above address, by accessing one of the addresses preceding the above address at once, and by performing shift processing of data spanning any two consecutive addresses during the access, by one memory access, Memory writing and reading any two consecutive times
This can be done across addresses.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing one embodiment of the memory device of the present invention.

This embodiment is an embodiment of a memory device having a function of reading data by shifting 4 bits to the left or 4 bits to the right in addition to the normal reading function.

The memory 1 is composed of a portion +a, a portion +b, and a portion 1c, and each portion is accessed by a separate address. This memory 1 is a 128-word buffer memory, where 1 word consists of 32 bits, and the 0 part 1a is used for work such as decimal operations.
and 1c is a memory of 4 bits x 128 words,
Portion 1b is a 24 bit by 128 word memory.

Reading from part 1a is performed using address signal 105a, part 1
Read from b is address signal 105b, gE minute 1c
Reading of data is performed by address signal 105G. Data l0Ia-101c read from each portion la, Ib, and Ic is sent to the switching circuit 2. Writing of data +00 to memory 1 is performed in the word specified by address signals 105a-105c in the same manner as in the case of reading.

The switching circuit 2 receives the data 101a read from the memory.
101c is input, and according to the read instructions specified at that time, that is, the instructions of signals 106 and 107, it is outputted as data 102 with a 4-bit shift to the left, a 4-bit shift to the right, or no shift.

When the signal +06 is "1", there are 4 bits, and when it is "0", there is no shift. Further, when the signal 107 is "1", it is a left shift, and when it is "0", it is a right shift instruction.

Address register 3 is a register that holds an address when writing to or reading from memory 1. When accessing memory 1, address signal 103 is set and output as address signal 104 to address generation circuit 4.

The address generation circuit 4 generates the memory 1 from the parts 1a to 1C based on the address signal 104 which is the output of the address register 3.
address signals 105a to 105+J are created. When there is no shift instruction (signal 106."0"), address signals 105a to 105C all have the same value, and are set to the same value as address signal 1σ4. When there is an instruction to shift 4 bits to the left (signal 106: "1", signal 107: "1"), address signal 105a is set to the value of address signal 104 plus 1, and address signal 1
05b and 105C are set to the same value as address signal 104. When there is an instruction to shift right 4 bits (signal 10
6.“1” and signal 107.“0”), the address signals 105a and 105b are set to the same value as the address signal 104, and the address signal 105C is set to the value obtained by subtracting 1 from the address signal 104.

Next, various read operations in this embodiment will be briefly explained. When reading address A without shifting, first set A in address register 3, and then set signal 1.
This read operation is the same as the read function of conventional memory devices, and the address signals 105a to 105G are all 8, and the contents of address A in memory 1 are read as data 101a to 101G. and output as data 102.

When reading address A by instructing a 4-bit shift to the left, set A in address register 3,
When reading is performed by setting both the signal 106 and the signal 107 to "1", A is output to the address signal 105a for the portion 1a of the memory 1, and A is output to the address signals 105b and 105G for the portion 1b and 1c of the memory 1. The data l01a~ read out by the respective address signals
101G is sent to the switching circuit 2. The switching circuit 2 edits the data 101a to 101c into a form shifted by 4 bits to the left, and outputs the data 102.

When reading by instructing a right bit shift to address A, A is set in the address register 3, the signal 106 is set to 1°, the signal 107 is set to "0", and the reading is performed. Then, the address signals 105acl''i and 105b for the portions 1a and 1b of the memory 1 are output with either A-1 or A-1 as the address signal 105c for the A1 portion 1C, and the data 10 sequentially output by the respective address signals is output.
1a to 101c are sent to the switching circuit 2. The switching circuit 2 edits data 101a to 101c into a form shifted by 4 bits to the right, and data +02 v! Specific power.

FIG. 2 is a diagram showing the correspondence between data stored in the memory 1 and data read out by various read operations. Case 1 is when reading is performed on address A without shifting, case 2 is when reading is performed on address A with instructions for the left 4 bits, and case 3 is when reading is performed on address A without shifting.
This is a case where an address is read by instructing to shift 4 bits to the right.

As is clear from the above explanation, if you want to read the data at a certain address, including the data at Mae-toshi's address, by shifting it 4 bits to the left or right, conventionally the memory access is performed twice to read the data for the two addresses. Previously, the desired data could only be obtained by reading and shifting, but according to this embodiment, one memory access allows data from any two consecutive locations to be shifted by four bits to the left or right as instructed. By outputting the processed data, processing time can be shortened.

In this embodiment, a memory device with a function of reading data by shifting 4 bits to the left or 4 bits to the right is described, but a memory device with a function of writing data to memory while performing a similar shift is also configured. This can be easily accomplished by providing a circuit corresponding to the switching circuit 2 of this embodiment on the data input side of the memory 1. in this case,
The relationship between the addition/subtraction and shifting directions of the address signal in the address generation circuit 4 is opposite to that in the case of reading.

〔Effect of the invention〕

As explained above, in the present invention, when there is no shift instruction, only the address indicated by the given address signal is accessed, and when there is a shift instruction, the address indicated by the given address signal is accessed. Then, depending on the contents of the shift instruction, access is performed at once across either of the addresses before or after the above address, and the shift processing of data spanning any two consecutive addresses is performed during the access.
By accessing the memory twice, it is possible to write and read data across two arbitrary consecutive addresses, and there are nine ways to reduce ri'+ during instruction processing.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the memory device of the present invention, and FIG. 2 is a diagram showing the correspondence between data stored in the memory 1 and data read out by various read operations. 1...Memory, 2...Switching circuit. 3...Address register. 4...Address generation circuit. Figure 1

Claims (1)

[Scope of Claims] A memory device that can read out data spanning two arbitrary consecutive addresses by performing a specified shift and converting data to one address by one memory access. A memory that consists of multiple memory blocks that are accessed by individual address signals, these memory blocks are sequentially allocated to each address, and a shift is performed in units of these memory blocks, and a memory that is made up of multiple memory blocks that are accessed by individual address signals, and a memory that is shifted in units of memory blocks. outputs the address signal for the memory as it is to each memory block, and if the shift instruction is in the left direction, outputs an address signal obtained by adding 1 to the address signal for the memory block that constitutes the upper bits equal to the number of bits of the shift. The address signal is output as is to other memory blocks, and when the shift instruction is in the right direction, the address signal is output to memory blocks that constitute lower bits equal to the number of bits of the shift. Outputs the address signal obtained by subtracting 1 from
For other memory blocks, there is an address generation circuit that outputs the address signal as is, and when there is no shift instruction, the data of each memory block read from the memory is output as is, and when there is a shift instruction, the address generation circuit outputs the address signal as is. The memory device includes a switching circuit that edits data in each memory block read from the memory according to specified shift contents and outputs the edited data. 2. With one memory access, data spanning two consecutive addresses can be read out as data for one address by performing the specified shift, and data for one address can be read out as data for one address. A memory device that can write across two consecutive addresses with a single memory access, and is composed of multiple memory blocks that are accessed by individual address signals, and each address A memory in which these memory blocks are sequentially allocated and a shift is performed in units of memory blocks, and a memory in which the address signal for the memory is output as is to each memory block when there is no shift instruction, and the shift instruction is directed to the left. In this case, an address signal obtained by adding or subtracting 1 from the address signal is output to the memory block constituting the upper bits equal to the number of bits of the shift in accordance with the memory read/write, and the address signal is output to the other memory blocks. When the shift instruction is in the right direction, the address signal is output as is for the memory block that constitutes the lower bits equal to the number of bits of the shift, and the address signal is output in accordance with the memory read and write. An address generation circuit that outputs an address signal that is subtracted or added by 1, and outputs the address signal as it is to other memory blocks, and the data of each memory block that is read from the memory if there is no shift instruction. If there is a shift instruction, the data in each memory block read from the memory is edited with the specified shift contents and output, and if there is no shift instruction, the input A memory device having a switching circuit that outputs write data to a memory as is, and when a shift instruction is given, edits the write data with the instructed shift contents and outputs the edited data.