JPH06139052A - Adding circuit - Google Patents

Abstract

PURPOSE:To delete the useless arithmetic time of the adding circuit of three binary data, and to attain a high speed by searching the sum data of three input data and output carry data by the first adding means, and searching the sum data of the pertinent sum data and the output carry data by the second adding means. CONSTITUTION:This circuit is equipped with an adder 1 which inputs input data A(A3, A2, and A1), B(B3, B2, and B1), and C(C3, C2, and C1), and outputs sum data SX(SX3, SX2, and SX1) and output carry data KX(KX3, KX2, and KX1), and an adder 2 which inputs the sum data SX, output carry data KX, input signals KB11, and KC11, and fixed signal ZCO, and outputs sum data SC (SC4, SC3, SC2, and SC1) and an output carry signal KCO4. The adder 1 is equipped with full adders F11-F13, and the adder 2 is equipped with full adders F21-F24. Thus, the sum signals and output carry signals of the outputs of the adder 1 are already changed, so that the useless arithmetic time can not be generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder circuit, and particularly to 3
The present invention relates to an adder circuit that obtains the sum of individual binary data.

[0002]

2. Description of the Related Art Conventionally, an adder circuit of this type is constructed such that first the sum of two data is calculated, and then the sum of the data and the remaining one data is calculated to obtain the sum of three data. It was.

As shown in FIG. 3, the conventional adder circuit has 3-bit input data A (A ₃ , A ₂ , A ₁ ) and B (B ₃ , B ₂ , B ₁ ) and an input carry signal, respectively. K _BI1 as an input, the sum data S _B (S _B3 , S _B2 , S _B1 ) and the output carry signal K _BO3 as an output, and the sum data S _B and the remaining input data C (C ₃ , C ₂ , C ₁ ), the input carry signal K _CI1 , the output carry signal K _BO3 and the fixed signal Z _C0 are input, and the sum data S _C (S _C4 , S _C3 , S _C2 ,
S _C1 ) and output carry signal K _CO4 as an output adder 4
It was equipped with and.

[0004] The adder 3, the input data A, the bit signals A ₁ of B, B ₁ and A _2, B ₂ and A _3, B ₃ and was used as a input, respectively, the bit signal S _B1 of the sum data S _B It comprises full adders F31, F32 and F33 which output S _B2 and S _B3 . As for the carry signal, the input carry signal K _BI1 is _sent to the full adder F31 and the output carry signal K _BI1 is output.
_BO1 is input to full adder F32, and its output carry signal K _BO2 is input to full adder F33, and the output of full adder F33 is transmitted as output carry signal K _BO3 . The adder 4 receives the bit signals S _B1 , C ₁ and S _B2 , C ₂ and S _B3 , C ₃ of the sum data S _B and the input data C, respectively, and inputs them to the bit signal S _C1 of the sum data S _C. Full adders F41, F42 and F43 which output S _C2 and S _C3
And an output carry signal K _BO3 and a fixed signal Z _C0 as inputs, and a full adder F44 which outputs a bit signal S _C4 of the sum data S _C. The carry signal is an input carry signal. K _CI1 is _sent to the full adder F41 and its output carry signal K
_CO1 is input to full adder F42, its output carry number K _CO2 is input to full adder F43, and its output carry signal K _CO3 is input to full adder F44, and the output of full adder F44 is output carry. It is transmitted as signal K _CO4 .

Further, full adders F31 to F33, F41 to
All F44s have the same configuration, and FIG. 4 is a logic circuit diagram showing an example thereof. Full adders F31 to F33, F4
As shown in FIG. 4, 1 to F44 are the logical product gate AND1 and the exclusive OR gate EOR1 which receive the input signals A and B, the output of the gate EOR1, and the exclusive carry which receives the input carry signal Ci. A logical sum gate EOR2 and a logical product gate AND2, and a logical sum gate OR whose inputs are the outputs of the gates AND2 and AND1
1 and the respective outputs of the gate OR1 and the exclusive OR gate EOR2 are output as the output carry signal Co and the sum signal S.

Next, the operation will be described.

First, the operation of the full adder shown in FIG. 4 will be described with reference to the truth table shown in Table 1.

[0008]

[Table 1]

Since the sum signal S is an exclusive OR output signal of the exclusive OR output signal of the input signals A and B and the input carry signal Ci, among the three signals A, B and Ci,
If any one or all three have a logical value of 1, the logical value is 1, and otherwise, the logical value is 0. The output carry signal Co is the logical product output signal of the input signals A and B, the exclusive OR output signal of the input signals A and B, the exclusive OR output signal of the input signals A and B, and the input carry signal Ci. Since it is the logical sum output signal with the logical product output signal, the three signals A,
If any two or all three of B and Ci have the logical value 1, the logical value is 1, and otherwise, the logical value is 0. That is, according to the following two logical expressions.

[0010]

FIG. 5 is a time chart showing the operation of the conventional adder circuit. FIG. 5 (A) input data A, B, C and input carry signal K _BI1, K _CI1 the value is changed at the same time,
The addition operation times of the sum operation and carry operation per bit of the full adders F41 to F44 forming the adder 4 are set to be equal to t _D, and the full adders F31 to F3 forming the adder 3 are set.
3 shows the case where the respective operation times of the sum operation and carry operation per 1 bit of 3 are set to be equal to t _D, and FIG. 5B shows the operation time of the full adders F31 to F33 which is twice t _D. Is shown. The sum signals S _B1 , S _B2 , S _B3 and the output carry signal K _BO3 of the adder 3 are calculated based on the change of the input carry signal K _{BI in} the calculation time t in FIG. 5 (A) and FIG. 5 (B), respectively. _D , 2 · t _D , 3 · t _D or 2 · t _D , 4 ·
Changes after t _D , 6 · t _D and 6 · t _D. Therefore, the sum signals S _C1 , S _C2 , S _C3 , S _C4 of the adder ₄ and the output carry signal K CO4 are the input carry signal KBI of the adder 3.
From the change of 1 in FIG. 5 (A), the calculation times are 2 · t _D, 3 · t _D , 4 · t _D , 5 · t _D and 5 · t _{D, respectively.}
It will change later. At this time, in the full adder F42, the carry signal K _CO1 and the sum signal S _{B2, which} are input, are changing at the same time, so that the calculation time is not wasted. Similarly, there is no waste in the full adder F43. On the other hand, in FIG. 5 (B), the calculation time is 3 · t _D , 5 · t _D , 7 ·, respectively.
Changes after t _D , 8 · t _D and 8 · t _D. At this time, in the full adder F 42, since the change of the signal S _B2 to changes in signal K _CO1 it is time t _D later, waste is generated in the time t _D in calculation time. Similarly, waste also occurs in full adder F43.

That is, the calculation time Tc is 8 · t _D instead of 6 · t _D , and the dead time Tl is 2 · t _D.

[0013] If the input data is n-bit, the following equation Tc = 2 · (n + 1 ) · t D Tl = (n-1) · t According to _D. When the input data is 8 bits, the calculation time Tc =
18 · t _D , dead time Tl = 7 · t _D , about 40%
Wasted.

[0014]

The above-described conventional adder circuit obtains the sum data of two input data by the first adder, and then calculates the sum data of the sum data and the remaining one input data. Since the change is made by the second adder, the change of the two sum signals of the first adder and the change of the two carry signals of the second adder do not match. There is a drawback that wasteful calculation time is generated. Especially in systems with fast response or high data rates,
The wasteful operation time is fatal, and in order to avoid this, it is necessary to match the operation speeds of the respective full adders forming both adders, which impairs the degree of freedom in design.

[0015]

SUMMARY OF THE INVENTION The adder circuit of the present invention comprises n
The first and second and third input data, which are binary numbers of (integer) bits, and the first and second input carry signals are input, and the n + 1-bit first sum data and the output carry signal are input. In an adder circuit for outputting, first adder means for inputting the first, second and third input data and outputting second sum data and first carry data; and the second sum data. And second adding means for inputting the first carry data and the first and second input carry signals and outputting the first sum data and the output carry signal. Has been done.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In this embodiment, the same input data as in the conventional example has a 3-bit structure, and as shown in FIG. 1, the input data A (A ₃ ,
A ₂ , A ₁ ) and B (B ₃ , B ₂ , B ₁ ) and C
Input (C ₃ , C ₂ , C ₁ ) and sum data S _X (S
_X3 , S _X2 , S _X1 ) and output carry data K _X (K _X3 ,
K _X2, K _X1) an adder 1 outputs the sum data S _X output carry data K _X and the input carry signal K _BI1, K _CI1
And fixed signal Z _C0 as input, sum data S
_C (S _C4 , S _C3 , S _C2 , S _C1 ) and output carry signal K _CO4
And an adder 2 that outputs and.

The adder 1 includes bit signals A ₁ , B ₁ , C ₁ and A ₂ , B ₂ , C ₂ and A of input data A, B, C, respectively.
₃ , B ₃ and C ₃ are input, and the bit signals S _X1 , K _X1 and S _{X2 of} the sum data SX and the output carry data K _X are input.
Full adders F11 to which outputs K _X2, S _X3 , and K _X3
And F13. The adder 2 receives the bit signal S _X1 of the sum data S _X and the input carry signal K _BI1 as input, and the full adder F21 which outputs the bit signal S _C1 of the sum data S _C , and the sum data S _X , Output carry data K _X
Fixed bit signal Z _X2 , K _X1 and S _X3 , K _X2 respectively, and full adders F22 and F23 which output bit signals S _C2 and S _C3 of sum data S _C and fixed signal Z
_CO and a bit signal K _{X3 of} the output carry data K _X are input, and a full adder F24 which outputs a bit signal S _C4 of the sum data S _C is provided. The carry signal is the input carry signal K _CI1 to the full adder F21, the output carry signal K _CO1 to the full adder F22, and the output carry signal K _CO2.
Is input to the full adder F23, and its output carry signal K _CO3 is input to the full adder F24, and its output is transmitted as the output carry signal K _CO4 . Further, as in the conventional example, the full adders F11 to F13 and F21 to F24 are all shown in FIG.
The circuit shown in FIG.

Next, the operation of this embodiment will be described with reference to the time chart shown in FIG.

[0019] FIG. 2 (A), the input data A, B, the values of C and the input carry signal K _BI1, K _CI1 is changed at the same time, the first full adder F21~F24 constituting the adder 2 The total operation time of the sum operation and the carry operation per bit are set to be equal to t _D, and the full adders F11 to F13 forming the adder 1
2B shows the case where the respective calculation times of the sum calculation and the carry calculation for each 1 bit are equally set to t _D , the above calculation times of the full adders F11 to F13 are set to double t _D. Each case is shown. Sum signals S _X3 , S _X2 , S _{X1 of the} adder 1
And output carry signals K _X3 , K _X2 , K _X1 are input signals C
In Figure 2 the _first change (A) or FIG. 2 (B), the changes in each operation time t _D simultaneously also 2 · t _D and after the same time. Therefore, the sum signals S _C1 , S _C2 ,
S _C3 , S _C4 and the output carry signal K _CO4 are calculated based on the change of the input signal C ₁ of the adder 1, and the calculation time is 2 · t _D
3 · t _D , 4 · t _D , 5 · t _D and 5 · t _D or 3 · t
Changes after t _D , 4 · t _D , 5 · t _D , 6 · t _D and 6 · t _D. At this time, the calculation in the full adder F22 starts from the change of the carry signal K _{CO1 that} is the input, and the sum signal S _X2 or the carry signal K _X1 has already changed, so there is no need to start the calculation. Regardless of the time, the dead time is zero. When the input data is n bits, the calculation time T _C and the dead time T ₁ are in accordance with the following equation: T _c = (n + 3) · t _D T _l = 0.

[0020]

As described above, in the adder circuit of the present invention, the sum data of the three input data and the output carry data are obtained by the first adding means, and then the sum data and the output carry data are obtained. Since the sum data of and is obtained by the second adding means, the sum signal and the output carry signal of the output of the first adding means have already been changed, and therefore no useless calculation time is generated. There is an effect. As a result, the calculation speed of the first adder may be set so as to match the calculation speed required by the system, independently of the calculation speed of the second adder, and thus the degree of freedom in design is increased. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an adder circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the adder circuit according to the present embodiment.

FIG. 3 is a block diagram showing an example of a conventional adder circuit.

FIG. 4 is a block diagram showing an example of a configuration of a Zen adder.

FIG. 5 is a time chart showing an example of the operation of a conventional adder circuit.

[Explanation of symbols]

1 to 4 adders F11 to F13, F21 to F24, F31 to F33, F
41-F44 full adder

Claims (2)

[Claims] 1. Inputting first and second and third input data, which are binary numbers of n (integer) bits, and first and second input carry signals, and first sum data of (n + 1) bits. In an adder circuit that outputs an output carry signal, first adding means that inputs the first and second and third input data and outputs second sum data and first carry data, A second addition which receives the second sum data, the first carry data and the first and second input carry signals and outputs the first sum data and the output carry signal. And an adder circuit. 2. The first adding means inputs data of respective bits of the first, second and third input data, and outputs the respective bits of the second sum data and the first carry data. N full adders for respectively outputting bit data, wherein the second adding means inputs the least significant bit data of the second sum data and the first and second input carry signals The least significant bit data of the first sum data and the most significant bit data of the first sum data generated by inputting the most significant bit of the first carry data. N to output the data of each bit including
The adder circuit according to claim 1, comprising +1 full adder.