JPH06138472A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide the liquid crystal display device which can suppress variance in the angle and length of oblique wiring and a decrease in the angle of slanting electric wirings since a connection excessive part of a TCP(tape carrier package) is not concentrated on a right-end TCP, facilitates the designing of electric wirings and suppresses an increase and variance in the resistance of the slanting electric wirings and the generation of a short circuit defect between slanting electric wirings and connects electric wirings of a liquid crystal display part to TCPs with high density and is advantageous to compact designing. CONSTITUTION:The liquid crystal display device which has plural TCPs (T1,U- Tn,U, and T1,L-Tn,L) which are connected to respective input terminals arrayed at the edge parts of the lateral and longitudinal sides of the transparent substrate 1 of the liquid crystal display part and also arrayed at the edge parts of the lateral side and longitudinal side; and TCPs having excessive connection terminals which are not connected to the input terminals are arranged at both ends of the lateral side and longitudinal side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device in which a plurality of TCPs (tape carrier packages) connected to respective input terminals provided on a transparent substrate of a liquid crystal display section are arranged on the transparent substrate. .

[0002]

2. Description of the Related Art For example, an active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system, and especially the color liquid crystal display device. Then it is becoming an indispensable technology. A typical example of the switching element is a thin film transistor (TFT).

An active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, "12.5 type active matrix type color liquid crystal display employing a redundant structure", Nikkei Electronics, p.
~ 210, known on December 15, 1986, published by Nikkei McGraw-Hill, Inc.

The liquid crystal display unit (liquid crystal display panel, liquid crystal display element) is used to set the orientation of thin film transistors, transparent pixel electrodes, thin film transistor protective films, and liquid crystal molecules on the lower transparent glass substrate with the liquid crystal layer as a reference. A lower transparent substrate on which a lower alignment film is sequentially provided, and an upper transparent substrate on which a black matrix, a color filter of three primary colors, a color filter protective film, a common transparent pixel electrode, and an upper alignment film are sequentially provided on an upper transparent glass substrate. The alignment films are stacked so that they face each other, and both substrates are bonded by a sealing material provided around the edge of the substrate surface, and liquid crystal is sealed between both substrates. A backlight for supplying light to the liquid crystal display unit is arranged on one transparent substrate side of the liquid crystal display unit, and a drive circuit is formed around three sides of the liquid crystal display unit to form a “U” -shaped print. The substrate is placed. Each input terminal of the liquid crystal display unit and each output terminal of the printed circuit board are electrically connected via a TCP on which an IC chip for driving the liquid crystal display unit is mounted. The input terminals of the liquid crystal display section and the output terminals of the TCP are connected via an anisotropic conductive film.

[0005]

FIG. 20 is a plan view showing the arrangement of TCPs in a conventional liquid crystal display device.

1 is a TFT substrate (lower transparent glass substrate SUB1 in FIG. 6) of the liquid crystal display unit, and T ₁ , _{U to} T _n , _U are n pieces on the upper side on the video signal line (drain signal line or vertical signal line) side. TCP (the central TCP is not shown), T ₁ , _L
T _n and _L are n TCPs on the lower side of the video signal line side (the central TCP is not shown), P _t is the pitch of the TCP output terminals, q is the number of TCP outputs, and L is TCP. Distance between,
2d is the total number of video signal lines, P _d is the pitch of the video signal lines,
L _s is the length of the diagonal wiring area, θ is the angle of the diagonal wiring (θ =
tan ~ ¹ (L _s / L _r )), NC (no connection) is a connection residual terminal that is not connected to the input terminal of the video signal line of the liquid crystal display, M is the number of connection residual terminals, and L _r is a connection residual portion. Is the length of.

As the TCP, the one in which the pitch P _t of the output terminals of the TCP has already been determined is used, and in many cases, the total number of video signal lines in the liquid crystal display cannot be divided by the number of TCP outputs. The video signal lines are alternately drawn out to the upper and lower lateral edges of the TFT substrate 1 of the liquid crystal display section. Here, the total number of TCPs connected to the video signal line is 2n (n on each of the upper side and the lower side), and the number of outputs of each TCP is q. The odd-numbered video signal lines are led out to the upper side, the even-numbered video signal lines are led out to the lower side, and each video signal line is connected to each input terminal through the diagonal wiring as shown in the drawing and each input is connected. The terminal is connected to each output terminal of TCP. Each number n of upper and lower TCPs is an integer part of d / q, and the number n of TCPs when it is not divisible by an integer is a value obtained by adding 1.

As a first example, TCP output terminal pitch P _t = 0.28 mm, TCP output number q = 160, total number of video signal lines 2d = 1120, video signal line pitch P
_In the case of _d = 0.204 mm, d / q = 3.5, and 1 is added to 3.5 to obtain n = 4. The total number of TCPs required is 2n = 8. Also, the TFT of the liquid crystal display section
The number of remaining TCP terminals that are not connected to the input terminals of the substrate 1 is (4-3.5) × 160 = 80 outputs. The length L _r of the connection surplus portion is 80 × 0.28 mm = 22.4.
It is as large as mm.

As a second example, TCP output terminal pitch P _t = 0.1 mm, TCP output number q = 192, total number of video signal lines 2d = 3360, video signal line pitch P _d
= 0.068 mm, d / q = 8.75 and n = 9. The total number of TCPs required is 2n = 18. In addition, the number of TCP terminals with a connection remainder is (9-
8.75) × 192 = 48 outputs. The length L _r of the connection surplus portion is 48 × 0.1 mm = 4.8 mm.

In the conventional liquid crystal display device, as shown in FIG. 20, on the upper side and the lower side, n TCPs are arranged densely and repeatedly at equal intervals L from the left end as a starting point. In this method, since the angle and length of the diagonal wiring are different for each TCP as shown in the figure, it takes time to design the diagonal wiring. Further, the angle of the diagonal wiring becomes smaller and the length of the diagonal wiring becomes longer toward the right, so that the wiring resistance increases and varies. Further, when the angle of the diagonal wiring becomes small, the interval between the diagonal wiring becomes narrow, which causes a short circuit failure between the diagonal wirings. For this reason, there may be a case where the design of the diagonal wiring is completely impossible. It should be noted that such a connection surplus problem becomes serious when the number after the decimal point of d / q is large.

In the first example, the TF of the liquid crystal display section
The length of the portion of the T substrate 1 where n TCPs on the video signal line side are connected is about 1119 (total number of video signal lines 2d-1).
× 0.204 (pitch P _d ) = 228.276 mm. On the other hand, if the length of each TCP is 50 mm and the distance L between TCPs is set to 9 mm, the total length from the TCP at the left end to the TCP at the right end is 50 (mm) × 4 (pieces) +9.
(Mm) × 3 = 227 mm, and the lengths of both are almost the same. In this state, if an attempt is made to connect the output terminal of the TCP on the right end to the input terminal of the video signal line, the distance L _r = 80 × 0.28 = 22.4 mm of the connection remainder is large, and therefore the right end is slanted. Wiring cannot be formed. That is, the angle θ of the rightmost diagonal wiring is tan θ = L _s / L _r
Can be expressed as follows (L _s is the length of the diagonal wiring region, L _r is the length of the connection remainder portion), but assuming that L _s = 4 mm as a normal value, in the first example, θ = arctan (4/22 ．
4) = 10 degrees. At this angle, the normal wiring width is 30
When the wiring pitch is 70 μm and the wiring interval is 70 μm, the diagonal wiring cannot be formed, and the diagonal wirings overlap each other. Also, the second
Also in the example of θ = arctan (4 / 4.8) = 39.8
It becomes degree. As described above, the small angle θ means that the distance between the diagonal wirings is long. Therefore, the resistance and its variation are large, and the distance between the diagonal wirings is narrow, resulting in a short circuit failure. Cause of. The angle θ of the diagonal wiring at the right end is preferably set to 20 degrees or more. As a countermeasure against this, in order to secure the angle θ of the diagonal wiring of a certain value or more, the position of the TCP on the right side is further shifted to the right side, and a part of the TCP extends to the outside of the TFT substrate 1 of the liquid crystal display unit. There are proposed a plan of arranging so as to protrude, and a plan of increasing the region length L _s of the diagonal wiring. However, the protruding portion of the TCP from the TFT substrate 1 is disadvantageous in mounting the liquid crystal display unit on the liquid crystal display module, and the protruding terminal connection reliability of the TCP is lowered. Further, the TFT substrate 1 is enlarged in the scanning signal line direction (horizontal direction) only in the protruding portion of the TCP, or the region length L _s of the diagonal wiring is lengthened to enlarge the TFT substrate 1 in the video signal line direction (vertical direction). In many cases, the outer shape of the liquid crystal display module is limited due to its compact design, and cannot be adopted.

An object of the present invention is to prevent the angle and length of diagonal wiring from varying and to reduce the angle of diagonal wiring when the total number of video signal lines in the liquid crystal display is not divisible by the number of TCP outputs. It is to provide a liquid crystal display device that can be suppressed.

Therefore, the wiring can be easily designed, and
An object of the present invention is to provide a liquid crystal display device capable of suppressing the increase / variation in resistance of diagonal wiring, the occurrence of a short circuit failure between diagonal wirings, and preventing the deterioration of the connection reliability of TCP due to the protrusion of TCP from the transparent substrate. .

Further, it is not necessary to enlarge the transparent substrate of the liquid crystal display section, and the TCPs can be arranged at a high density in a compact area, which is advantageous for compact design, and the wiring of the liquid crystal display section and the TC can be improved.
It is to provide a liquid crystal display device that enables high-density connection with P.

[0015]

In order to solve the above-mentioned problems, the present invention is one in which the arrangement of TCP is devised, and the TCPs are arranged at the edges of the horizontal and vertical sides of the transparent substrate of the liquid crystal display section. In a liquid crystal display device having a plurality of TCPs connected to the respective input terminals and arranged at the edges of the horizontal and vertical sides, there is a connection remainder not connected to the input terminals involved in driving the liquid crystal. Provided is a liquid crystal display device in which the TCP having a terminal is arranged at both ends of at least one of the horizontal side and the vertical side.

The present invention also provides the above-mentioned two TCPs at both ends.
There is provided a liquid crystal display device having the same or substantially the same number of terminals as the connection remainder.

The present invention also provides a liquid crystal display device in which the TCPs between the TCPs at both ends are repeatedly arranged at a constant interval.

Further, the present invention provides a liquid crystal display device in which a distance between the TCPs at both ends and the TCPs adjacent to the TCPs is smaller than the constant distance.

[0019]

According to the present invention, the TCP having the extra connection terminals that are not connected to the input terminals of the liquid crystal display section is arranged at both ends of the horizontal side or the vertical side of the liquid crystal display section, and the extra connection terminals are two T terminals.
By allocating the CPs, the connection surplus terminals of the TCP are not concentrated on the TCP at the right end, so that the angle and the length of the diagonal wiring can be prevented from varying and the angle of the diagonal wiring can be prevented from becoming small. Therefore, it is possible to easily design the wiring, suppress the increase / variation of the resistance of the diagonal wiring, and prevent the short circuit between the diagonal wirings from occurring, and prevent the deterioration of the connection reliability of the TCP due to the protrusion of the TCP from the transparent substrate. .
Furthermore, it is not necessary to make the transparent substrate of the liquid crystal display unit large,
It is possible to provide a liquid crystal display device in which TCPs can be arranged at a high density in a compact area, which is advantageous for a compact design, and which enables high-density connection between wirings of the liquid crystal display unit and TCPs.

[0020]

【Example】

(Arrangement of TCP on Video Signal Side Connected to TFT Substrate 1 of Liquid Crystal Display Section) FIG. 1 is a plan view showing the arrangement of TCPs in a liquid crystal display device according to an embodiment of the present invention.

Reference numeral 1 denotes a TFT substrate of the liquid crystal display unit, T ₁ , _{U to} T
_n and _U are upper TCPs on the video signal line side (the central TCP is not shown), and T ₁ , _{L to} T _n , _L are lower Ts on the video signal line side.
CP (the central TCP is not shown), P _t is the pitch of the TCP output terminals, q is the number of outputs of one TCP, L _C is the TCP between the TCPs at both ends (hereinafter referred to as the central TCP)
, L _L is the distance between the leftmost TCP and the TCP adjacent to the right, L _R is the distance between the rightmost TCP and the TCP adjacent to the left, P _c is the pitch of the central TCP, 2d Is the total number of video signal lines, P _d is the pitch of the video signal lines, L _s is the length of the diagonal wiring area, θ is the angle of the diagonal wiring, M / 2 is the number of left-end and right-end TCP connection terminals, and L _r is the length of the connection remainder, 2 is the center of the total number of video signal lines, 3 is the central TCP
Is a center of the video signal line in the repeating block, L _T is a distance of d video signal lines, and L _H is a distance L _T −the length of the connection remainder portion.

The upper n-2 central TCPs (T ₂ , _U ~
T _n-1 , _U ) and the lower n-2 central TCPs (T
₂ , _{L to} T _n-1 , _L ) are repeatedly arranged at a constant pitch P _c . This pitch P _c is set as P _c = 2 × P _d × q.

FIG. 2 is an overall plan view of the TFT substrate of the liquid crystal display device according to the first embodiment of the present invention, and FIG. 3 is an enlarged view of portion A in FIG. FIG. 4 is an overall plan view of the TFT substrate of the liquid crystal display device according to the second embodiment of the present invention.

In the first embodiment, P _c = 2 × 0.204
X160 = 65.28mm, TCP length is 50
mm, L _C = 65.28-50 = 15.28 m
m.

In the second embodiment, P _c = 2 × 0.068
X192 = 26.112mm, TCP length is 22m
m, L _C = 26.112-22 = 4.112 m
m. By setting the pitch P _C of the central TCP in this way, the pattern of the diagonal wiring and the input terminal connected to the central TCP can be formed by repeating n−2 times. The center of the central TCP is made to coincide with the center 3 of the video signal line in the repeating block, and the TCP is transmitted n-2 times.
Is also the center of the total number of video signal lines 2d.
The n−2 central TCPs are repeatedly arranged so as to match This minimizes variations in the angle and length of the diagonal wiring.

Interval L between TCP on both ends and TCP next to it
_L and L _R may be the same as the interval L _C of the central TCP, but by making the intervals L _L and L _R smaller than the interval L _C , the liquid crystal display unit can be made more compact.

The number of TCPs at both ends of the connection surplus terminal is equal to M / 2. The values of the distances L _L and L _R between the TCPs at both ends and the TCPs adjacent to the TCPs are determined so as to ensure the angle θ of the diagonal wiring of a certain value or more.

In the above first embodiment, the intervals L _L , L _R
= 11 mm, the distance L of the video signal lines for d lines
_T is L _T = P _d × d = 0.204 × 560 = 1114.
4 mm, distance L _H (distance L _T − length of connection residual portion L _r ) ≈
7.64 + 50 + 11 + 2.6 + (160-40) ×
0.28 = 104.84 mm. 7.64 is the central TCP pitch L _C / 2, 50 is the TCP length, 11 is the spacing L _L , L _R , 2.6 is the end length of the TCP at both ends, 1
Reference numeral 60 is the number of outputs of one TCP, 40 is the number of terminals of TCP connection remainders at both ends, and 0.28 is the pitch P _t of TCP output terminals. Angle of diagonal wiring θ = arctan (diagonal wiring region length L _s / length of connection residual portion L _r ) = arctan
(4 / (114.24-104.84)) = 23 degrees, and a wireable value is obtained.

As described above, in the above-described embodiment, the TCP having the connection surplus terminal not connected to the input terminal of the liquid crystal display unit is provided on the video signal line side (horizontal side) above and below the liquid crystal display unit. By arranging the terminals on both ends at two ends and allocating the terminals for connection surplus to two TCPs, as shown in FIG. 20, the terminals for connection surplus are not concentrated on the TCP at the right end. It is possible to suppress variations in the angle and to prevent the angle of the diagonal wiring from decreasing. Therefore, the wiring can be easily designed, the resistance of the diagonal wiring can be prevented from increasing or varying, and the short circuit between the diagonal wiring can be prevented from occurring.
It is possible to prevent a decrease in connection reliability. Further, it is not necessary to make the TFT substrate 1 of the liquid crystal display unit large, and the TCPs can be arranged at a high density in a compact area, which is advantageous for a compact design and enables high-density connection between the wirings of the liquid crystal display unit and the TCPs. A liquid crystal display device can be provided.

(Active matrix liquid crystal display device)
An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

FIG. 5 shows an active system to which the present invention is applied.
FIG. 6 is a plan view showing one pixel of the matrix type color liquid crystal display device and its periphery, FIG. 6 is a sectional view taken along section line 3-3 of FIG. 5, and FIG. 7 is a sectional view taken along section line 4-4 of FIG. . Further, FIG. 8 shows a plan view when a plurality of pixels shown in FIG. 5 are arranged.

(Pixel Arrangement) As shown in FIG. 5, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or drain signal lines). The signal line is arranged in an area intersecting with the vertical signal line DL (in an area surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction and are arranged in the row direction. Video signal line DL
Extend in the row direction and are arranged in the column direction.

(Overall Structure of Display Section) As shown in FIG. 6, a thin film transistor TFT and a transparent pixel electrode ITO1 are provided on the lower transparent glass substrate SUB1 side based on the liquid crystal LC.
On the upper transparent glass substrate SUB2 side, a color filter FIL and a light-shielding black matrix pattern B are formed.
M is formed. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm. Further, a silicon oxide film SIO formed by dipping or the like is provided on both surfaces of the transparent glass substrates SUB1 and SUB2. Therefore, the transparent glass substrates SUB1 and SUB
Even if there are sharp scratches on the surface of No. 2, since the sharp scratches can be covered with the silicon oxide film SIO, the film quality of the scanning signal lines GL, the black matrix BM, etc. deposited thereon can be kept uniform. .

Although not shown, a sealant is formed so as to seal the liquid crystal LC along the entire periphery of the transparent glass substrates SUB1 and SUB2 excluding the liquid crystal inlet. The sealing material is made of epoxy resin, for example. Upper transparent glass substrate S
The common transparent pixel electrode ITO2 on the UB2 side is connected to an external lead wire formed on the lower transparent glass substrate SUB1 side by a silver paste material at at least one place. The external lead wiring is formed in the same manufacturing process as the gate terminal GTM and the drain terminal DTM described later.

The orientation films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2, and the respective layers are formed inside the sealing material. Polarizing plates POL1, P
The OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI that sets the orientation of liquid crystal molecules.
1 and the upper alignment film ORI2, and is sealed by a sealing material. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

A black matrix BM, a color filter FIL, a protective film PSV2, and a common transparent pixel electrode I are formed on the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2.
TO2 (COM) and the upper alignment film ORI2 are sequentially stacked and provided.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and then the lower transparent glass substrate SUB1.
And the upper transparent glass substrate SUB2 are overlapped with each other, and the liquid crystal LC is sealed between the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

(Thin Film Transistor TFT) The thin film transistor TFT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large.

The thin film transistor TFT of each pixel is divided into two (plural) in the pixel and is composed of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 is an i-type semiconductor made of a gate electrode GT, a gate insulating film GI, an i-type (intrinsic, conductivity type determination impurity-undoped) amorphous silicon (Si). It has a layer AS, a pair of source electrodes SD1 and a drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

(Gate Electrode GT) The gate electrode GT is shown in FIG.
As shown in (a plan view in which only the second conductive film g2 and the i-type semiconductor layer AS of FIG. 5 are drawn), it is formed in a shape protruding in the vertical direction (upward in FIGS. 5 and 9) from the scanning signal line GL. (T-shaped branch). The gate electrode GT projects so as to extend beyond the active regions of the thin film transistors TFT1 and TFT2. The gate electrodes GT of the thin film transistors TFT1 and TFT2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of the single-layer second conductive film g2. The second conductive film g2 is, for example, an aluminum (Al) film formed by sputtering, and is 1000 to 550.
It is formed with a film thickness of about 0Å. An Al anodic oxide film AOF is provided on the gate electrode GT.

As shown in FIGS. 5, 6 and 9, this gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below).
Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque Al becomes a shadow, and the i-type semiconductor layer AS is not exposed to the backlight light. The conduction phenomenon due to light irradiation, that is, the deterioration of the off-characteristics of the thin film transistor TFT is less likely to occur. The original size of the gate electrode GT is the minimum required to extend between the source electrode SD1 and the drain electrode SD2 (including the alignment margin between the gate electrode GT, the source electrode SD1 and the drain electrode SD2). ) Has a width and its depth length that determines the channel width W is the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the mutual conductance gm. It depends on what you do. Gate electrode G in this liquid crystal display device
The size of T is, of course, larger than the original size described above.

(Scanning Signal Line GL) The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. Also, an Al anodic oxide film AOF is provided on the scanning signal line GL.

(Insulating Film GI) The insulating film GI is used as the gate insulating film of each of the thin film transistors TFT1 and TFT2. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI is, for example, a silicon nitride film formed by plasma CVD, and is formed with a film thickness of 1200 to 2700Å (in this liquid crystal display device, a film thickness of about 2000Å).

(I-type semiconductor layer AS) i-type semiconductor layer AS
Is used as a channel forming region of each of the thin film transistors TFT1 and TFT2 divided as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film and has a thickness of 200 to 2200.
It is formed with a film thickness of Å (in this liquid crystal display device, a film thickness of about 2000 Å).

This i-type semiconductor layer AS is continuously formed by the same plasma CVD apparatus and the same plasma as the formation of the insulating film GI used as a gate insulating film made of Si ₃ N ₄ by changing the components of the supply gas. It is formed without being exposed to the outside from the CVD device. Further, phosphorus (P) for ohmic contact is doped with 2.5% of N (+) type semiconductor layer d.
0 (FIG. 6) is similarly continuously formed with a film thickness of 200 to 500 Å (in this liquid crystal display device, a film thickness of about 300 Å). After that, the lower transparent glass substrate SUB1 is CV
It is taken out from the D device and is N (+) by the photo processing technology.
The type semiconductor layer d0 and the i-type semiconductor layer AS are patterned into independent islands as shown in FIGS. 5, 6 and 9.

As shown in FIGS. 5 and 9, the i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Transparent Pixel Electrode ITO1) Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor operates normally. You can leave it alone because it does. It is rare that defects occur simultaneously in the two thin film transistors TFT1 and TFT2, and the probability of point defects or line defects can be extremely reduced by such a redundancy system. Transparent pixel electrode ITO
1 is composed of the first conductive film d1.
The conductive film d1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering.
The film thickness of 00 to 2000 Å (in this liquid crystal display device, 14
The film thickness is about 00Å).

(Source electrode SD1, drain electrode SD
2) Thin film transistors TFT1 and TF divided into a plurality of parts
Source electrode SD1 and drain electrode SD of T2
2 means i as shown in FIGS. 5, 6 and 10 (a plan view showing only the first to third conductive films d1 to d3 of FIG. 5).
The semiconductor layers AS are provided separately from each other.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially superposing the second conductive film d2 and the third conductive film d3 from the lower layer side in contact with the N (+) type semiconductor layer d0. The second conductive film d2 of the source electrode SD1
The third conductive film d3 is formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.

The second conductive film d2 is formed of a chromium (Cr) film formed by sputtering and has a film thickness of 500 to 1000 Å (in this liquid crystal display device, a film thickness of about 600 Å).
Since the stress increases when the Cr film is formed thicker, the Cr film is formed within the range of about 2000 Å.
The Cr film has good contact with the N (+) type semiconductor layer d0.
The Cr film constitutes a so-called barrier layer that prevents Al of the third conductive film d3 described later from diffusing into the N (+) type semiconductor layer d0. As the second conductive film d2, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used instead of the Cr film.

The third conductive film d3 is formed by sputtering Al and has a thickness of 3000 to 5000 Å (in this liquid crystal display device,
The film thickness is about 4000Å). The Al film has less stress than the Cr film, can be formed to have a thick film thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an Al film containing silicon or copper (Cu) as an additive may be used in addition to the pure Al film.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

The source electrode SD1 is the transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 has the i-type semiconductor layer AS step difference (thickness of the second conductive film g2, thickness of the anodic oxide film AOF, thickness of the i-type semiconductor layer AS, and thickness of the N (+) type semiconductor layer d0. It is configured along a step corresponding to the added film thickness). Specifically, the source electrode SD1 is the second conductive film d2 formed along the step of the i-type semiconductor layer AS.
And the third conductive film d formed on the second conductive film d2.
3 and 3. The third conductive film d3 of the source electrode SD1 cannot be formed thick due to the increased stress of the Cr film of the second conductive film d2 and cannot overcome the step shape of the i-type semiconductor layer AS. Is configured for. That is, the step coverage is improved by forming the third conductive film d3 thick. Since the third conductive film d3 can be formed thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

(Protective film PSV1) Thin film transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

(Light-shielding film BM) Upper transparent glass substrate SUB
A light-shielding film BM is provided on the second side so that external light (light from above in FIG. 6) does not enter the i-type semiconductor layer AS used as a channel formation region.
The pattern is as shown by hatching 1. Note that FIG. 11 is a plan view showing only the first conductive film d1 made of the ITO film, the color filter FIL, and the light shielding film BM in FIG.

Therefore, the thin film transistors TFT1 and
The i-type semiconductor layer AS of the TFT 2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 11, that is, the light-shielding film BM is formed in a grid shape (black matrix), and the effective display area of one pixel is partitioned by this grid. There is. Therefore,
The contour of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

A portion facing the edge portion of the transparent pixel electrode ITO1 on the base side in the rubbing direction (lower right portion in FIG. 5).
Since the light is shielded by the light shielding film BM, even if a domain is generated in the above portion, the domain cannot be seen, so that the display characteristics are not deteriorated.

The backlight may be attached to the upper transparent glass substrate SUB2 side and the lower transparent glass substrate SUB1 may be the observation side (externally exposed side).

The light-shielding film BM may be formed of a metal film such as Cr or an organic material such as acrylic resin.

(Color Filter FIL) The color filter FIL is constructed by coloring a dyeing base material made of a resin material such as acrylic resin with a dye. Color filter F
The ILs are formed in stripes at positions facing the pixels (FIG. 12) and are dyed separately (FIG. 12 is the first in FIG. 8).
Conductive film d1, light-shielding film BM and color filter FIL
(B, R, G color filters FIL are 45 °, 135 °, and cross hatched, respectively). The color filter FIL is shown in FIGS.
As shown in FIG. 5, the light-shielding film BM is formed to have a large size so as to cover all of the transparent pixel electrode ITO1, and the light-shielding film BM includes
The transparent pixel electrode ITO1 is formed inside the peripheral portion of the transparent pixel electrode ITO1 so as to overlap with the edge portion of the transparent pixel electrode ITO1.

(Protective Film PSV2) In the protective film PSV2, the liquid crystal L is a dye in which the color filter FIL is dyed in different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. The common voltage Vcom is an intermediate potential between the low level drive voltage Vdmin and the high level drive voltage Vdmax applied to the video signal line DL.

(Gate Terminal GTM) FIG. 13 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, where (A) is a plane (B).
Shows a cross section taken along the line BB of (A). It should be noted that this figure shows the substrate SUB based on the matrix of FIG.
1 shows the vicinity of the left end of 1.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view, its locus remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. Anodized A
The oxide Al ₂ O ₃ film AOF is formed on the surface of the L layer g2, and the volume of the conductive portion therebelow is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. As described above, the mask pattern AO does not intersect the scanning line GL with a single straight line, but is bent in a crank shape and intersects with it.

In the figure, the AL layer g2 is hatched for easy understanding, but the region which is not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the Al layer is wide. Therefore, by narrowing the width of each one and arranging a plurality of them in parallel, whiskers can be prevented and wire breakage can be prevented. The aim is to minimize the probability of and the sacrifice of conductivity. Therefore, in this example, the portion corresponding to the base of the comb is also displaced along the mask AO.

The gate terminal GTM is composed of a silicon oxide SIO layer and a Cr layer g1 having a good adhesive property, and a transparent conductive layer d1 having the same level (same layer, simultaneously formed) as the pixel electrode ITO1 for protecting the surface thereof. There is. In addition, the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have their regions so that the conductive layers g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive layers d3 and d2. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located at the left end is formed.
Are exposed from them to allow electrical contact with external circuitry. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically, and the left end of the gate terminal in the figure is
During the manufacturing process, it is extended and shorted beyond the cut area of the substrate. Such a short circuit in the manufacturing process is useful for supplying power during anodization and preventing electrostatic breakdown during rubbing of the alignment film ORI1.

(Drain Terminal DTM) FIG. 14 is a diagram showing the connection from the video signal line DL to the external connection terminal DTM, (A) shows the plane, and (B) shows B of (A).
-B shows a cross section taken along the line B. This figure shows the upper end and the lower end of the substrate SUB1 based on the matrix of FIG. 8, and although the direction is changed for convenience, the left end direction corresponds to the upper end or the lower end of the substrate SUB1.

TSTd is an inspection terminal, and no external circuit is connected to it. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the substrate SUB1 as shown in the figure. Further extended beyond the cutting line of the substrate SUB1,
During the manufacturing process, all of them are short-circuited to each other to prevent electrostatic breakdown. In the figure, the video signal line D in which the inspection terminal TSTd exists
The drain connection terminal is connected to the opposite side across the matrix of L, and conversely the inspection terminal is connected to the opposite side across the matrix of the video signal line DL in which the drain connection terminal DTM exists. The drain connection terminal DTM is For the same reason as the above-mentioned gate terminal GTM, it is formed of two layers of the Cr layer g1 and the ITO layer d1, and is connected to the video signal line DL at the portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. Terminal DTM
In the above, the protective film PSV1 is, of course, removed in order to connect to the external circuit. AO is the anodizing mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with the mask, but the layer g2 is covered in the part not covered in this figure. This pattern is not directly relevant as it does not exist.

(Structure of Storage Capacitance Element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. In this superposition, as is apparent from FIG. 7, the transparent pixel electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode PL.
A holding capacitance element (electrostatic capacitance element) Cadd which is 1 is configured. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I and the anodic oxide film AOF.

As is clear from FIG. 9, the storage capacitor element Cadd is formed in the portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL. Storage capacitor element C
In the step portion of the electrode PL1 of add, the transparent pixel electrode ITO
Even if 1 is disconnected, the defect is compensated by the island region formed by the second conductive film d2 and the third conductive film d3 formed so as to cross the step. This island region is formed as small as possible so as not to reduce the aperture ratio.

(Equivalent Circuit of Entire Display) FIG. 15 shows a connection diagram of an equivalent circuit of the display matrix section and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device for displaying information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source. It is a circuit including a circuit for exchanging information for use.

(Equivalent circuit of holding capacitance element Cadd and its operation) FIG. 16 shows an equivalent circuit of the pixel shown in FIG. In FIG. 16, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film having the parasitic capacitance Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is a transparent pixel electrode ITO
A liquid crystal capacitor formed between 1 (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitance Cpix is the liquid crystal LC, the protective film PSV1 and the alignment film ORI.
1 and ORI2. Vlc is the midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This can be expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents the change amount of the midpoint potential due to ΔVg. This variation ΔVlc causes a direct current component added to the liquid crystal LC, but the larger the holding capacitance Cadd, the more
The value can be reduced. Further, the storage capacitor element Cadd also has a function of prolonging the discharge time, and stores the image information for a long time after the thin film transistor TFT is turned off. The reduction of the direct current component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and the parasitic capacitance Cgs is increased accordingly. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, the storage capacitor Cadd
By providing the above, this demerit can be eliminated.

The holding capacitance of the holding capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

(Method of Connecting Retention Capacitance Element Cadd Electrode Wire)
The first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is connected to the common transparent pixel electrode ITO2 (Vcom) as shown in FIG. As described above, the common transparent pixel electrode ITO2 of the substrate SUB2 is formed of the silver paste material on the substrate SUB1 in the peripheral portion of the liquid crystal display device.
Since the first stage scanning signal line GL (Y ₀ ) is connected to the external lead-out wiring of the substrate SUB1, it may be connected to the external lead-out wiring. Alternatively, the storage capacitor electrode line Y ₀ in the first stage is connected to the scanning signal line Yend in the final stage and is connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y ₀ from the vertical scanning circuit V. You may connect to receive.

(Manufacturing Method) Next, a manufacturing method of the substrate SUB1 side of the above-mentioned liquid crystal display device will be described with reference to FIGS.
Will be described with reference to. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 6, and the right side shows the processing flow seen in the sectional shape near the gate terminal shown in FIG. Except for the step D, steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage after the photo process is finished and the photoresist is removed. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 17 After a silicon oxide film SIO is formed on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by a dip process, baking is performed at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line (not shown) connecting the gate terminal GTM, the bus line (not shown) short-circuiting the drain terminal DTM, and the anode connected to the anodized bus line. Form an oxide pad (not shown).

Step B, FIG. 17 Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Are provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step C, FIG. 17 After photographic processing (after forming the above-mentioned anodic oxidation mask AO), 3
Substrate SUB1 is immersed in an anodizing solution consisting of a solution prepared by diluting 1% of tartaric acid with ammonia to pH 6.25 ± 0.05 with ethylene glycol solution, and the formation current density is 0.5 mA / cm. ² so as to adjust (constant current Kasei). Next, anodic oxidation is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized,
An anodic oxide film AOF having a film thickness of 1800Å is formed on the scanning signal line GL, the gate electrode GT and the electrode PL1 Step D, FIG. 18 Ammonia gas, silane gas and nitrogen gas are introduced into the plasma CVD apparatus to make the film thickness A 2000 Å Si nitride film is provided, and silane gas and hydrogen gas are introduced into the plasma CVD device to form an i-type amorphous Si film with a film thickness of 2000 Å, then hydrogen gas and phosphine gas are introduced into the plasma CVD device. Then, an N (+) type amorphous Si film having a film thickness of 300Å is provided.

Step E, FIG. 18 After photo processing, SF ₆ and CC as dry etching gas are used.
Use l ₄ N (+) type amorphous Si film, i-type amorphous Si
The island of the i-type semiconductor layer AS is formed by selectively etching the film.

Step F, FIG. 18 After the photo processing, SF ₆ is used as a dry etching gas to selectively etch the Si nitride film.

Step G, FIG. 19 A first conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H, FIG. 19 A second conductive film d2 made of Cr having a film thickness of 600 Å is provided by sputtering, and further, an Al- film having a film thickness of 4000 Å is formed.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as the process B, and the second conductive film d2 is etched with the same liquid as the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, by introducing CCl ₄ and SF ₆ into the dry etching apparatus, N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 19 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 1 μm. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique using SF ₆ as a dry etching gas.

(Modification) In the above-described embodiment, the photoresist pattern on the Al gate wiring is formed in a crank shape, but it is not limited to this shape. In short, when peeling occurs in the hot pattern and progresses, it may be formed of a rectangle, a triangle, a circle, a trapezoid, or the like alone or in combination as long as it stops the peeling.

(Application range) The invention made by the present inventor has been specifically described based on the embodiments. However, the invention is not limited to the embodiments and does not depart from the gist of the invention. Needless to say, various changes can be made in.

For example, the liquid crystal display device in which the greatest mass-production effect can be expected has been described in the above embodiment, but the present invention is not limited to this, and a thin film device such as a contact photosensor using a thin film transistor or an electroluminescent display device. Can also be applied to.

In addition, the above-mentioned first and second shown in FIGS.
In the embodiment described above, the example applied to the TCP on the video signal side arranged on the upper and lower two sides of the liquid crystal display section is shown.
TC on the scanning signal side arranged on one vertical side of the liquid crystal display unit
It may be applied to P.

Further, although the above-mentioned embodiment shows the example applied to the active matrix type liquid crystal display device, the present invention can also be applied to the simple matrix type liquid crystal display device, and the simple matrix type liquid crystal device. It can be applied to at least one of the segment side and the common side of the display device.

[0098]

As described above, according to the present invention, TCPs having terminals for connection surplus are arranged at both ends of the horizontal side or the vertical side of the liquid crystal display portion, and the connection surplus is allocated to two TCPs. , The connection surplus of TCP is not concentrated on the TCP at the right end, so that the angle and length of the diagonal wiring can be prevented from varying, and the angle of the diagonal wiring can be prevented from becoming small. Therefore, it is possible to easily design the wiring, suppress the increase / variation of the resistance of the diagonal wiring, and prevent the short circuit between the diagonal wirings from occurring, and prevent the deterioration of the connection reliability of the TCP due to the protrusion of the TCP from the transparent substrate. . In addition, the transparent substrate of the liquid crystal display unit does not have to be large, which is advantageous for compact design, TCPs can be arranged in high density in a compact area, and liquid crystal display lines and TCPs can be connected at high density. A display device can be provided.

[Brief description of drawings]

FIG. 1 is a plan view showing how TCPs are arranged in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a TFT of the liquid crystal display device according to the first embodiment of the present invention.
It is an overall plan view of the substrate.

FIG. 3 is an enlarged view of part A of FIG.

FIG. 4 is a TFT of a liquid crystal display device according to a second embodiment of the present invention.
It is an overall plan view of the substrate.

FIG. 5 is a main-portion plan view showing one pixel and its periphery of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied.

6 is a cross-sectional view showing one pixel and its periphery under the section line 3-3 in FIG.

7 is a cross-sectional view of the additional capacitance Cadd taken along the line 4-4 in FIG.

8 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 5 are arranged.

9 is a plan view illustrating only layers g2 and AS of the pixel shown in FIG.

10 is a plan view illustrating only layers d1, d2 and d3 of the pixel shown in FIG.

11 is a plan view showing only a pixel electrode layer, a light shielding film and a color filter layer of the pixel shown in FIG.

FIG. 12 is a plan view of relevant parts showing only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG.

FIG. 13 is a plan view and a cross-sectional view showing the vicinity of a connecting portion between a gate terminal GTM and a gate line GL to which the present invention is applied.

FIG. 14 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 15 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device.

16 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 17 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 18 is a flow chart of a cross-sectional view of the pixel portion and the gate terminal portion showing the manufacturing steps of steps D to F on the side of the substrate SUB1.

FIG. 19 is a flow chart of a cross-sectional view of the pixel portion and the gate terminal portion showing the manufacturing steps of steps GI on the side of the substrate SUB1.

FIG. 20 is a plan view showing the arrangement of TCPs in a conventional liquid crystal display device.

[Explanation of symbols]

1 ... TFT substrate T ₁ of the liquid crystal display unit, _U ~T _{n, U} ... video signal line side upper _{TCP T 1, L ~T n,} L ... of the lower image signal line side of the TCP P _t ... TCP Pitch of output terminals q ... Number of outputs of one TCP L _C ... Interval between central TCP _LL ... Interval between leftmost TCP and its right adjacent TCP _LR ... Rightmost TCP and its left adjacent angle M / 2 ... both ends in the longitudinal theta ... oblique wiring pitch L _s ... diagonal interconnect region of the total number P _d ... video signal lines of a pitch 2d ... video signal lines spacing P _c ... center of TCP between TCP number of output terminals of TCP-odd connected L _r ... video signal of the center L _T ... d duty of the video signal lines in the repeat block of the center 3 ... central TCP of the total number of connections odd portions of length 2 ... video signal lines distance L _H ... distance line L _T - connecting more than part of the length L _r.

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[Procedure amendment]

[Submission date] December 8, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 20

[Correction method] Change

[Correction content]

FIG. 20

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuyuki Ishige, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Shunichi Kumaoka 3300, Hayano, Mobara-shi, Chiba Hitachi Ltd. ) Inventor Kenkichi Suzuki 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd. Mobara factory

Claims (4)

[Claims] 1. A transparent substrate of a liquid crystal display unit, which is connected to each of the input terminals arranged on the edges of the horizontal and vertical sides and arranged on the edges of the horizontal and vertical sides. Multiple TCs
In a liquid crystal display device having P, a liquid crystal display characterized in that the TCP having a connection residual terminal that is not connected to the input terminal involved in driving the liquid crystal is arranged at both ends of at least one of the horizontal side and the vertical side. apparatus. 2. The number of terminals of the connection surplus of the two TCPs at both ends is the same or substantially equal to each other.
The described liquid crystal display device. 3. The liquid crystal display device according to claim 1, wherein the TCPs between the TCPs at both ends are repeatedly arranged at a constant interval. 4. The liquid crystal display device according to claim 3, wherein a distance between the TCPs at both ends and the TCPs adjacent to the TCPs is smaller than the predetermined distance.