JPH0613521A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0613521A
JPH0613521A JP16877692A JP16877692A JPH0613521A JP H0613521 A JPH0613521 A JP H0613521A JP 16877692 A JP16877692 A JP 16877692A JP 16877692 A JP16877692 A JP 16877692A JP H0613521 A JPH0613521 A JP H0613521A
Authority
JP
Japan
Prior art keywords
solder
semiconductor device
external electrode
view
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16877692A
Other languages
Japanese (ja)
Inventor
Minoru Kawabe
實 川邉
Hiroaki Kamiura
宏明 上浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP16877692A priority Critical patent/JPH0613521A/en
Publication of JPH0613521A publication Critical patent/JPH0613521A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a solder-dip semiconductor device which can be soldered to a board of electric apparatuses in a stable manner. CONSTITUTION:A groove 4a is provided on an outside electrode 2 of a semiconductor device so that stabilized soldering may be performed by forming a solder fillet which comprises a solder which treats a land electrode for an electric apparatus and solders 3 and 5 which treat the outside electrode 2 for the semiconductor device.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置を電気機器
の基板に実装する際に、半導体装置の外部電極と基板の
ランド電極に安定した半田フィレットを形成することが
できる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of forming a stable solder fillet on an external electrode of the semiconductor device and a land electrode of the substrate when the semiconductor device is mounted on a substrate of electric equipment.

【0002】[0002]

【従来の技術】近年、産業界の動向として、半導体装置
を電気機器の基板に実装する方法は、リフロー半田によ
る面実装が主流となっている。なお、リフロー半田に使
用する半田の量はコスト面、環境面等により減少方向に
ある。
2. Description of the Related Art In recent years, as a trend in the industrial world, surface mounting by reflow soldering has become the mainstream method of mounting a semiconductor device on a substrate of electric equipment. The amount of solder used for the reflow solder is decreasing due to cost, environment and the like.

【0003】半導体装置の外部電極には予め半田を付け
ているが、その形成方法は一般的にメッキによる半田処
理(半田メッキ)と、半田槽等で溶融した半田の中に浸
漬する半田処理(半田ディップ)がある。
Solder is preliminarily attached to the external electrodes of the semiconductor device. The forming method is generally soldering by plating (solder plating) and soldering by immersing in molten solder in a solder bath or the like ( There is a solder dip).

【0004】従来の半導体装置完成品を図5に示す。図
5(a)は半導体装置の正面図であり、半導体素子を封
止したパッケージ1と、半導体素子とつながる外部電極
2からなる。
FIG. 5 shows a conventional finished semiconductor device. FIG. 5A is a front view of the semiconductor device, which includes a package 1 encapsulating a semiconductor element and an external electrode 2 connected to the semiconductor element.

【0005】図5(b)は図5(a)の斜視図である。
図5(c)は図5(a)のA−B線に沿った外部電極2
の断面図である。ここで、外部電極2を半田ディップ処
理した場合、外部電極2のエッジと側面部分に半田3が
薄く付く。
FIG. 5 (b) is a perspective view of FIG. 5 (a).
FIG. 5C shows the external electrode 2 taken along the line AB of FIG.
FIG. Here, when the external electrode 2 is subjected to the solder dip treatment, the solder 3 is thinly attached to the edge and the side surface portion of the external electrode 2.

【0006】[0006]

【発明が解決しようとする課題】しかし、前記従来の構
成では、半導体装置を電気機器の基板へ安定に実装する
ために、半導体装置の外部電極2の表面に一定厚(5〜
10μm程度)の半田3を均一に付けておく必要があ
る。半田メッキであれば、外部電極2に一定の厚みで均
一な半田3を付けることが可能である。しかし、半田デ
ィップは半田3の性質上、外部電極2のエッジと側面に
薄く付く。従って、半田ディップによる半導体装置は電
気機器の基板に安定な実装ができないという問題を有し
ている。
However, in the above conventional structure, in order to stably mount the semiconductor device on the substrate of electric equipment, the external electrode 2 of the semiconductor device has a constant thickness (5 to 5 mm) on the surface thereof.
It is necessary to uniformly apply the solder 3 of about 10 μm). With solder plating, it is possible to apply the uniform solder 3 to the external electrode 2 with a constant thickness. However, due to the nature of the solder 3, the solder dip is thinly attached to the edges and side surfaces of the external electrode 2. Therefore, the semiconductor device using the solder dip has a problem that it cannot be stably mounted on the substrate of the electric device.

【0007】本発明は、電気機器の基板に安定して実装
ができる半田ディップによる半導体装置を提供すること
を目的とする。
It is an object of the present invention to provide a solder dip semiconductor device which can be stably mounted on a substrate of electric equipment.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体装置は、パッケージと、前記パッケ
ージから伸びた外部電極とを備え、前記外部電極の基板
と接触する先端部に凹凸構造を有している。
In order to achieve the above object, a semiconductor device of the present invention comprises a package and an external electrode extending from the package, and a concavo-convex structure is formed on a tip portion of the external electrode which comes into contact with a substrate. have.

【0009】[0009]

【作用】本発明の構成によれば、外部電極に溝、くぼ
み、穴等の凹凸を備えることにより、溶融した半田の性
質上、外部電極に備えた凹凸に半田が溜まる構造と、半
導体装置外部電極と電気機器の基板ランド電極に処理し
ている半田との接触面を広くして、半田付き性を良くす
る構造を備えるものであり、半導体装置を安定に電気機
器の基板へ実装することが可能である。
According to the structure of the present invention, since the external electrodes are provided with irregularities such as grooves, dents, holes, etc., due to the nature of the molten solder, the structure in which the solder is accumulated in the irregularities provided on the external electrodes, It has a structure that improves the solderability by widening the contact surface between the electrode and the solder that is processed on the board land electrode of the electric device, so that the semiconductor device can be stably mounted on the board of the electric device. It is possible.

【0010】[0010]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0011】ただし、図は本発明の特徴を説明するた
め、正面図と斜視図については、外部電極の半田状態は
記載していない。
However, in order to explain the features of the present invention, the soldering state of the external electrodes is not shown in the front view and the perspective view.

【0012】図1は、本発明の一実施例における半導体
装置を示し、図1(a)が正面図、図1(b)が斜視
図、図1(c)が図1(a)のA−B線に沿った外部電
極の断面図である。
FIG. 1 shows a semiconductor device according to an embodiment of the present invention. FIG. 1 (a) is a front view, FIG. 1 (b) is a perspective view, and FIG. 1 (c) is A of FIG. 1 (a). FIG. 7 is a cross-sectional view of the external electrode taken along the line B.

【0013】図1において、半導体装置は半導体素子を
封止したパッケージ1と、半導体素子とつながる外部電
極2からなり、外部電極2の先端上部に溝4aを有す
る。本実施例では、電気機器の基板ランド電極に処理さ
れている半田3と、半導体装置の外部電極2の半田3
が、リフロー半田時に安定したフィレットを形成するた
めに、溝4aを外部電極2に形成している。溝4aは、
外部電極2を製造する段階で機械的、または化学的に形
成される。
In FIG. 1, the semiconductor device comprises a package 1 encapsulating a semiconductor element and an external electrode 2 connected to the semiconductor element, and a groove 4a is provided at the upper end of the external electrode 2. In this embodiment, the solder 3 that is processed on the board land electrode of the electric device and the solder 3 of the external electrode 2 of the semiconductor device.
However, the groove 4a is formed in the external electrode 2 in order to form a stable fillet during reflow soldering. The groove 4a is
The external electrode 2 is mechanically or chemically formed during the manufacturing process.

【0014】溝4aは外部電極2の先端部分で、半導体
装置設置時に平坦となる領域に形成されている。その形
状は、図1(c)に見られるようにその断面形状は三角
形に形成されている。
The groove 4a is a tip portion of the external electrode 2 and is formed in a region which becomes flat when the semiconductor device is installed. As shown in FIG. 1C, the shape is triangular in cross section.

【0015】このように、溝4aを外部電極2に形成し
ておくと、半田ディップ時に溝4aに半田5が溜る。こ
の溝4aと半田5は、リフロー半田の際、電気機器のラ
ンド電極に処理されている半田と外部電極2の半田付き
性を良くする構成となっているので、安定した半田フィ
レットを形成することができる。言い替えれば、溝4a
と半田5はリフロー半田の際、電気機器の基板ランド電
極に処理されている半田5を外部電極2の上に引き上げ
る構成となっている。
When the groove 4a is formed in the external electrode 2 as described above, the solder 5 is accumulated in the groove 4a during the solder dip. Since the groove 4a and the solder 5 are configured to improve the solderability of the external electrode 2 with the solder that has been processed to the land electrode of the electric device during reflow soldering, it is necessary to form a stable solder fillet. You can In other words, the groove 4a
The solder 5 and the solder 5 are configured to pull up the solder 5 processed on the board land electrode of the electric device onto the external electrode 2 during the reflow soldering.

【0016】図2(a),(b),(c)、図3
(a),(b),(c)、および図4(a),(b),
(c)に他の実施例を示す。それぞれの図は、図1で説
明した溝を孔、欠け等に置き替えているものであり、構
成は図1と同様である。また、対応する部分には同じ符
号が付されている。
2 (a), (b), (c) and FIG.
(A), (b), (c), and FIGS. 4 (a), (b),
(C) shows another embodiment. In each drawing, the groove described in FIG. 1 is replaced with a hole, a chip or the like, and the configuration is the same as that in FIG. Further, the same reference numerals are given to corresponding parts.

【0017】図2では、くぼみ4bは外部電極2の先端
部分に形成されている。その形状は図2(a)に見られ
るように半円形に形成されている。
In FIG. 2, the recess 4 b is formed at the tip of the external electrode 2. The shape is formed in a semicircular shape as seen in FIG.

【0018】本実施例のくぼみ4bを外部電極2に形成
しておくと、半田ディップ時にくぼみ4bに半田5が溜
る。このくぼみ4bと半田5は、リフロー半田の際、電
気機器のランド電極に処理されている半田と外部電極2
の半田付き性を良くする構成となっているので、安定し
た半田フィレットを形成することができる。
If the recess 4b of this embodiment is formed in the external electrode 2, the solder 5 will collect in the recess 4b during solder dipping. The recess 4b and the solder 5 are the solder and the external electrode 2 which have been treated as the land electrode of the electric device during the reflow soldering.
Since it has a structure for improving the solderability, the stable solder fillet can be formed.

【0019】図3では、外部電極2の両端部分にくぼみ
4bが形成されている。くぼみ4bは外部電極2が折り
曲げられ、半導体装置設置時に平坦となる領域に形成さ
れている。その形状は図3(a)に見られるようにその
断面形状は半円形が外部電極2の両端に形成されてい
る。
In FIG. 3, recesses 4b are formed at both ends of the external electrode 2. The recess 4b is formed in a region where the external electrode 2 is bent and becomes flat when the semiconductor device is installed. As shown in FIG. 3A, the shape is a semicircular cross section formed at both ends of the external electrode 2.

【0020】本実施例のくぼみ4bを外部電極2に形成
しておくと、半田ディップ時にくぼみ4bに半田5が溜
る。このくぼみ4bと半田5は、リフロー半田の際、電
気機器のランド電極に処理されている半田と外部電極2
の半田付き性を良くする構成となっているので、安定し
た半田フィレットを形成することができる。
When the recess 4b of this embodiment is formed in the external electrode 2, the solder 5 is accumulated in the recess 4b during solder dipping. The recess 4b and the solder 5 are the solder and the external electrode 2 which have been treated as the land electrode of the electric device during the reflow soldering.
Since it has a structure for improving the solderability, the stable solder fillet can be formed.

【0021】図4では、円形にくり抜かれた穴4cが外
部電極2の折り曲げられ、半導体装置設置時に平坦とな
る領域に形成されている。
In FIG. 4, a hole 4c that is hollowed out in a circle is formed in a region where the external electrode 2 is bent and becomes flat when the semiconductor device is installed.

【0022】本実施例の穴4cを外部電極2に形成して
おくと、半田ディップ時に穴4cに半田5が溜る。この
穴4cと半田5は、リフロー半田の際、電気機器のラン
ド電極に処理されている半田と外部電極2の半田付き性
を良くする構成となっているので、安定した半田フィレ
ットを形成することが出来る。
When the hole 4c of this embodiment is formed in the external electrode 2, the solder 5 is accumulated in the hole 4c during the solder dip. Since the holes 4c and the solder 5 are configured to improve the solderability of the external electrode 2 with the solder treated on the land electrode of the electric device at the time of reflow soldering, a stable solder fillet should be formed. Can be done.

【0023】溝、くぼみ、穴等の数を上記に説明した実
施例より増やすことにより、実施例の効果を更に顕著に
することが可能であり、半田メッキをする半導体装置に
も利用が可能である。
By increasing the number of grooves, depressions, holes, etc., as compared with the above-described embodiment, the effect of the embodiment can be made more remarkable, and it can be used in a semiconductor device for solder plating. is there.

【0024】[0024]

【発明の効果】以上説明したように、本発明による溝、
くぼみ、穴等の凸、凹を半導体装置の外部電極に形成す
ると、半田ディップをした半導体装置の外部電極が電気
機器の基板ランド電極と安定した半田フィレットを形成
することが可能となる。
As described above, the groove according to the present invention,
By forming protrusions and depressions such as dents and holes in the external electrodes of the semiconductor device, it becomes possible for the external electrodes of the semiconductor device having the solder dip to form a stable solder fillet with the board land electrodes of the electric device.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は本発明の半導体装置の一実施例の正面
図 (b)はその斜視図 (c)は(a)のA−B線に沿った断面図
1A is a front view of an embodiment of a semiconductor device of the present invention, FIG. 1B is a perspective view thereof, and FIG. 1C is a sectional view taken along the line AB of FIG.

【図2】(a)は本発明の半導体装置の他の実施例の正
面図 (b)はその斜視図 (c)は(a)のA−B線に沿った断面図
2A is a front view of another embodiment of the semiconductor device of the present invention, FIG. 2B is a perspective view thereof, and FIG. 2C is a cross-sectional view taken along the line AB of FIG.

【図3】(a)は本発明の半導体装置のさらに他の実施
例の正面図 (b)はその斜視図 (c)は(a)のA−B線に沿った断面図
3A is a front view of yet another embodiment of the semiconductor device of the present invention, FIG. 3B is a perspective view thereof, and FIG. 3C is a sectional view taken along the line AB of FIG.

【図4】(a)は本発明の半導体装置のさらに他の実施
例の正面図 (b)はその斜視図 (c)は(a)のA−B線に沿った断面図
4A is a front view of yet another embodiment of the semiconductor device of the present invention, FIG. 4B is a perspective view thereof, and FIG. 4C is a sectional view taken along the line AB of FIG.

【図5】(a)は従来の半導体装置の正面図 (b)はその斜視図 (c)は(a)のA−B線に沿った断面図5A is a front view of a conventional semiconductor device, FIG. 5B is a perspective view thereof, and FIG. 5C is a cross-sectional view taken along line AB of FIG.

【符号の説明】[Explanation of symbols]

1 パッケージ 2 外部電極 3 半田 4a 溝 4b くぼみ 4c 穴 5 半田 1 Package 2 External Electrode 3 Solder 4a Groove 4b Recess 4c Hole 5 Solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】パッケージと、前記パッケージから伸びた
外部電極とを備え、前記外部電極の基板と接触する先端
部に凹凸構造を有していることを特徴とする半導体装
置。
1. A semiconductor device comprising a package and an external electrode extending from the package, wherein a tip portion of the external electrode in contact with the substrate has an uneven structure.
JP16877692A 1992-06-26 1992-06-26 Semiconductor device Pending JPH0613521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16877692A JPH0613521A (en) 1992-06-26 1992-06-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16877692A JPH0613521A (en) 1992-06-26 1992-06-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0613521A true JPH0613521A (en) 1994-01-21

Family

ID=15874255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16877692A Pending JPH0613521A (en) 1992-06-26 1992-06-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0613521A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184024A (en) * 1987-08-13 1991-08-12 Toray Ind Inc Organic nonlinear material
US5647124A (en) * 1994-04-25 1997-07-15 Texas Instruments Incorporated Method of attachment of a semiconductor slotted lead to a substrate
JP2001127419A (en) * 1999-10-26 2001-05-11 Nec Saitama Ltd Method for positioning terminal and land
JP2007053008A (en) * 2005-08-18 2007-03-01 Sumitomo Wiring Syst Ltd Connector for board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184024A (en) * 1987-08-13 1991-08-12 Toray Ind Inc Organic nonlinear material
US5647124A (en) * 1994-04-25 1997-07-15 Texas Instruments Incorporated Method of attachment of a semiconductor slotted lead to a substrate
US6040623A (en) * 1994-04-25 2000-03-21 Texas Instruments Incorporated Slotted lead for a semiconductor device
JP2001127419A (en) * 1999-10-26 2001-05-11 Nec Saitama Ltd Method for positioning terminal and land
JP2007053008A (en) * 2005-08-18 2007-03-01 Sumitomo Wiring Syst Ltd Connector for board

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