JPH0613485A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPH0613485A
JPH0613485A JP3223986A JP22398691A JPH0613485A JP H0613485 A JPH0613485 A JP H0613485A JP 3223986 A JP3223986 A JP 3223986A JP 22398691 A JP22398691 A JP 22398691A JP H0613485 A JPH0613485 A JP H0613485A
Authority
JP
Japan
Prior art keywords
pellet
semiconductor device
plate
metal plate
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3223986A
Other languages
Japanese (ja)
Inventor
Kenichi Nakura
健一 那倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP3223986A priority Critical patent/JPH0613485A/en
Publication of JPH0613485A publication Critical patent/JPH0613485A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain the method of manufacturing a P. PGA type semiconductor device capable of using solder or a gold-silicon eutectic by a method wherein a pellet is fitted into a plate of which the surface is treated and which is made of ceramic or metal with the solder or gold-silicon eutectic, and this plate is fitted onto a sub strate. CONSTITUTION:After a pellet 1 is fitted onto a ceramic or metal plate 2 for fitting the pellet 1 thereon with adhesives such as gold-silicon eutectic, solder 3, or the like, the metal plate 2 or the ceramic plate are fitted onto the base 4 of plastic. Thus, as the metal plate is fitted onto the base before a pellet fitting plate or the metal plate is fitted thereon, the pellet can be fitted thereon at a high temparature and a semiconductor device having a low heat resistance can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
係り、特にペレット取付け部に金属あるいはセラミック
を使用するプラスチックタイプのピン・グリッド・アレ
イ（以下Ｐ．ＰＧＡという）に適用して有効な技術に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is particularly effective when applied to a plastic type pin grid array (hereinafter referred to as P.PGA) using a metal or ceramic for a pellet mounting portion. It is about technology.

【０００２】[0002]

【従来の技術】近年、半導体装置の高集積化が進み、そ
れに伴ってパッケ−ジも多ピン化が進んでいる。多ピン
化に適したものにセラミックベ−スにピンを取り付けた
ものを使用するピン・グリッド・アレイ（以下ＰＧＡと
いう）ものがある。耐質性の優れたＰＧＡは多ピン化が
可能のため、ゲ−トアレイ等の高集積化された半導体装
置に適しているが、セラミックを使用しているためその
単価が高く、耐質性を必要とする装置に主として使用さ
れる他、あまり広範囲には使用されていない。このよう
な状況で、最近は耐質性をＰＧＡほど必要としない半導
体装置に適用するため、ガラスエポキシ樹脂を主とした
プラスチックをベ−スに使用したものが開発され、プラ
スチック・ピン・グリッド・アレイ（以下ＰＰＧＡとい
う）として使用されている。このようなものを示したも
のとして１９８７年８月号 「日経マイクロデバイセ
ズ」日経マグロウヒル社刊 第５７頁〜第６８頁があ
る。現在ではこのようなもののペレット取付け部に熱抵
抗を改善するために銅等の金属板を設けたものが使用さ
れるようになってきている。2. Description of the Related Art In recent years, semiconductor devices have been highly integrated, and accordingly, the number of pins of packages has been increased. One suitable for increasing the number of pins is a pin grid array (hereinafter referred to as PGA) that uses a ceramic base with pins attached. PGA, which has excellent durability, is suitable for highly integrated semiconductor devices such as gate arrays because it can have a large number of pins, but since it uses ceramics, its unit price is high and the durability is high. In addition to being used primarily for equipment that needs it, it is not widely used. Under these circumstances, in recent years, in order to apply it to a semiconductor device that does not require as high resistance as PGA, a plastic using a glass epoxy resin as a base has been developed. It is used as an array (hereinafter referred to as PPGA). As an example showing such a case, there is an August 1987 issue of "Nikkei Micro Devices", pages 57 to 68, published by Nikkei McGraw-Hill. Nowadays, a pellet mounting portion provided with a metal plate of copper or the like has been used in order to improve thermal resistance.

【０００３】[0003]

【発明が解決しようとする課題】しかし、上記したよう
な手段においてはパッケージの形成時ベ−スのペレット
取付け部に予め銅板を組み込んだ状態でベースを形成す
るため、ガラスエポキシ樹脂等で形成されたベ−スの耐
熱温度が１５０゜〜２００゜程度なことから銀ペ−スト
等の比較的低温度で可能な接着剤にてペレット取付けが
行われる。しかし銀ペ−ストは熱抵抗が高く、あまり使
用時に高熱を発生するタイプの半導体装置には適してい
ない。熱抵抗の良好な半田や金−シリコン共晶を用いる
のが良いが３００゜〜４５０゜の加熱が必要なため、上
記したベ−スに適用できないという課題があった。However, in the above-mentioned means, since the base is formed in the state where the copper plate is previously incorporated in the pellet mounting portion of the base when the package is formed, it is formed of glass epoxy resin or the like. Since the base has a heat-resistant temperature of about 150 ° to 200 °, pellets are attached using an adhesive such as silver paste that can be used at a relatively low temperature. However, the silver paste has a high thermal resistance and is not suitable for a semiconductor device of a type that generates a high heat during use. It is preferable to use solder or gold-silicon eutectic having good thermal resistance, but there is a problem that it cannot be applied to the above-mentioned base because it requires heating at 300 ° to 450 °.

【０００４】本願発明は上記したような課題を解決し、
半田や金−シリコン共晶を用いることのできるＰ．ＰＧ
Ａ型の半導体装置の製造方法を提供することにある。The present invention solves the above problems,
It is possible to use P.O. PG
It is to provide a method for manufacturing an A-type semiconductor device.

【０００５】[0005]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものによって得られるものの効果を
記載すれば下記のとおりである。The effects of the typical inventions among the inventions disclosed in the present application will be described below.

【０００６】すなわち表面処理を施したセラミックある
いは金属からなる板を用意する工程と、前記用意した板
にペレットを半田あるいは金−シリコン共晶により取り
付ける工程と、前記ペレットの取り付けられた板を基板
に取り付ける工程とを有することを特徴とする半導体装
置の製造方法である。また複数の外部リ−ドを有する基
板でありかつペレット取付けのための穴部を有する基板
を用意する工程と、前記穴部にペレットを取り付ける工
程と、前記取り付けたペレットの片面を覆うように封止
する工程とからなることを特徴とする半導体装置の製造
方法である。That is, a step of preparing a plate made of surface-treated ceramic or metal, a step of attaching pellets to the prepared plate by soldering or a gold-silicon eutectic crystal, and a plate on which the pellets are attached to a substrate And a step of mounting the semiconductor device. Further, a step of preparing a board having a plurality of external leads and having a hole portion for mounting a pellet, a step of mounting a pellet in the hole portion, and a sealing so as to cover one side of the mounted pellet. A method of manufacturing a semiconductor device, comprising: a step of stopping.

【０００７】[0007]

【作用】上記した手段によれば、ペレットを取り付ける
セラミックあるいは金属板に予めペレットを取り付けた
後にガラスエポキシ樹脂等で形成されたベ−スに前記ペ
レットを取り付けた板を取り付けるため、ガラスエポキ
シ樹脂で形成されたベ−スの耐熱温度に関係無くペレッ
ト付けを行うことができる。このため半田あるいは金−
シリコン共晶のような低熱抵抗のペレット付け方法を用
いることが可能となり、従来の銀ペ−ストによるものよ
り低熱抵抗を有する半導体装置が可能となる。またペレ
ットの片面を露出させることにより放熱効果を向上させ
ることを可能とした半導体装置の製造方法である。According to the above-mentioned means, since the pellets are attached to the ceramic or metal plate to which the pellets are attached in advance and then the pellet-attached plate is attached to the base formed of glass epoxy resin or the like, the glass epoxy resin is used. Pelletization can be performed regardless of the heat resistant temperature of the formed base. Therefore, solder or gold
A pelletizing method having a low thermal resistance such as silicon eutectic can be used, and a semiconductor device having a lower thermal resistance than that of a conventional silver paste can be obtained. Further, it is a method of manufacturing a semiconductor device, which makes it possible to improve the heat dissipation effect by exposing one surface of the pellet.

【０００８】[0008]

【実施例１】図１は本願発明の実施例である半導体装置
の製造方法を示した一部断面側面図である。以下図１に
基ずいて説明する。[Embodiment 1] FIG. 1 is a partial cross-sectional side view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. A description will be given below with reference to FIG.

【０００９】図１に示したように本実施例においては銅
からなりその表面に金等のめっき処理を施した金属板２
を用意しシリコンで形成された半導体素子ペレット１を
半田３で約３５０゜Ｃの熱処理によって取り付ける。As shown in FIG. 1, in this embodiment, a metal plate 2 made of copper and having its surface plated with gold or the like is used.
The semiconductor element pellets 1 made of silicon are attached with solder 3 by heat treatment at about 350 ° C.

【００１０】次にガラスエポキシ樹脂からなり多数の外
部リ−ドピン６を有するパッケ−ジベ−ス４を用意す
る。このベ−ス４には中央に前記工程によりペレット１
を取り付けた金属板２を取り付けるための穴部が形成さ
れている。またペレットが取り付けられる面と同じ側の
面にメタライズにより配線層が形成されている（図示せ
ず）。 次に前記穴部に前記工程においてペレット１が
取り付けられた金属板を樹脂系の接着剤５を用いて取り
付ける。Next, a package base 4 made of glass epoxy resin and having a large number of external lead pins 6 is prepared. At the center of this base 4, the pellet 1
A hole for attaching the metal plate 2 to which is attached is formed. A wiring layer is formed by metallization on the same surface as the surface on which the pellets are attached (not shown). Next, the metal plate to which the pellet 1 has been attached in the above step is attached to the hole using a resin adhesive 5.

【００１１】次に前記ベ−ス４に取り付けられたペレッ
ト１と前記ベ−ス４上に形成された配線層とをワイヤ７
によりワイヤボンディングにより接続する。このワイヤ
ボンディングについては通常の技術を用いることができ
る。Next, the pellet 1 attached to the base 4 and the wiring layer formed on the base 4 are connected to the wire 7.
To connect by wire bonding. A normal technique can be used for this wire bonding.

【００１２】次に前記ベ−ス４の穴部と前記ペレット１
と前記ワイヤ７およびベ−ス４の一部を覆うようにトラ
ンスファモ−ルドにより封止し封止体８を形成する。こ
の封止方法については通常の技術を用いることができ
る。Next, the hole portion of the base 4 and the pellet 1
Then, the wire 7 and a part of the base 4 are covered with a transfer mold to form a sealed body 8. A usual technique can be used for this sealing method.

【００１３】本実施例によれば半田等を用いることによ
り低熱抵抗の半導体装置を得ることが可能となる。According to this embodiment, it is possible to obtain a semiconductor device having low thermal resistance by using solder or the like.

【００１４】[0014]

【実施例２】図２は本願発明の第２の実施例により形成
した半導体装置を示した側面断面図である。Second Embodiment FIG. 2 is a side sectional view showing a semiconductor device formed according to a second embodiment of the present invention.

【００１５】本実施例において対象となる半導体装置は
外部に放熱フィンを有するＰ．ＰＧＡタイプを有するも
のである。本実施例においても上記実施例と同様に銅等
からなる放熱フィンを有する板２に半田によりペレット
１を取り付ける。次に複数の外部リ−ド６を有する基板
を用意し、ワイヤボンディングによりペレット１の上面
に形成された電極と基板４上に形成されたメタライズ配
線をワイヤ７によって接続する。その後上面をトランス
ファモ−ルドにより封止を行い図２に示したような半導
体装置を得る。The semiconductor device of interest in this embodiment is a P.I. It has a PGA type. Also in this embodiment, the pellets 1 are attached to the plate 2 having the heat radiation fins made of copper or the like by solder as in the above embodiments. Next, a substrate having a plurality of external leads 6 is prepared, and an electrode formed on the upper surface of the pellet 1 by wire bonding and a metallized wiring formed on the substrate 4 are connected by a wire 7. After that, the upper surface is sealed by transfer molding to obtain a semiconductor device as shown in FIG.

【００１６】本願実施例によればさらに放熱効果の高い
低熱抵抗型のＰ．ＰＧＡを得ることが可能となる。According to the embodiment of the present application, the low thermal resistance type P.P. It becomes possible to obtain PGA.

【００１７】[0017]

【実施例３】図３は本願発明の第３の実施例である半導
体装置の実施例を示した側面断面図である。Third Embodiment FIG. 3 is a side sectional view showing an embodiment of a semiconductor device according to the third embodiment of the present invention.

【００１８】本実施例においてはペレットと複数の外部
リ−ドピン６と前記ペレットを取り付ける穴部を有する
ガラスエポキシ樹脂等で形成された基板４を用意する。In this embodiment, a substrate 4 formed of glass epoxy resin or the like having a pellet, a plurality of external lead pins 6 and a hole for mounting the pellet is prepared.

【００１９】次に前記基板４の穴部に樹脂系の接着材３
によりペレット１を取り付ける。その後、上記実施例と
同様にトランスファモ−ルドによりペレット１の片面を
封止する。Next, the resin-based adhesive 3 is placed in the hole of the substrate 4.
The pellet 1 is attached by. Then, one side of the pellet 1 is sealed by transfer molding as in the above embodiment.

【００２０】[0020]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られるものの効果を記載すれば下記
の通りである。The effects of the typical ones of the inventions disclosed in the present application will be described below.

【００２１】すなわち放熱効果の優れた半導体装置の製
造方法を提供することが可能となる。以上、本願発明を
本願発明者によってなされた技術について説明したが本
願は上記実施例に限定されるものではなく、その技術の
範囲において種々変更可能であることはいうまでもな
い。すなわち金属板に取り付けるための接着剤ははんだ
を用いず金−シリコン共晶を用いても構わない。また金
属板を基盤に取り付けるための接着剤は樹脂系のものを
用いても構わないし、さらにペレットを封じする手段に
ついてはポッテイングを用いるようにしても構わない。That is, it is possible to provide a method of manufacturing a semiconductor device having an excellent heat dissipation effect. The invention of the present application has been described above with respect to the technology made by the inventor of the present application, but it is needless to say that the present application is not limited to the above-described embodiments and various modifications can be made within the scope of the technology. That is, the adhesive for attaching to the metal plate may use gold-silicon eutectic instead of solder. Further, a resin-based adhesive may be used for attaching the metal plate to the base, and potting may be used as a means for sealing the pellet.

【００２２】[0022]

【図面の簡単な説明】[Brief description of drawings]

【図１】図１は本願発明の実施例である半導体装置の製
造方法を示した断面側面図である。FIG. 1 is a sectional side view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図２】図２は本願発明の第２の実施例により形成した
半導体装置を示した側面断面図である。FIG. 2 is a side sectional view showing a semiconductor device formed according to a second embodiment of the present invention.

【図３】図３は本願発明の第３の実施例である半導体装
置の実施例を示した側面断面図である。FIG. 3 is a side sectional view showing an embodiment of a semiconductor device which is a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１．．半導体チップ、２．．．金属板、３．．．半田、
４．．．基板、５．．．接着剤 ６．．．リ−ド、７．．．ワイヤ、８．．．封止体、1. ． Semiconductor chip, 2. ． ． Metal plate, 3. ． ． solder,
4. ． ． Substrate, 5. ． ． Adhesive 6. ． ． Lead, 7. ． ． Wire, 8. ． ． Sealed body,

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】表面処理を施したセラミックあるいは金属
から成る板を用意する工程と、前記用意した板にペレッ
トを取り付ける工程と、前記ペレットの取り付けられた
板を基板に取り付ける工程とからなることを特徴とする
半導体装置の製造方法。1. A method comprising the steps of preparing a surface-treated ceramic or metal plate, attaching pellets to the prepared plate, and attaching the pellet-attached plate to a substrate. A method for manufacturing a characteristic semiconductor device. 【請求項２】複数の外部リ−ドを有する基板でありかつ
ペレット取付けのための穴部を有する基板を用意する工
程と、前記穴部にペレットを取り付ける工程と、前記取
り付けたペレットの片面を覆うように封止する工程とか
らなることを特徴とする半導体装置の製造方法。2. A step of preparing a board having a plurality of external leads and having holes for mounting pellets, a step of mounting pellets in the holes, and one side of the mounted pellets And a step of sealing so as to cover the semiconductor device.
JP3223986A 1991-09-04 1991-09-04 Method of manufacturing semiconductor device Pending JPH0613485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3223986A JPH0613485A (en) 1991-09-04 1991-09-04 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3223986A JPH0613485A (en) 1991-09-04 1991-09-04 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH0613485A true JPH0613485A (en) 1994-01-21

Family

ID=16806793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3223986A Pending JPH0613485A (en) 1991-09-04 1991-09-04 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0613485A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920117A (en) * 1994-08-02 1999-07-06 Fujitsu Limited Semiconductor device and method of forming the device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920117A (en) * 1994-08-02 1999-07-06 Fujitsu Limited Semiconductor device and method of forming the device

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