JPH06133173A - Picture data processing unit - Google Patents

Abstract

PURPOSE:To provide the picture data processing unit in which number of times of DMA transfer is reduced, the bus throughput is improved and the processing speed of the entire processing unit is improved. CONSTITUTION:The picture data processing unit provided with a companding means CE applying compression and expansion processing to binary picture data is made up of a discrimination means 2 discriminating whether or not input picture data GDIN to be processed are consecutively the same for n-bits (n is an integer being 2 or over) and outputting a discrimination signal S, a coding means 3 coding picture data part having the same value consecutively and outputting the result to the companding means CE as coded data DC, and a decoding means 4 converting the expansion data DE into output picture data GDOUT being the original picture data when the expansion data DE from the companding means CE are coded data DC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus for processing binary image data (= monochrome image data) such as a facsimile.

In recent years, an image data processing apparatus for processing binary image data such as a facsimile is required to have a high processing speed, and it is strongly desired to improve the throughput of the entire image data processing apparatus.

[0003]

2. Description of the Related Art FIG. 6 shows a block diagram of a conventional facsimile apparatus. Facsimile apparatus 50 includes a scanner unit 51 for outputting a read serial image data DG _S the set original, serial / parallel converter converts the serial image data DG _S into parallel image data DG _P bus 53 52 , A memory 54 for storing various data, and a direct memory access controller (hereinafter, DM) for controlling direct memory access (DMA).
Call it AC. ) 55, a compressing / expanding device 56 for compressing / expanding the transfer data, and the compressed compressed parallel image data CDG _P compressed by the compressing / expanding device 56 and stored in the memory 54 into compressed serial image data CDG _S. A parallel-to-serial converter 57 that outputs the data and a high-level data link controller (hereinafter, HDLC) that exchanges data with the outside through a modem (MODEM) described later.
Call. ) 58, a modem 59 for directly exchanging data with the outside through a communication line, and a CPU 60 for controlling the entire facsimile apparatus 50.

FIG. 7 shows the configuration of the main part of the serial / parallel converter 52. The serial / parallel converter 52 is
The serial image data DG _S from the scanner unit 51 is shifted bit by bit at the timing of the clock signal CK _P ,
An n-bit shift register 52a that outputs a capture end signal full at the time of shifting by n bits, a control circuit that outputs a data output signal OE _P when the capture end signal full is input, and a data output signal OE _P A buffer 52c for simultaneously outputting n bits of contents of the shift register 52a to the bus 53 in response to input, is configured.

Next, the operation will be described. The scanner unit 51 reads the set original document and outputs the serial image data DG _S to the serial / parallel converter 52.

The shift register 52a of the serial / parallel conversion circuit 52 shifts by 1 bit at a timing of the clock signal CK _P , and outputs an acquisition end signal signal full to the control circuit 52b at the time of shifting by n bits. When the capture end signal full is input, the control circuit 52b outputs the data output signal OE _P to the buffer 52c, and the buffer 52c outputs the contents of the shift register 52a for n bits in accordance with the input of the data output signal OE _P. At the same time, that is, the parallel image data DG _P is output to the bus 53.

This parallel image data DG _P is DMA
Under the control of C55, it is first transferred to and stored in the memory 54. Subsequently, the parallel image data DG _P stored in the memory 54 is again transferred to the bus 5 under the control of the DMAC.
3 to the compressor / decompressor 56.

The compressor / decompressor 56 has a counter (not shown) and has the same value when the n-bit parallel image data DG _P is all "0" or all "1". The number of consecutive parallel image data DG _P is counted, and the first-step data compression is performed to convert to a corresponding code according to the value of the parallel image data DG _P and the number of consecutive parallel image data DG _P. Thereafter, one-dimensional or two-dimensional compression processing is performed according to the CCITT standard or the like, and the compressed parallel image data CDG _P is transferred to the memory 54 again under the control of the DMAC 55.

Thereafter, the compressed parallel image data CDG _P stored in the memory 54 is again controlled by the DMAC 55.
Is converted into compressed serial image data CDG _S by the parallel / serial converter 57, and the HDLC 58, the modem 59
Is transferred to another facsimile device or the like via the.

[0010]

In the data of the above-mentioned conventional facsimile apparatus, CCITT standard T.264 is used. 4 standard modes need to process 1728 bits per line. In order to transfer this via a bus having an 8-bit width, 216 DMA transfers are required. Further, during the image data processing, as described above, not only the serial / parallel converter but also the compressor / expander frequently perform DMA transfer, so that the throughput of the bus is significantly reduced, and the CP
There is a problem that the processing speed of task processing by U decreases.

Therefore, an object of the present invention is to provide an image data processing apparatus capable of reducing the number of DMA transfers, improving the throughput of the bus, and improving the processing speed of the entire apparatus.

[0012]

FIG. 1 shows an explanatory view of the principle of the present invention. In order to solve the above problems, the present invention provides a compression / expansion means CE for compressing and expanding image data of a binary image.
In the image data processing device having the above, the discriminating means 2 for discriminating whether or not the input image data GD _IN to be processed has the same value for n bits (n: an integer of 2 or more) continuously and outputting the discrimination signal S. From the compression / expansion means CE, the encoding means 3 encodes the image data portions having the same value continuously based on the discrimination signal S and outputs them as the encoded data D _C to the compression / expansion means CE. If the decompressed data D _E of the above is the encoded data D _C , the encoded data D _E
Decoding means 4 for converting _C to output image data GD _OUT which is original image data and outputting the output image data GD _OUT .

[0013]

According to the present invention, the discriminating means 2 discriminates whether or not the input image data GD _IN to be processed has the same value continuously for n bits (n: an integer of 2 or more) and outputs the discrimination signal S. To do.
The encoding means 3 encodes image data portions having the same value continuously based on the discrimination signal S and outputs them as encoded data D _C to the compression / decompression means CE.

The decoding means 4 is a compression / decompression means CE.
Decompressed data D _E from within when a coded data D _C, and outputs by converting the encoded data D _C to the output image data GD _OUT which is the original image data.

Therefore, when image data having the same value continues, the image data portion is transferred in a compressed state, so that the number of DMA transfers is reduced and the throughput of the entire image data processing device is improved. .

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings. FIG. 2 shows a schematic block diagram of the facsimile apparatus of this embodiment.

The facsimile apparatus 10 reads a set original document and outputs the serial image data DG _S, and the scanner unit 11, converts the serial image data DG _S into parallel image data DG _P , and reserves the parallel image data DG _P. Compress the first compressed parallel image data D
A serial / parallel converter 12 for outputting to the bus 13 as G _P1 , a memory 14 for storing various data, and a DMAC 15 for controlling direct memory access (DMA)
And a compression / expansion unit 16 for compressing / expanding transfer data
And the first compressed parallel image data DG _P1 is compressed by the compressor / decompressor 56, and the second compressed parallel image data CDG _P2 stored in the memory 54 is compressed serial image data CD.
Parallel / serial converter 17 for converting into G _S2 and outputting
An HDLC 18 for exchanging data with the outside via a modem (MODEM), a modem 19 for exchanging data directly with the outside via a communication line, and a CPU 20 for controlling the entire facsimile apparatus 10. It is equipped with.

As shown in FIG. 3, the serial / parallel converter 12 changes when the shift register 31 takes in n bits of image data which is serial data based on the clock signal CK, and when the shift register 31 takes in n bits. A change point detection circuit 32 that outputs a change point detection signal when a change point is detected by detecting the presence or absence of a point, and n-bit image data is all "0" or all "1" based on the change point detection signal. In some cases, a counter 33 that counts the number of consecutive image data groups composed of n-bit image data, a control circuit 34 that outputs first and second data output signals based on a change point detection signal, A buffer 34 that outputs the image data group of the shift register 31 to the data bus based on one data output signal, and a count based on the second data output signal. And it is configured 33 count value of the buffer 36 to be output to the data bus, includes a.

Next, the operation will be described. When serial image data DG _S is input from the scanner unit 11, the serial / serial data
The shift register 31 of the parallel converter 12 takes in image data bit by bit based on the clock signal CK,
Take in n-bit serial image data DG _S.

When the shift register 31 takes in n-bit serial image data DG _S , the change point detection circuit 32 becomes
It is determined whether or not all the captured n-bit serial image data DG _S (these are collectively referred to as an image data group) are “0” (= white) or all “1” (= black).

The serial image data DG _S forming the image data group stored in the shift register 32 are all "0".
Alternatively, if all are “1” and the previous image data group includes “0” and “1”, the change point detection circuit 32 causes the control circuit 35 to reset the counter 33, The conversion point detection signal S for causing the counter 33 to count up is output. As a result, the control circuit 35 resets the counter 33, and then the counter 33
Increments the count value by 1.

In this case, when the current image data group is different from the next image data group, the change point detection circuit 32 similarly outputs the change point detection signal S for resetting the counter to the control circuit 35. . As a result, the control circuit 35 outputs the first data output signal OE ₁ to the buffer 34, and the buffer 34 outputs the image data group of the shift register 31 to the bus 13.

When the current image data group is the same as the next image data group, the change point detection circuit 32 outputs the change point detection signal S for causing the counter 33 to count up. As a result, the counter 33 further increments the count value by 1.

After that, the change point detection circuit 32 determines again the next image data group. Further, when the image data group is not all "0" or all "1", the change point detection signal S indicating that there is a change point, that is, indicating that "0" and "1" are mixed is generated. Output to the control circuit 35. As a result, the control circuit 35 outputs the first data output signal OE ₁ to the buffer 14, and the buffer 14 outputs the image data group of the shift register 31 to the bus 13.

To summarize the above operation, when the image data group of all "0" is continuous or when the image data group of all "1" is continuous, the image data group is input to the shift register 31 first. That is, the image data is output to the bus 13 as it is, and the continuous number is output to the bus 13 when the images are no longer continuous. Further, when there is only one image data of all “0” or all “1” or when image data of “0” and “1” are mixed, the image data group is directly output to the bus 13, This means that the counter 33 will remain reset.

Therefore, when the image data groups of all "0" or all "1" are respectively continuous, only the first image data group and the number of continuous times are the bus 13.
Since the data is output to the printer, the occupation rate of the bus 13 is reduced and the throughput of the entire facsimile apparatus as the image data processing apparatus can be improved.

Next, referring to FIG. 4, a more specific embodiment will be described.
explain. The serial / parallel conversion circuit 40 is a serial
8-bit image data based on the clock signal CK
Capture end signal ful at the time of capture and 8-bit capture
shift register 41 that outputs 1 and shift register 4
1 captures 8-bit image data (image data group)
At that time, it is determined whether all 8 bits are "1".
First change point detection signal S₁AND circuit 42 for outputting
The image data forming the image data group is all “0”
It is determined whether or not the second change point detection signal S₂NA to output
The ND circuit 43 and the first change point detection signal S₁And the second strange
Sampling point detection signal S₂The logical sum signal S is obtained by taking the logical sum of₃Out
OR circuit 44 for applying a logical sum signal S ₃And end of import
The logical product of the signals full is calculated and the result is described later.
AN which outputs as the count clock signal CKC
D circuit 45 and 8-bit image data are all "0"
If all are “1”, the number of consecutive image data groups
A counter 46 for counting, a change point detection signal and
The first data output signal OE based on the plug-in end signal full
₁, Second data output signal OE₂, Reset signal RST
And a control circuit for outputting the DMA request signal REQ
And the first data output signal OE₁Shift register based on
A buffer 4 for outputting the image data group of the data 11 to the bus 13.
8 and the second data output signal OE₂Based on counter 4
A buffer 49 for outputting to the count value tabus 13 of 6;
It is configured with.

Next, the operation of the specific embodiment will be described with reference to FIG. When serial image data DG _S is input from the scanner unit 11 to the shift register 41 and image data of 8 bits is stored at time t ₁ , the shift register 41
Sets the capture end signal full to "H" level. At this time, the data stored in the shift register 41 is "40H" (H
Indicates a hexadecimal number. The same applies hereinafter. ), Both the first change point detection signal S ₁ and the second change point detection signal S ₂ are at “L” level, and the logical sum signal S ₃ is also at “L” level.

As a result, the reset signal RST is output from the control circuit 47 to the counter 46, and the counter 46 is reset. Next, the control circuit 47, at time t ₂ ,
The DMA request signal REQ is output to the DMAC15,
The first data output signal OE ₁ is output to the buffer 48.
As a result, the buffer 48 causes the first compressed parallel data D, which is a group of image data stored in the shift register 41.
G _P1 (= “40H”) is output to the bus 13 and DMAC1
5 transfers this to the memory 14.

Again, the serial image data DG _S is input from the scanner section 11 to the shift register 11, and at time t ₃
When the 8-bit image data has been captured, the shift register 41 sets the capture end signal full to "H" level. At this time, if the image data group stored in the shift register 41 is “33H”, both the first change point detection signal S ₁ and the second change point detection signal S ₂ are “L”.
And the logical sum signal S ₃ also becomes “L” level.

As a result, the reset signal RST is output from the control circuit 47 to the counter 46, and the counter 46 is reset (= count value is "00H"). Next, the control circuit 47 outputs the DMA request signal REQ to the DMAC 15 at time t ₄ , and the first data output signal O
The E ₁ is output to the buffer 48. This makes buffer 4
8 outputs the first compressed parallel data DG _P1 (= “40H”) stored in the shift register 41 to the bus 13,
The DMAC 15 transfers this to the memory 14.

Further, the serial image data DG _S is input from the scanner unit 11 to the shift register 41, and at time t ₅
When the 8-bit image data is captured in the shift register 41, the shift register 41 sets the capture end signal full to the “H” level. At this time, the data stored in the shift register 41 is "0".
"When was the first change point detection signals S ₁ is" 0H L "level, the second change point detection signal S ₂ is""level, the logical sum signal S ₃ is" H becomes H "level.

Therefore, the counter clock signal CKC
Becomes "H" level, the counter 46 counts up by 1, and the count value becomes "01H". Next, the control circuit 47
Outputs the DMA request signal REQ to the DMAC 15 and the first data output signal OE ₁ to the buffer 48 at time t ₆ . As a result, the buffer 48 causes the first compressed parallel data DG _P1 (= “00
H ") is output to the bus 13, and the DMAC 15 transfers it to the memory 14.

Further, when the image data is input from the scanner section 11 to the shift register 41 and the 8-bit image data is input at time t ₇ , the shift register 41 sets the capture end signal full to the “H” level. To do. At this time, if the data stored in the shift register 41 is "00H" again, similarly, the first change point detection signal S ₁ is at "L" level and the second change point detection signal S ₂ is at "H". "level, the logical sum signal S ₃ becomes" H "level.

Therefore, the counter clock signal CKC
Becomes "H" level, the counter 46 counts up by 1, and the count value becomes "02H". Similarly,
Time t _8, when the content of the shift register 41 at time t ₉ is assumed to be again "00H", further counter 46
Is counted up twice and the count value becomes "04H".

Next, from the scanner section 11 to the shift register 4
The image data is input at 1 and time t _Ten8-bit image
When the image data is captured, the shift register 41 finishes capturing.
The end signal full is set to "H" level. At this time, Schiff
The data content stored in the register 41 was "72H"
Then, the first change point detection signal S₁And second change inspection
Outgoing signal S₂Are both at "L" level, and the OR signal S₃
Also becomes the "L" level.

As a result, the control circuit 47 outputs the second data output signal OE ₂ to the buffer 49 and, at the same time, the DMAC.
The DMA request signal REQ is output to 15. Consequently, at time t ₁₁ , the buffer 49 outputs the count data (= “04H”) of the counter 46 to the bus 13 and D
The MAC 15 transfers this to the memory 14.

Next, the control circuit 47 causes the reset signal RST.
Is output to the counter 46, and the counter 46 is reset. Next, at time t ₁₂ , the control circuit 47 outputs the DMA request signal REQ to the DMAC 15 and outputs the first data output signal OE ₁ to the buffer. As a result, the buffer 48 outputs the data (= "72H") stored in the shift register 41 to the bus 13, and the DMAC 15 transfers it to the memory 14.

Similarly, at time t ₁₃ , when the data fetch signal full becomes "H" level, the contents of the shift register 41 are determined, and at time t ₁₄ , the image data stored in the shift register 14 is stored. Group (= "8
1H ″) is DMA-transferred via the bus 13.

In the above explanation of the operation, the case where four pieces of 8-bit image data = "00H" are consecutive,
In the following description, 8-bit image data = “00
Four H "s continue, and 8-bit image data =" F
The operation in the case where seven FH ″ are continuous will be described. Note that FIG. 2 is used in the following description.

First, from the scanner section 11 to the shift register 4
When the serial image data DG _S is input to 1 and the 8-bit serial image data DG _S is input, the shift register 41 sets the capture end signal full to the “H” level. At this time, if the data contents are stored in the shift register 41 is a "00H", the first change point detection signals S ₁ is "L" level, the second change point detection signal S ₂ becomes "H" level , The logical sum signal S ₃ becomes "H" level.

Therefore, the counter clock signal CKC
Becomes "H" level, the counter 46 counts up by 1, and the count value becomes "01H". Next, the control circuit 4
7 outputs the DMA request signal REQ to the DMAC 15 and outputs the first data output signal OE ₁ to the buffer 48. As a result, the buffer 48 outputs the data (= “00H”) stored in the shift register 41 to the bus 13, and DM
The AC 15 transfers this to the memory 14.

Further, when image data is input from the scanner unit 11 to the shift register 41 and 8-bit image data is input at time t ₇ , the shift register 41 sets the capture end signal full to "H" level. . At this time, if the data in the shift register 41 is "00H" again, the first change point detection signal S ₁ is "L" in the same manner.
The level and the second change point detection signal S ₂ become “H” level, and the logical sum signal S ₃ becomes “H” level.

Therefore, the counter clock signal CKC
Becomes "H" level, the counter 46 counts up by 1, and the count value becomes "02H". Similarly, the data stored in the shift register 41 is again "0" consecutively twice.
If it is “0H”, the counter is further counted up twice, and the count value becomes “04H”.

Next, from the scanner section 11 to the shift register 4
When the image data is input to 1 and the image data of 8 bits is input, the shift register 41 causes the capture end signal fu.
11 is set to "H" level. At this time, if the data in the shift register 41 is "FFH", the first change point detection signal S ₁ is at "H" level and the second change point detection signal S
₂ becomes the "L" level, the logical sum signal S ₃ becomes "H" level.

At this time, the control circuit 47 detects that the signal levels of the first change point detection signal S ₁ and the second change point detection signal S ₂ are inverted from those of the previous time, and the second data output signal OE ₂ Is output to the buffer 49, and at the same time, the DMAC15
The DMA request signal REQ is output to. As a result, the buffer 49 outputs the content (= "04H") of the counter 46 to the bus 13, and the DMAC 15 transfers it to the memory 14.

At the same time, the control circuit 47 outputs the reset signal RST to the counter 46, and the counter 46 is reset. After that, the counter clock signal CKC becomes "H" level, the counter 46 counts up by 1, and the count value becomes "01H".

Next, the control circuit 47 outputs the DMA request signal REQ to the DMAC 15 and the first data output signal S ₁ to the buffer 48. This makes buffer 4
8 outputs the content (= “FFH”) of the shift register 41 to the bus 13, and the DMAC 15 transfers it to the memory 14.

Further, when image data is input from the scanner section 11 to the shift register 41 and image data of 8 bits is input, the shift register 41 causes the capture end signal f.
ull is set to "H" level. At this time, if the data content of the shift register 41 was again "FFH", the first change point detection signals S ₁ in the same manner as the "H" level, the second change point detection signal S ₂ becomes "L" level , The logical sum signal S ₃ becomes "H" level. In this case, since the first change point detection signal S ₁ and the second change point detection signal S ₂ are not inverted as compared with the previous time, the control circuit 4
7 does not reset the counter 46.

On the other hand, the counter clock signal CKC becomes "H" level, the counter 46 counts up by 1, and the count value becomes "02H". Similarly, the data stored in the shift register 41 is again "F" five times consecutively.
If it is FH ”, the counter 46 is further counted up 5 times, and the count value becomes“ 07H ”.

Next, when the image data group other than "00H" or "FFH" is stored in the shift register 41,
First change point detection signal S ₁ and second change point detection signal S ₂
Both become "L" level, and the logical sum signal S ₃ also becomes "L" level. As a result, the control circuit 47 outputs the second data output signal OE ₂ to the buffer 49 and, at the same time, the DMAC.
The DMA request signal REQ is output to 15. As a result, the buffer 49 causes the contents of the counter 46 (= "07
H ") is output to the bus 13, and the DMAC 15 transfers it to the memory 14.

Next, the control circuit 47 sends the reset signal RST.
Is output to the counter 46, and the counter 46 is reset. As described above, according to the present embodiment, when the image data group composed of all “0” or all “1” image data is continuous, only the image data group and the number of continuous images are set. Since it is output, the number of DMA transfers is reduced, and the throughput of the image data processing apparatus as a whole is improved.

Further, in the above description, only the case where the image data is compressed and coded is described, but the modem, the HDLC, the serial that receives the coded serial data from the outside and performs the serial / parallel conversion. It is also possible to provide a / parallel converter, and perform inverse conversion (expansion) on the encoded image data by the compression / expansion device 16 to decode the original image data.

Therefore, also in the processing device for decoding, the number of DMA transfers is reduced and the throughput is improved. Further, as described above, according to the present embodiment, when the image data group composed of all “0” or all “1” image data is continuous, the image data group and the number of continuous times thereof. Since only the data is output, the number of DMA transfers is reduced and the throughput of the image data processing apparatus as a whole is improved.

In the above description, only the facsimile apparatus is described as the image data processing apparatus, but the present invention is also applied to other image data processing apparatuses such as digital copying apparatus and personal computer which handle binary image data. Is possible.

[0056]

According to the present invention, in the image data processing apparatus for processing the image data of the binary image, when the image data having the same value is continuous, the image data portion is transferred in a compressed state. Therefore, the number of DMA transfers is reduced, and the throughput of the entire image data processing device is improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an embodiment.

FIG. 3 is a block diagram showing a schematic configuration of a serial / parallel converter.

FIG. 4 is a block diagram showing a specific configuration of a serial / parallel converter.

FIG. 5 is an operation timing chart of the serial / parallel converter.

FIG. 6 is a block diagram showing a schematic configuration of a conventional example.

FIG. 7 is a block diagram showing a schematic configuration of a conventional serial / parallel converter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image data processing apparatus 2 ... Storage means 3 ... Change point detection means 4 ... Value determination means 5 ... Counting means 10 ... Facsimile apparatus 11 ... Scanner section 12 ... Serial / parallel converter 13 ... Bus 14 ... Memory 15 ... DMAC 16 ... compression / expansion device 17 ... parallel / serial converter 18 ... HDLC 19 ... modem 20 ... CPU 31 ... shift register 32 ... change point detection circuit 33 ... counter 34 ... buffer 35 ... control circuit 36 ... buffer 40 ... serial / parallel conversion 41 ... Shift register 42 ... AND circuit 43 ... NAND circuit 44 ... OR circuit 45 ... AND circuit 46 ... Counter 47 ... Control circuit 48 ... Buffer 49 ... Buffer CK ... Clock signal CKC ... Count clock signal CNT ... Count data DET ... Change Point detection signal full ... Capture Completion signal GD ... image data GD _P1 ... parallel image data GD _P2 ... parallel image data GD _S ... serial image data GP ... image data group OE ₁ ... first data output signal OE ₂ ... second data output signal REQ ... DMA request signal S ... changing point detection signal S ₁ ... first change point detection signal S ₂ ... second change point detection signal VAL ... value determination signal

Claims (2)

[Claims] 1. Image data of a binary image is compressed and expanded.
Image processing apparatus including compression / expansion means (CE)
Input image data (GD_IN) Is n bits (n:
(An integer of 2 or more) Continuously determine whether or not they are the same value.
No. (S) for outputting the determination signal (S), and based on the determination signal (S), the same value is continuously output.
Coded data by coding the image data part that has
(D_C) To the compression / expansion means (CE)
And the decompression data (D) from the compression / decompression means (CE)._E)But
The encoded data (D _C), The encoding data is
Data (D_C) Is the output image data that is the original image data
(GD_OUT) And a decoding means (4) for outputting the converted data. 2. The image data processing apparatus according to claim 1, wherein the discriminating means stores a shift register for storing the image data (GD) to be processed in an image data group unit consisting of n-bit image data, A change point detection unit that determines whether binary values (= 0, 1) are mixed in the image data group stored in the shift register and outputs a change point detection signal, and the change point detection signal (DET). On the basis of which, when two values do not coexist in the image data group, it is determined which value the image data forming the image data group has,
And a value discriminating means for outputting a value discriminating signal, wherein the encoding means, based on the change point detection signal and the value discriminating signal, when the two values are not mixed in the image data group, the same value An image data processing device, comprising: a counting unit that counts the number of consecutive image data groups having the number and outputs count data corresponding to the image data group and the number of consecutive images.