JPS6366113B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to image signals having any line length (number of pixels in one scanning line) (binary image consisting of white pixels and black pixels, multivalue image, or color image). The present invention relates to an image signal compression device that can also perform compression processing on images.

Image compression devices include those that are integrated with an image input device (such as a scanner), such as a facsimile, and those that are connected to a computer in an image processing system. For image input devices that have a fixed length of one scanning line, such as a conventional facsimile, the compression block length of the image compression device built into the device (the length of one block that the compression device compresses and encodes) (or the number of pixels per line) was also fixed and there was no problem. However, the length of one scanning line of an image input device can be made variable, and the number of pixels in one block of the input image signal (the number of pixels in one line or a part of one line can be extracted) depending on the size of the document or drawing. If it is possible to change the number of pixels in the image, the image compression device will also need to have a variable compression block length. On the other hand, in image processing systems, the size of images handled is not constant, and only a portion of a certain image is extracted and compressed. Therefore, an image compression apparatus connected to such a system is required to have a variable compression block length and be capable of compressing an image having an arbitrary number of pixels per block. However, if the compression block length is made variable according to the number of pixels in one block of the input image signal, the configuration of the compression device becomes complicated.

An object of the present invention is to perform compression processing on an input image signal having an arbitrary number of pixels in one block with a simple configuration having a fixed compression block length, and to make the compression block length variable according to the number of pixels in one block of the input image signal. It is an object of the present invention to provide an image signal compression device that has almost the same compression efficiency as the image signal compression device.

The image signal compression device of the present invention compresses an input image signal of L pixels per block so that the number of pixels matches the compression block length M (L≦M).
- pixel signal adding means for adding L) pixels;
It is comprised of a compression means for compressing M pixels outputted from the pixel signal adding means and outputting compressed encoded data.

The present invention will be described below with reference to drawings showing embodiments. First, the image signal compression device will be explained.

FIG. 1 is a block diagram showing the basic configuration of an image signal compression apparatus according to the present invention. Input image signal 1 is output from an image input device, image processing system, etc.
This is an image signal of block L pixels. For example, L is
In the case of a facsimile scanned at A4 size at 8 lines/mm, it will be 1728. The pixel signal addition section 2 adds (ML) pixels to the input image signal 1 so that the number of pixels matches the compression block length M (for example, 2048) of the compression section 4, and adds a total of M pixels. The image signal 3 is sent to the compression section 4. However, M≧L.
The compression unit 4 performs compression processing on the image signal 3 of M pixels that matches the compression block length, and outputs compressed encoded data 5. With respect to this basic configuration, various configuration examples of the pixel signal adding section 2 can be considered, and examples thereof will be shown below.

First, two embodiments will be described by considering the case where only one block of the input image signal is input, excluding the case where a plurality of blocks of input image signals are input consecutively.

FIG. 2 is a block diagram showing a first embodiment of the image signal compression apparatus of the present invention. The composition is counting part 6,
It consists of a clock generation section 7, an OR circuit 8, an image signal gate 9, and a compression section 4, and receives as signals an input image signal 1, an image signal clock 10, an image signal 3 of M pixels,
There is compressed encoded data 5. Next, the operation will be explained. The input image signal 1 is a signal of L pixels for one block and is sent to the compression section 4 through the image signal gate 9, and the image signal clock 10 is a clock synchronized with the input image signal 1 and is sent to the compression section 4 through the OR circuit 8. . The image signal gate 9 is open while the input image signal 1 is being sent to the compression section 4. The counting section 6 counts the number of clocks of the picture signal clock 10, and when it reaches L, sends a control signal to the clock generating section 7 and the picture signal gate 9. When the clock generating section 7 receives this control signal, it calculates the difference (M-) between the compression block length M of the compression section 4 and the number of pixels L of the input image signal 1.
L) clocks are generated. These (ML) clocks are sent to the compression unit 4 through the OR circuit 8, so M clocks are sent to the compression unit together with the image signal clock. When the image signal gate 9 receives the control signal from the counting section 6, it closes the gate and sends a fixed value to the compression section 4. As a result, in the image signal 3 of M pixels sent to the compression unit 4, the first L pixels are the input image signal 1, and the remaining (M-
L) Pixel has a fixed value. The compression unit 4 performs compression processing on the image signal 3 of M pixels matching the compression block length and outputs compressed encoded data 5. The fixed value output by the image signal gate 9 is selected so that the compression efficiency in the compression section 4 is high. If the input image signal 1 is a binary signal of white and black, such as a facsimile signal, it is better to set the fixed value to white. Generally speaking, in the case of facsimile signals, the end of one line is often white, and when run-length encoding is used as the compression encoding method in the compression unit 4, the length of the final white run becomes slightly longer. The number of runs does not change. Therefore, the compression coding efficiency remains almost unchanged compared to the case where the compression block length is made variable and the number of block pixels L of the input image signal 1 is made the same. If the last run of a compressed block is omitted in run-length encoding and is not encoded, exactly the same compression encoding efficiency as when the compression block length is made variable can be obtained. Furthermore, in this embodiment, the end of the input image signal is detected by counting L pixels in the counting section 6;
It is also possible to receive a synchronization signal (phase signal) for a block and thereby detect the end.

FIG. 3 is a block diagram showing a second embodiment of the image signal compression apparatus of the present invention. This embodiment also considers the case where only one block of image signals is input. The configuration consists of an input buffer 11, a counting section 6, an image signal gate 9, and a compression section 4, and the signals include an input image signal 1, an image signal clock 10, an image signal 3 of M pixels, a readout clock 12, and compressed encoded data 5. be. Next, the operation will be explained. An input image signal 1 of one block of L pixels is written into an input buffer 11 by an image signal clock 10. When all L pixels of the input image signal 1 have been written into the input buffer 11, the compression unit 4 outputs M readout clocks 12.
is sent to the input buffer 11 and the input image signal is read from the beginning. The counting section 6 is connected to the readout clock 12.
is counted, and when the number reaches L, a control signal is sent to the image signal gate 9. The image signal gate 9 is open while the input image signal is being sent to the compression section 4, but when it receives a control signal from the counting section 6, it closes and sends a fixed value to the compression section 4. As a result, in the image signal 3 of M pixels, the first L pixels are input image signals, and the remaining (ML) pixels have fixed values. The compression unit 4 performs compression processing on the image signal 3 of M pixels and outputs compressed encoded data 5.

Two embodiments have been described above regarding the case where only one block is input as the input image signal.
Next, a case where multiple blocks of image signals are input will be described. When multiple blocks of signals are input, the period from when the image signal of one block is input until the signal of the next block is input (M
-L) When there is a sufficient time interval to add pixel signals and perform compression processing, compression can be performed using the first and second embodiments described above, but such If there is no time interval, the first and second embodiments cannot be used. An embodiment of the image signal compression apparatus for the case where N blocks of image signals are input continuously will be described below.

FIG. 4 is a block diagram showing a third embodiment of the image signal compression apparatus of the present invention. The configuration includes an input buffer 11, an address controller 13, a counting section 6,
It consists of an image signal gate 9 and a compression section 4, and has an input image signal 1, an image signal clock 10, an image signal 3 of M pixels, a readout clock 12, and compressed encoded data 5 as signals.

Next, the operation will be explained. When an input image signal of one block of L pixels is inputted for N blocks consecutively, this signal is written into the input buffer 11 from the initial address (for example, address 0) by the image signal clock 10. In the counting section 6, the image signal clock 10
is counted, and a control signal is sent to the address controller 13 every time the counted value reaches L. When the address controller 13 receives the control signal, the address controller 13 inputs the input buffer 1 by the difference (ML) between the compression block lengths M and L.
1 write address is skipped. As a result, each time an input image signal of L pixels is written to the input buffer 11, the address jumps by (ML).
Next, the input pixel signal is written again. FIG. 5 shows an example of the image signal storage area of the input buffer 11. Note that the shaded area indicates the area where the image signal is stored. After all N blocks of input image signals 1 are written to the input buffer 11, the compression unit 4 outputs the readout clock 1.
2 is sent to the input buffer 11 in N blocks at a time, and the image signal is read from the initial address of the input buffer 11. At this point, the counting unit 6 repeatedly counts the readout clocks 12 in units of M, and while counting (ML) clocks from when the count value exceeds L until it reaches M, the image signal gate is Send a control signal to 9. The image signal gate 9 closes only while receiving a control signal from the counting section 6 and sends a fixed value signal to the compression section 4, but opens at other times. As a result, while the image signal gate 9 is reading out the image signal of one block of L pixels written to the input buffer 11, the signal is sent as is to the compression unit 4, but when the image signal is written to the input buffer 11, it is skipped. While reading the contents of (ML) addresses, the fixed value is stored in the compressor 4.
Repeat the process of sending to. Therefore, the image signal 3 of M pixels is the input image signal of L pixels and (M
-L) It is composed of a fixed value signal of pixels, and the compression unit 4 compresses this signal by N blocks and outputs compressed encoded data 5.

Note that in this embodiment, N for the input buffer 11 is
Writing and reading of data for a block are performed separately, but if the address counters for writing and reading are separated and the timing slots are separated so that they can operate in parallel, the compression process can be transferred to the input buffer 11. By starting with a delay from the writing of the image signal, it is possible to input the image signal and perform compression processing at the same time. However, in this case, it is necessary to divide the counting section 6 into a counting section for the image signal clock 10 and a counting section for the readout clock 12.

FIG. 6 is a block diagram showing a fourth embodiment of the image signal compression apparatus of the present invention. This embodiment also considers the case where N blocks of input image signals are input continuously. The configuration consists of an input buffer 11, a counting section 6, an image signal gate 9, a clock gate 14, and a compression section 4, and the signals include an input image signal 1, an image signal clock 10, an image signal 3 of M pixels, a readout clock 12, and compression encoding. There is data 5.

When the input image signal 1 of one block of L pixels is input for N blocks, the input image signal 1 is all written into the continuous address area from the initial address (for example, address 0) of the input buffer 11 by the image signal clock 10. An example of the image signal storage area of the input buffer 11 is shown in FIG. When N blocks of input image signals are written to the input buffer 11, the compression unit 4 changes the read clock 12 to M.
The image signal is sent to the input buffer 11 in N blocks at a time, and the image signal is read out from the initial address of the input buffer 11. The counting section 6 repeatedly counts the readout clocks 12 in units of M, and while counting (ML) clocks from when the count value exceeds L until it reaches M, the clock gate 14 and the image signal gate are 9
send a control signal to. The clock gate 14 closes only while the control signal is being sent from the counter 6, and the read clock 12 is connected to the input buffer 11.
I don't send it to. The image signal gate 9 closes only while the control signal is being sent from the counting section 6, and sends a fixed value signal to the compression section 4. As a result, when M read clocks are output from the compression section 4, the addresses of the input buffer 11 increase in order for the first L clocks, and the accumulated input image signals are sent to the compression section 4. , for the remaining (ML) addresses, the addresses of the input buffer 11 do not change, and fixed value signals are sent to the compression unit 4. Therefore, the image signal 13 of M pixels is the image signal of L pixels and (M
-L) consists of a fixed value signal of pixels, and the compression unit 4 compresses this signal by N blocks and outputs compressed encoded data 5.

In this embodiment as well, as in the third embodiment, image signal input and compression processing can be performed in parallel.

In each of the embodiments of the image signal compression device described above, the image signal of M pixels sent to the compression section is in the form of the image signal of L pixels, followed by the fixed value signal of (ML) pixels. However, the position at which the (ML) pixel is added can be arbitrarily selected if a convention is established with the corresponding image signal expansion device.

Next, the image signal expansion device will be explained.

FIG. 8 is a block diagram showing the basic configuration of an image signal expansion device corresponding to the image signal compression device of the present invention. The compressed encoded data 20 is encoded data of compressed block length M, which is obtained by performing compression processing on an image signal of one block of L pixels by the image signal compression apparatus of the present invention. In the decompression unit 21, compressed encoded data 2
0 is input, and after decompression processing is performed, an expanded signal 22 of M pixels is output. The signal extraction unit 23 extracts an output image signal 24 of one block of L pixels before compression from among the M pixels. With respect to this basic configuration, several configuration examples of the signal extraction section can be considered, and examples thereof will be shown below.

First, consider the case where only one block of compressed encoded data 20 is input and an output image signal of L pixels is sent out.

FIG. 9 is a block diagram showing a first embodiment of the image signal expansion device. The configuration consists of an expansion section 21, an output buffer 25, and an address controller 26, and the signals include compressed encoded data 20, expansion signal 22, write clock 27, and output image signal 2.
4. There is an image signal clock 28.

Next, the operation will be explained. The decompression unit 21 inputs compressed encoded data 20, performs decompression processing, and then outputs a decompressed signal 22 having the number of pixels equal to the compressed block length M. This expanded signal 22 for M pixels is composed of an image signal for L pixels and a fixed value signal for (ML) pixels, and is written into the output buffer 25 by a write clock 27 output from the expansion section. When this writing is completed, the address controller 26 sets the address of the output buffer 25 to the initial address where one actual block of L pixel image signals is stored among the M pixel signals stored in the output buffer 25. be done. This initial address is determined by the agreement with the image signal compression device, but setting the address to 0 simplifies the device configuration. After this initial address setting is completed, when the image signal clock 28 is input for L pixels, the output image signal 24 expanded by one block of L pixels from the initial address of the output buffer 25 is read out.

Next, a case will be explained in which N blocks of compressed encoded data are continuously input. In this case, the decompression processing for one block and the L
When there is a sufficient time interval for extracting and transmitting the output image signals of the pixels, decompression can be performed using the first embodiment, but when there is no such time interval. In this case, the embodiment described below must be used.

FIG. 10 is a block diagram showing a second embodiment of the image signal expansion device. The configuration includes an expansion section 21, an output buffer 25, an address controller 26, and a counting section 29, and the signals include compressed encoded data 20, expansion signal 22, write clock 27, output image signal 24, and image signal clock 28. Next, the operation will be explained. When N blocks of compressed encoded data 20 are input, the decompression unit 21 performs decompression processing on each block and generates N blocks of decompressed signals 2.
2 is written to successive addresses of the output buffer 25 from address 0 by the write clock 27. When the first L pixels of the expanded signal 22 of M pixels are image signals and the remaining (ML) pixels are fixed value signals, the image signal storage area in the output buffer 25 is equal to that shown in FIG. After N blocks of expansion processing have been performed, the address of the output buffer 25 is returned to 0, and when the image signal clock 28 is input to the output buffer 25, the output image signals 24 are sequentially read out. The counting section 29 counts the image signal clock 28 and sends an address control signal to the address controller 26 every time L clocks are counted. Each time the address controller 26 receives an address control signal from the counting section 27, the address of the output buffer is skipped by (ML) and set to the address where the next image signal is stored. With this operation, L
After the image signal of the pixel is read out (M-L), data other than the image signal of the pixel is read out, and the next image signal part is read out, and finally only the image signal of N blocks is output. It will be sent out as an image signal 24.

FIG. 11 is a block diagram showing a third embodiment of the image signal expansion device. The configuration includes an expansion section 21, a counting section 29, a clock gate 30, and an output buffer 25.
The signals include compressed encoded data 20,
There are an expansion signal 22, a write clock 27, an output image signal 24, and an image signal clock 28. N blocks of compressed encoded data 20 are input continuously.
The decompression unit 21 performs decompression processing on the compressed encoded data 20 for each compressed block, sends out the decompression signal 22 for M pixels and the write clock 23, and writes the decompression signal 22 from address 0 of the output buffer. It is assumed that the first L pixels of this expanded signal 22 are image signals. The counter 29 counts the write clock 27 and repeats the operation of sending a gate control signal to the clock gate 30 for (ML) clock intervals until the count value changes from L to M. In clock gate 30, write clock 2 is normally
7 is sent as is to the output buffer, but the counter 29
While the gate control signal is being sent from the gate control signal, the clock is stopped and no signal is sent to the output buffer 25. As a result, the image signals of the first valid L pixels are written to the output buffer 25, but the remaining (ML) pixels are not written, and when the expansion process for N blocks is completed in the expansion section 21, the output buffer 25 is written. The image signal storage area is in a continuous form as in FIG. When the image signal clock 28 is input after the address of the output buffer is reset to 0, N blocks of output image signals 25 are successively read out and sent out.

In the embodiments of the second and third image signal decompression devices described above, the first L pixels of the M pixel decompression signals are valid image signals.
Even when the image signal of a pixel is located at another position in the expanded data of M pixels, only the effective image signal can be easily extracted by changing the initial point of counting of the counting section.

By using the image signal compression device whose configuration and operation have been explained above, it is possible to compress an image signal having an arbitrary number of pixels per block with a simple configuration having a fixed compression block length, and to compress an image signal having an arbitrary number of pixels per block. This has the effect of achieving almost the same compression efficiency as when the compression block length is made variable according to the number of pixels.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the image signal compression device of the present invention, and FIGS.
6 are block diagrams showing first, second, third and fourth embodiments of the image signal compression apparatus of the present invention, respectively. FIG. 5 and FIG. 7 are diagrams showing the contents of the input buffer in the third and fourth embodiments, respectively. FIG. 8 is a block diagram showing the basic configuration of an inner image signal expansion device corresponding to the image signal compression device of the present invention, and FIGS. 2 is a block diagram showing a third embodiment. The numbers in the figure indicate the following, respectively. 1... Input image signal, 2... Pixel signal addition section,
3...M pixel image signal, 4...Compression section, 5...
Output compression encoded data, 6... Counting section of compression device, 7... Clock generation section, 8... OR circuit,
9...Picture signal gate, 10...Picture signal clock of the compression device, 11...Input buffer, 12...Reading clock, 13...Address controller of the compression device, 14...Clock gate of the compression device,
20... Input compressed encoded data, 21... Expansion section, 22... Expanded signal, 23... Signal extraction section, 2
4... Output image signal, 25... Output buffer, 2
6...address controller of decompression device, 27...
...Write clock, 28...Picture signal clock of the decompression device, 29...Counter of the decompression device, 30...
Stretcher clock gate.

Claims (1)

[Claims] 1. In an image signal compression device that data compresses an input image signal having an arbitrary number of pixels per line L,
A fixed number of pixels in one line M (provided that L≦M) for the above-mentioned arbitrary input image signal with the number of pixels in one line L
a pixel signal addition means for adding (M-L) fixed level value pixels so that the number of pixels matches, and a compression code for compressing the image signal of one line M pixels output from the pixel signal addition means. 1. An image signal compression device comprising: compression means for outputting converted data.