JPH06132455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06132455A JPH06132455A JP4281886A JP28188692A JPH06132455A JP H06132455 A JPH06132455 A JP H06132455A JP 4281886 A JP4281886 A JP 4281886A JP 28188692 A JP28188692 A JP 28188692A JP H06132455 A JPH06132455 A JP H06132455A
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- lead
- semiconductor element
- semiconductor device
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は特にリードフレームへ
のボンディング工程を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bonding process to a lead frame.
【０００２】[0002]
【従来の技術】図６は従来の半導体装置の第１構成を示
す上面図である。半導体素子11はエポキシ系のペースト
12を用いてリードフレ−ムにおけるダイパッド15に固着
されている。このダイパッド15は銀メッキされたインナ
リード16のうちのインナリード16-1と結合している。2. Description of the Related Art FIG. 6 is a top view showing a first structure of a conventional semiconductor device. The semiconductor element 11 is an epoxy paste
It is fixed to the die pad 15 in the lead frame by using 12. The die pad 15 is connected to the inner lead 16-1 of the silver-plated inner leads 16.
【０００３】インナリード16-1はダイパッド15を支持す
るつりピンを兼ねている。半導体素子11主面に複数配置
された電極パッド18のうちの電極パッド18-1はインナリ
ード16-1とボンディングワイヤ19により接続される。こ
れは、半導体素子11動作時に安定した電位を確保するた
めの構成である。The inner lead 16-1 also serves as a hanging pin that supports the die pad 15. The electrode pad 18-1 of the plurality of electrode pads 18 arranged on the main surface of the semiconductor element 11 is connected to the inner lead 16-1 by the bonding wire 19. This is a configuration for ensuring a stable potential when the semiconductor element 11 is operating.
【０００４】図７は従来の半導体装置の第２構成を示す
断面図で、ＬＯＣ（lead on chip）構造を示している。
半導体素子21の主面とインナリード22とは、両面に熱硬
化性の接着剤25を塗布したポリイミド等の絶縁テープ26
を用いて固着される。半導体素子21主面中央に配列され
た各電極パッド28はボンディングワイヤ29により各イン
ナリード22と接続される。FIG. 7 is a sectional view showing a second structure of a conventional semiconductor device, showing a LOC (lead on chip) structure.
The main surface of the semiconductor element 21 and the inner leads 22 are insulating tapes 26 such as polyimide whose both surfaces are coated with a thermosetting adhesive 25.
Is fixed using. Each electrode pad 28 arranged in the center of the main surface of the semiconductor element 21 is connected to each inner lead 22 by a bonding wire 29.
【０００５】図８は従来の半導体装置の第３構成を示す
断面図で、ＣＯＬ（chip on lead）構造を示している。
半導体素子31の裏面と銀メッキされたインナリード32と
は、前記図７と同様の接着剤35を塗布した絶縁テープ36
を用いて固着される。半導体素子31主面上に配列された
各電極パッド38はボンディングワイヤ39により各インナ
リード32と接続される。FIG. 8 is a sectional view showing a third structure of a conventional semiconductor device, showing a COL (chip on lead) structure.
The back surface of the semiconductor element 31 and the silver-plated inner lead 32 are the insulating tape 36 coated with the same adhesive 35 as in FIG.
Is fixed using. Each electrode pad 38 arranged on the main surface of the semiconductor element 31 is connected to each inner lead 32 by a bonding wire 39.
【０００６】上記図６の構成は次のような問題がある。
エポキシ系のペースト12の液体成分は銀メッキされたイ
ンナリード16の粗い面を伝って、ワイヤボンディングし
た接続部17を覆い。ボンディング性を著しく劣化させ
る。The structure shown in FIG. 6 has the following problems.
The liquid component of the epoxy paste 12 travels along the rough surface of the silver-plated inner lead 16 and covers the wire-bonded connection portion 17. Bondability is significantly deteriorated.
【０００７】上記図７，図８の構成は次のような問題が
ある。インナリード22（もしくは32）の配列間隔は微細
なため、絶縁テープ26（もしくは36）間でインナリード
の銀がマイグレーションを起こし、ショートに至る。ま
た、絶縁テープの接着剤25の熱硬化時やワイヤボンディ
ング時の熱工程において、接着剤25の成分がインナリー
ド22（もしくは32）伝って移動し図６と同様にボンディ
ング性を劣化させることもあげられる。The configurations shown in FIGS. 7 and 8 have the following problems. Since the inner leads 22 (or 32) are arranged at very small intervals, silver in the inner leads migrates between the insulating tapes 26 (or 36), resulting in a short circuit. In addition, the components of the adhesive 25 may move along the inner leads 22 (or 32) during the heat treatment of the adhesive 25 of the insulating tape during the heat curing or the wire bonding, which may deteriorate the bondability as in FIG. can give.
【０００８】[0008]
【発明が解決しようとする課題】このように、従来では
半導体素子とリードフレームを接合させるための接着剤
の成分がリードのワイヤボンディング部分に被覆し、ボ
ンディング性を劣化させたり、リード部の銀メッキが隣
列するリード間においてマイグレーションを起すという
欠点がある。As described above, conventionally, the component of the adhesive for bonding the semiconductor element and the lead frame covers the wire bonding portion of the lead, deteriorating the bonding property, and silver of the lead portion. There is a drawback that the plating causes migration between adjacent leads.
【０００９】この発明は、上記のような事情を考慮して
なされたものであり、その目的は、第１に、ボンディン
グ性を劣化させる接着剤の拡散を防止する構造、第２に
リードにおける銀メッキのマイグレーションを防止する
構造を有する半導体装置を提供することにある。The present invention has been made in consideration of the above circumstances, and its objects are, firstly, a structure for preventing diffusion of an adhesive which deteriorates the bonding property, and secondly, silver in a lead. An object of the present invention is to provide a semiconductor device having a structure that prevents migration of plating.
【００１０】[0010]
【課題を解決するための手段】この発明の半導体装置は
主面に複数の電極パッドが配置された半導体素子と、前
記半導体素子がリードフレームに固着されるための接着
部材と、前記リードフレームの一部であり前記各電極パ
ッドと電気的に接続される接続部と、前記接続部周辺に
設けられ前記接着部材の侵入を防ぐ阻止部材とを具備し
たことを特徴とする。A semiconductor device according to the present invention includes a semiconductor element having a plurality of electrode pads arranged on its main surface, an adhesive member for fixing the semiconductor element to a lead frame, and the lead frame. It is characterized by comprising a connection part which is a part and is electrically connected to each of the electrode pads, and a blocking member which is provided around the connection part and prevents the intrusion of the adhesive member.
【００１１】また、この発明の半導体装置は主面に複数
の電極パッドが配置された半導体素子と、前記半導体素
子に絶縁性の接着部材を介して固着される固着部分を有
するリードと、前記リードの一部であり少なくとも前記
固着部分を含んで前記各電極パッドと電気的に接続され
る領域以外を絶縁物で被覆したインナリード部とを具備
したことを特徴とする。In the semiconductor device of the present invention, a semiconductor element having a plurality of electrode pads arranged on its main surface, a lead having a fixing portion fixed to the semiconductor element via an insulating adhesive member, and the lead are provided. And an inner lead portion that covers at least the fixed portion and is electrically connected to each of the electrode pads, the inner lead portion being covered with an insulating material.
【００１２】[0012]
【作用】この発明では、インナリード部を阻止部材（面
の粗くないもの）、もしくは絶縁物で被覆し、ワイヤボ
ンディングされる部分だけを露出させ、接着剤がこのボ
ンディング部分まで拡散するのを防止し、さらにリード
の銀メッキのマイグレーションを防止する。According to the present invention, the inner lead portion is covered with a blocking member (having a rough surface) or an insulating material to expose only the portion to be wire-bonded and prevent the adhesive from diffusing to this bonding portion. In addition, the migration of lead silver plating is prevented.
【００１３】[0013]
【実施例】以下、図面を参照してこの発明を実施例によ
り説明する。図１はこの発明の第１実施例に係る半導体
装置の構成を示す上面図であり、半導体素子11がリード
フレ−ム10に固着される構成を示している。半導体素子
11とリードフレ−ムにおけるダイパッド15とはエポキシ
系のペースト12により固着されている。このダイパッド
15は銀メッキされたインナリード16のうちのインナリー
ド16-1と結合している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a top view showing the structure of a semiconductor device according to a first embodiment of the present invention, and shows a structure in which a semiconductor element 11 is fixed to a lead frame 10. Semiconductor element
11 and the die pad 15 of the lead frame are fixed to each other by an epoxy paste 12. This die pad
15 is connected to the inner lead 16-1 of the inner lead 16 plated with silver.
【００１４】すなわち、インナリード16-1はダイパッド
15を支持するつりピンを兼ねている。また、半導体素子
11動作時に安定した電位を確保するために、複数配置さ
れた電極パッド18のうちの所定の電極パッド18-1とイン
ナリード16-1とは電気的に例えばボンディングワイヤ19
により接続される。That is, the inner lead 16-1 is a die pad.
Also serves as a hanging pin that supports 15. Also, semiconductor devices
11 In order to secure a stable potential during operation, a predetermined electrode pad 18-1 of the plurality of electrode pads 18 and the inner lead 16-1 are electrically connected to, for example, a bonding wire 19
Connected by.
【００１５】インナリード16-1におけるボンディングワ
イヤ19との接続部41の周辺には、ペースト12の侵入を防
ぐ阻止部材42が被覆されている。この阻止部材42に用い
られる材料は例えばポリイミド系の樹脂であり、面が粗
くなく、鏡面に近い。これにより、接続部41へペースト
12の液体成分がしみ出るのを弾いて接続部41の汚染を防
止する。A block member 42 for preventing the invasion of the paste 12 is coated around the connection portion 41 of the inner lead 16-1 with the bonding wire 19. The material used for the blocking member 42 is, for example, a polyimide resin, the surface of which is not rough and is close to a mirror surface. By this, paste to the connection part 41
The 12 liquid components are repelled to prevent the connection portion 41 from being contaminated.
【００１６】上記構成によれば、銀メッキされたインナ
リード16-1の粗い面を伝って、ペースト12の液体成分が
移動するのを阻止部材42により遮断することができる。
この結果、インナリード16-1の接続部41のボンディング
の信頼性を維持することができる。According to the above construction, the blocking member 42 can block the movement of the liquid component of the paste 12 along the rough surface of the silver-plated inner lead 16-1.
As a result, the reliability of the bonding of the connecting portion 41 of the inner lead 16-1 can be maintained.
【００１７】また、インナリード16-1の反対側のインナ
リード16-2もつりピンを兼ねているとすれば、同様に所
定の電極パッド18-2と接続されることになる。この場合
にもボンディングワイヤ19との接続部41の周辺には、ペ
ースト12の侵入を防ぐ阻止部材42が被覆されている。If the inner lead 16-2 on the opposite side of the inner lead 16-1 also serves as an entanglement pin, it is similarly connected to a predetermined electrode pad 18-2. Also in this case, a blocking member 42 for preventing the invasion of the paste 12 is coated around the connection portion 41 with the bonding wire 19.
【００１８】図２、図３はそれぞれこの発明の第２実施
例に係るＬＯＣ（lead on chip）構造の半導体装置の構
成を示しており、図２は上面図、図３は図２の３Ａ−３
Ａ断面図である。2 and 3 show the structure of a semiconductor device having a LOC (lead on chip) structure according to a second embodiment of the present invention. FIG. 2 is a top view and FIG. 3 is 3A- of FIG. Three
FIG.
【００１９】半導体素子21の主面と銀メッキされたイン
ナリード22とは、両面に熱硬化性の接着剤25を塗布した
ポリイミド等の絶縁テープ26により固着される。半導体
素子21主面中央に配列された各電極パッド28はボンディ
ングワイヤ29により各インナリード22と接続される。The principal surface of the semiconductor element 21 and the silver-plated inner lead 22 are fixed to each other by an insulating tape 26 such as polyimide whose both surfaces are coated with a thermosetting adhesive 25. Each electrode pad 28 arranged in the center of the main surface of the semiconductor element 21 is connected to each inner lead 22 by a bonding wire 29.
【００２０】インナリード22はボンディングワイヤ29と
の接続領域44を除いて、絶縁テープ26との固着部分を含
みポリイミド系の絶縁樹脂45で被覆されている。これに
より、インナリードの銀がマイグレーションを起こすの
を防止する。The inner lead 22 is covered with a polyimide-based insulating resin 45 including a portion to be fixed to the insulating tape 26, except for a connecting region 44 with the bonding wire 29. This prevents the inner lead silver from migrating.
【００２１】図４、図５はそれぞれこの発明の第３実施
例に係るＣＯＬ（chip on lead）構造の半導体装置の構
成を示しており、図４は上面図、図５は図４の５Ａ−５
Ａ断面図である。FIGS. 4 and 5 respectively show the structure of a semiconductor device having a COL (chip on lead) structure according to a third embodiment of the present invention. FIG. 4 is a top view, and FIG. 5 is 5A- in FIG. 5
FIG.
【００２２】半導体素子31の裏面と銀メッキされたイン
ナリード32とは、前記図３と同様の接着剤35を塗布した
絶縁テープ36を用いて固着される。すなわち、インナリ
ード32は半導体素子31のベッドを兼ねる。半導体素子31
主面上に配列された各電極パッド38はボンディングワイ
ヤ39により各インナリード32と接続される。The back surface of the semiconductor element 31 and the silver-plated inner lead 32 are fixed to each other using an insulating tape 36 coated with an adhesive 35 similar to that shown in FIG. That is, the inner lead 32 also serves as a bed for the semiconductor element 31. Semiconductor element 31
Each electrode pad 38 arranged on the main surface is connected to each inner lead 32 by a bonding wire 39.
【００２３】インナリード32はボンディングワイヤ39と
の接続領域54を除いて、絶縁テープ36との固着部分を含
んでポリイミド系の絶縁樹脂55で被覆されている。これ
により、インナリード32の銀がマイグレーションを起こ
すのを防止する。The inner lead 32 is covered with a polyimide-based insulating resin 55 including a portion to be fixed to the insulating tape 36 except for a connection area 54 with the bonding wire 39. This prevents the silver of the inner lead 32 from migrating.
【００２４】上記図２〜図５の構成によれば、インナリ
ード22（もしくは32）の隣列間において、インナリード
の銀が絶縁テープ26を介してマイグレーションを起こす
ことがなくなり、インナリード22（もしくは32）間のシ
ョートが防止される。また、絶縁テープ26（もしくは3
6）の接着剤25（もしくは35）が移動してボンディング
性を劣化させることも抑えられる。2 to 5, the silver of the inner leads 22 (or 32) is prevented from migrating through the insulating tape 26 between the adjacent rows of the inner leads 22 (or 32), and the inner leads 22 ( Or short circuit between 32) is prevented. Insulating tape 26 (or 3
It is also possible to prevent the adhesive 25 (or 35) of 6) from moving to deteriorate the bonding property.
【００２５】[0025]
【発明の効果】以上説明したようにこの発明によれば、
インナリード部のボンディング領域周辺に阻止部材を被
覆する、あるいはインナリード部をボンディング領域を
除いて絶縁物で被覆することにより、接着剤の侵入、イ
ンナリードの銀のマイグレーションを防ぐことができる
高信頼性の半導体装置を提供することができる。As described above, according to the present invention,
By coating the blocking material around the bonding area of the inner lead part or by covering the inner lead part with an insulator excluding the bonding area, it is possible to prevent the intrusion of adhesive and the migration of silver of the inner lead. It is possible to provide a conductive semiconductor device.
【図１】この発明の第１実施例に係る半導体装置の構成
を示す上面図。FIG. 1 is a top view showing the configuration of a semiconductor device according to a first embodiment of the invention.
【図２】この発明の第２実施例に係る半導体装置の構成
を示す上面図。FIG. 2 is a top view showing a configuration of a semiconductor device according to a second embodiment of the present invention.
【図３】図２の３Ａ−３Ａ断面図。3A is a cross-sectional view taken along line 3A-3A in FIG.
【図４】この発明の第３実施例に係る半導体装置の構成
を示す上面図。FIG. 4 is a top view showing the configuration of a semiconductor device according to a third embodiment of the invention.
【図５】図４の５Ａ−５Ａ断面図。5A is a cross-sectional view taken along line 5A-5A of FIG.
【図６】従来の半導体装置の第１構成を示す上面図。FIG. 6 is a top view showing a first configuration of a conventional semiconductor device.
【図７】従来の半導体装置の第２構成を示す上面図。FIG. 7 is a top view showing a second configuration of the conventional semiconductor device.
【図８】従来の半導体装置の第２構成を示す上面図。FIG. 8 is a top view showing a second configuration of the conventional semiconductor device.
10…リードフレーム、11，21，31…半導体素子、12…ペ
ースト、15…ダイパッド、16，16-1，16-2，22，32…イ
ンナリード、17…、18，18-1，18-2，28，38…電極パッ
ド、19，29，39…ボンディングワイヤ、35…接着剤、2
6，36…絶縁テープ、41…接続部、42…阻止部材、44，5
4…接続領域、45，55…絶縁樹脂。10 ... Lead frame, 11, 21, 31 ... Semiconductor element, 12 ... Paste, 15 ... Die pad, 16, 16-1, 16-2, 22, 32 ... Inner lead, 17 ..., 18, 18-1, 18- 2, 28, 38 ... Electrode pad, 19, 29, 39 ... Bonding wire, 35 ... Adhesive, 2
6, 36 ... Insulating tape, 41 ... Connection part, 42 ... Blocking member, 44, 5
4 ... Connection area, 45, 55 ... Insulating resin.
Claims (2)
導体素子と、 前記半導体素子がリードフレームに固着されるための接
着部材と、 前記リードフレームの一部であり前記各電極パッドと電
気的に接続される接続部と、 前記接続部周辺に設けられ前記接着部材の侵入を防ぐ阻
止部材とを具備したことを特徴とする半導体装置。1. A semiconductor element having a plurality of electrode pads arranged on a main surface thereof, an adhesive member for fixing the semiconductor element to a lead frame, and a portion of the lead frame which is electrically connected to each of the electrode pads. A semiconductor device comprising: a connection portion that is electrically connected; and a blocking member that is provided around the connection portion and that prevents the intrusion of the adhesive member.
導体素子と、 前記半導体素子に絶縁性の接着部材を介して固着される
固着部分を有するリードと、 前記リードの一部であり少なくとも前記固着部分を含ん
で前記各電極パッドと電気的に接続される領域以外を絶
縁物で被覆したインナリード部とを具備したことを特徴
とする半導体装置。2. A semiconductor element having a plurality of electrode pads arranged on a main surface, a lead having a fixing portion fixed to the semiconductor element via an insulating adhesive member, and at least a part of the lead. A semiconductor device, comprising: an inner lead portion including an insulating material except a region including the fixed portion and electrically connected to each electrode pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4281886A JPH06132455A (en) | 1992-10-20 | 1992-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4281886A JPH06132455A (en) | 1992-10-20 | 1992-10-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06132455A true JPH06132455A (en) | 1994-05-13 |
Family
ID=17645343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4281886A Pending JPH06132455A (en) | 1992-10-20 | 1992-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06132455A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009038164A (en) * | 2007-08-01 | 2009-02-19 | Sumitomo Metal Electronics Devices Inc | Ceramic package for housing semiconductor element, and manufacturing method thereof |
| US7692292B2 (en) | 2003-12-05 | 2010-04-06 | Panasonic Corporation | Packaged electronic element and method of producing electronic element package |
-
1992
- 1992-10-20 JP JP4281886A patent/JPH06132455A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7692292B2 (en) | 2003-12-05 | 2010-04-06 | Panasonic Corporation | Packaged electronic element and method of producing electronic element package |
| JP2009038164A (en) * | 2007-08-01 | 2009-02-19 | Sumitomo Metal Electronics Devices Inc | Ceramic package for housing semiconductor element, and manufacturing method thereof |
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