JPS61174755A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPS61174755A
JPS61174755A JP1629085A JP1629085A JPS61174755A JP S61174755 A JPS61174755 A JP S61174755A JP 1629085 A JP1629085 A JP 1629085A JP 1629085 A JP1629085 A JP 1629085A JP S61174755 A JPS61174755 A JP S61174755A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
mounting part
element mounting
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1629085A
Other languages
Japanese (ja)
Inventor
Mitsumasa Tsutsui
筒井 光正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP1629085A priority Critical patent/JPS61174755A/en
Publication of JPS61174755A publication Critical patent/JPS61174755A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Abstract

PURPOSE:To suppress intrusion of moisture, by forming an element mounting part by an insulating material having excellent adhesion property with a sealing resin, and bonding and fixing the mounting part to one end of each lead in the sealing resin. CONSTITUTION:An element mounting part 6 is broadly formed by using an insulating material. The peripheral part of the mounting part is fixed to the lower surface of the end part of each lead 1 by a bonding agent and the like. An element 4 is mounted and fixed on the mounting part 6 by the bonding agent and the like. Thereafter, wire bonding and resin sealing are performed. Since the mounting part 6 is not exposed to the outside of a package directly, intrusion of moisture can be suppressed and reliability can be enhanced.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a resin-sealed semiconductor device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来広く用いられている樹脂封止型半導体装置の構造を
第2図および第3図に示す。
The structure of a conventionally widely used resin-sealed semiconductor device is shown in FIGS. 2 and 3.

樹脂封止型半導体装置は一般にリードのフレームのベッ
ド部上に半導体チップを搭載し、この半導体チップとリ
ードとの間にワイヤボンディングを施した後樹脂封止し
てパッケージを構成し、パッケージ外に突出するリード
をパッケージごとに切り離して製作される。
Resin-sealed semiconductor devices generally have a semiconductor chip mounted on the bed of a lead frame, wire bonding is performed between the semiconductor chip and the leads, and then resin-sealed to form a package. Manufactured by cutting out the protruding leads for each package.

半導体チップ4を搭載するための素子搭載部となるベッ
ド3は通常リードフレームの中央部に形成され、タイバ
ー2によってフレームに固定支持されている。半導体チ
ップの上面周辺部に形成される電極と電気的接続を行な
うためのり一部1は、ベッド3の周囲にその一端が近接
するように放射状に配列されている。
A bed 3 serving as an element mounting portion on which a semiconductor chip 4 is mounted is usually formed at the center of the lead frame, and is fixedly supported by tie bars 2 to the frame. Glue portions 1 for making electrical connection with electrodes formed on the upper peripheral portion of the semiconductor chip are arranged radially such that one end thereof is close to the periphery of the bed 3.

第2図の構造では、前述したベッド3を保持するタイバ
ーをリード1の一部と兼用して用いられているが、第3
図に示す構造ではタイバー2′はリード1とは別に設け
られており、電気的に外部端子との接続は行なっていな
い。
In the structure shown in Fig. 2, the tie bar that holds the bed 3 described above is also used as a part of the lead 1, but the third
In the structure shown in the figure, the tie bar 2' is provided separately from the lead 1, and is not electrically connected to an external terminal.

このような構造の半導体装置では、ベッド3に半導体チ
ップ4をダイボンドし、半導体チップ上の電極とり一部
1の一端とをボンディングワイヤ5により接続した後、
リード1の他端を外部に突出させるように所定のモール
ド型内で封止樹脂10により成型加工しパッケージを構
成する。
In a semiconductor device having such a structure, the semiconductor chip 4 is die-bonded to the bed 3, and after connecting one end of the electrode portion 1 on the semiconductor chip with the bonding wire 5,
A package is constructed by molding the lead 1 with a sealing resin 10 in a predetermined mold so that the other end of the lead 1 protrudes to the outside.

第2図および第3図に示すいずれの構造の半導体装置も
ベッド3を保持しているタイバー2あるいは2′の他端
が封止樹脂10の外に露出している。
In each of the semiconductor devices shown in FIGS. 2 and 3, the other end of the tie bar 2 or 2' holding the bed 3 is exposed outside the sealing resin 10.

このような構造を持った樹脂封止型半導体装置は、セラ
ミックを使用したセラミックパッケージに比べて耐湿性
が一般に劣っている。その主な原因は封止樹脂10の外
部に突出したタイバー2と封止樹脂10との界面を経由
して外部からの水分がパッケージ内に導入され、半導体
素子4に到達するため、この水分により半導体チップ4
の劣化をIH<ことによる。
A resin-sealed semiconductor device having such a structure is generally inferior in moisture resistance to a ceramic package using ceramic. The main reason for this is that moisture from the outside is introduced into the package through the interface between the tie bar 2 protruding outside the sealing resin 10 and the sealing resin 10 and reaches the semiconductor element 4. semiconductor chip 4
This is due to the deterioration of IH.

なおリード1を介してパッケージ内部に進入した水分は
ボンディングワイヤ5を介して半導体素子4に到達する
ことも考えられるが、このような経路には形状に凹凸が
あり、またボンディングワイヤ5はきわめて細いため水
分の到達度がきわめて低いことから無視することができ
る。
It is also conceivable that the moisture that has entered the inside of the package via the leads 1 may reach the semiconductor element 4 via the bonding wires 5, but such a route has an uneven shape and the bonding wires 5 are extremely thin. Therefore, the degree of moisture reaching the area is extremely low and can be ignored.

このように従来の樹脂封止型半導体装置ではベッド3を
保持するためのタイバーが必要であり、このタイバーは
直接パッケージの外部に連通しているために、パッケー
ジ形成後にタイバー2と封止樹脂10との界面から進入
する水分を有効に阻止することができず信頼性が低いと
いう欠点を有している。
In this way, the conventional resin-sealed semiconductor device requires a tie bar to hold the bed 3, and since this tie bar is directly connected to the outside of the package, the tie bar 2 and the sealing resin 10 are connected to each other after the package is formed. It has the disadvantage of being unable to effectively prevent moisture from entering from the interface with the metal, resulting in low reliability.

〔発明の目的〕[Purpose of the invention]

本発明は前述した欠点を改善するためになされたもので
、水分の進入を最少限にとどめ半導体装置の信頼性を高
めることのできる樹脂封止型半導体装置を提供すること
を目的とする。
The present invention has been made to improve the above-mentioned drawbacks, and an object of the present invention is to provide a resin-sealed semiconductor device that can minimize the ingress of moisture and improve the reliability of the semiconductor device.

〔発明の概要〕[Summary of the invention]

上記目的達成のため、本発明はかかる樹脂封止型半導体
装置においては、素子搭載部と、この搭載部の周囲に一
端が近接して配列され、他端がパッケージ外部に突出す
る複数のリードとを有してなる樹脂封止型半導体装置に
おいて、前記素子搭載部が封止樹脂と密着性の良い絶縁
材料で形成され、その周縁部において前記各リードの一
端部の下面に固着され、かつ前記各リードを支持するよ
うにしており、水分が半導体チップに直接到達する経路
をしゃ断することによって劣化を防止し、信頼性を高め
ることができるものである。
To achieve the above object, the present invention provides such a resin-sealed semiconductor device including an element mounting part and a plurality of leads arranged close to each other around the mounting part, one end of which is arranged close to the other end of which protrudes outside the package. In the resin-sealed semiconductor device, the element mounting portion is formed of an insulating material that has good adhesion to the encapsulating resin, and its peripheral portion is fixed to the lower surface of one end of each of the leads, and Each lead is supported, and by blocking the path through which moisture directly reaches the semiconductor chip, deterioration can be prevented and reliability can be improved.

〔発明の実施例〕[Embodiments of the invention]

第1図は本発明の一実施例の平面構造を示す半導体装置
の横断面図である。
FIG. 1 is a cross-sectional view of a semiconductor device showing a planar structure of an embodiment of the present invention.

なお第2図および第3図に示したと同一部分には同一符
号を付しその説明は省略する。
Note that the same parts as shown in FIGS. 2 and 3 are given the same reference numerals, and the explanation thereof will be omitted.

従来の構造ではベッド3に接続されたタイバー2が封止
樹脂10中を延在してパッケージの外部に露出している
ことに最大の欠点があった。
The biggest drawback of the conventional structure is that the tie bar 2 connected to the bed 3 extends through the sealing resin 10 and is exposed to the outside of the package.

そこでこの発明ではタイバーをなりシ、かつ素子搭載部
が封止樹脂10の内部のみに存在するように構成してい
る。すなわち、第1図に示すように絶縁材料を用いて素
子搭載部6を従来のベッド部周囲に存在するリードの一
端部を含むように広く形成し、その周縁部をリード1の
一端下面に接着剤等で固着する。このような構造を採用
することによって従来のように素子搭載部をタイバーを
介してリードフレームに直接固定する必要が無くなる。
Therefore, in the present invention, the tie bar is omitted and the element mounting portion is configured to exist only inside the sealing resin 10. That is, as shown in FIG. 1, the element mounting part 6 is formed using an insulating material to be wide enough to include one end of the lead that exists around the conventional bed part, and its peripheral part is glued to the lower surface of one end of the lead 1. Fix with adhesive etc. By adopting such a structure, there is no need to directly fix the element mounting portion to the lead frame via tie bars as in the conventional case.

そしてこの素子搭載部6上に半導体素子4を接着剤等で
搭載、固着したのち周知の方法でワイヤボンディングお
よび樹脂封止を実行することにより半導体装置が完成す
る。
After mounting and fixing the semiconductor element 4 on the element mounting portion 6 with an adhesive or the like, wire bonding and resin sealing are performed by well-known methods to complete the semiconductor device.

なお第1図に示した実施例はDIR(デュアルインライ
ンパッケージ)タイプのものであるが、半導体チップを
搭載するベッド部がタイバーを介してフレームに支持さ
れている他のタイプの樹脂封止型半導体装置にも適用で
きるのはいうまでもない。
The embodiment shown in FIG. 1 is of the DIR (dual in-line package) type, but other types of resin-sealed semiconductors in which the bed section on which the semiconductor chip is mounted are supported by the frame via tie bars are also applicable. Needless to say, it can also be applied to devices.

なお、素子搭載領域6を形成するための絶縁材料として
は封止樹脂との密着性が良く、機械的強度にすぐれ、耐
熱性を有するものが使用され、例えばポリイミドテープ
が最適である。しかし、封止樹脂と密着性が良好であり
かつこの封止樹脂10との界面で水分が通りにくいもの
であればポリイミドに限定されることなく他の材料も使
用可能である。
As the insulating material for forming the element mounting area 6, an insulating material that has good adhesion to the sealing resin, excellent mechanical strength, and heat resistance is used; for example, polyimide tape is most suitable. However, other materials can be used without being limited to polyimide as long as they have good adhesion to the sealing resin and do not allow moisture to easily pass through the interface with the sealing resin 10.

また素子搭載部6の大きさは半導体素子4を搭載するた
めの十分な大きさとり一部1の一端を固定するに十分な
大きさとを有していることが必要である。
Further, the size of the element mounting portion 6 needs to be large enough to mount the semiconductor element 4 and large enough to fix one end of the portion 1.

この素子搭載領域6は封止樹脂10の外部に露出させて
はならないことは言うまでもない。
Needless to say, this element mounting area 6 must not be exposed to the outside of the sealing resin 10.

〔発明の効果〕〔Effect of the invention〕

以上実施例に基づいて詳細に説明したように、本発明で
は素子搭載部を封止樹脂の内部でリードとの一端に接着
し固定させて形成したので、素子搭載部が直接パッケー
ジの外部に露出することはなく水分が直接半導体チップ
に達することはない。
As described above in detail based on the embodiments, in the present invention, the element mounting part is formed by bonding and fixing it to one end of the lead inside the sealing resin, so the element mounting part is directly exposed to the outside of the package. This prevents moisture from directly reaching the semiconductor chip.

しかもこの素子搭載部を形成するための絶縁材料として
封止樹脂と密着性が良く水の通りにくい材料を用いてい
るため、パッケージの外部から水の進入があってもこの
水は凹凸のあるボンディングワイヤを通る経路からしか
半導体素子に到達しないため、従来の半導体装置に比べ
て格段に耐湿性の面において優れ、信頼性の向上を図る
ことができる。
Moreover, since the insulating material used to form this element mounting area is a material that has good adhesion to the sealing resin and is difficult for water to pass through, even if water enters from the outside of the package, this water will not pass through the uneven bonding area. Since the semiconductor device is reached only through the wire path, it has much better moisture resistance than conventional semiconductor devices, and can improve reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明による半導体装置の構成を示す横断面
図、第2図および第3図は従来の半導体装置の構造を示
す横断面図である。 1・・・リード、2.2′・・−タイバー、4・・・半
導体素子、5・・・ボンディングワイヤ、6・・・素子
搭載部、10・・・封止樹脂。
FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the present invention, and FIGS. 2 and 3 are cross-sectional views showing the structure of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Lead, 2.2'... - tie bar, 4... Semiconductor element, 5... Bonding wire, 6... Element mounting part, 10... Sealing resin.

Claims (1)

【特許請求の範囲】 1、素子搭載部と、この搭載部の周囲に一端が近接して
配列され、他端がパッケージ外部に突出する複数のリー
ドとを有してなる樹脂封止型半導体装置において、 前記素子搭載部が封止樹脂と密着性の良い絶縁材料で形
成され、その周縁部において前記各リードの一端部の下
面に固着され、かつ前記各リードを支持するようにして
なる樹脂封止型半導体装置。 2、絶縁材料がポリイミド樹脂であることを特徴とする
特許請求の範囲第1項記載の樹脂封止型半導体装置。
[Claims] 1. A resin-sealed semiconductor device comprising an element mounting portion and a plurality of leads having one end arranged close to the mounting portion and the other end protruding outside the package. In the above, the element mounting portion is formed of an insulating material that has good adhesion to the sealing resin, and the resin seal is fixed to the lower surface of one end of each of the leads at the peripheral edge thereof and supports each of the leads. Stop type semiconductor device. 2. The resin-sealed semiconductor device according to claim 1, wherein the insulating material is polyimide resin.
JP1629085A 1985-01-30 1985-01-30 Resin sealed type semiconductor device Pending JPS61174755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1629085A JPS61174755A (en) 1985-01-30 1985-01-30 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1629085A JPS61174755A (en) 1985-01-30 1985-01-30 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS61174755A true JPS61174755A (en) 1986-08-06

Family

ID=11912411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1629085A Pending JPS61174755A (en) 1985-01-30 1985-01-30 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS61174755A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63293961A (en) * 1987-05-27 1988-11-30 Hitachi Ltd Resin-sealed semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63293961A (en) * 1987-05-27 1988-11-30 Hitachi Ltd Resin-sealed semiconductor device

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