JPH0613156U - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JPH0613156U JPH0613156U JP052994U JP5299492U JPH0613156U JP H0613156 U JPH0613156 U JP H0613156U JP 052994 U JP052994 U JP 052994U JP 5299492 U JP5299492 U JP 5299492U JP H0613156 U JPH0613156 U JP H0613156U
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- semiconductor device
- semiconductor element
- lead frame
- protection function
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Abstract
(57)【要約】
【目的】 急激な電力印加に対しても、過熱保護機能が
確実に働く高信頼性の電力用半導体装置を実現する。
【構成】 過熱保護機能を有する制御用保護回路素子４
を、電力用半導体素子１上に、絶縁ぺースト５を介して
直接搭載する。
(57) [Abstract] [Purpose] To realize a highly reliable power semiconductor device in which the overheat protection function reliably operates even when a rapid power is applied. [Structure] Control protection circuit element 4 having overheat protection function
Are directly mounted on the power semiconductor element 1 via the insulating paste 5.
Description
【０００１】[0001]
本考案は電力用半導体装置に関し、特に過熱保護機能を有する制御素子を備え た電力用半導体装置に関する。 The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device including a control element having an overheat protection function.
【０００２】[0002]
従来の技術について図２を参照して説明する。 A conventional technique will be described with reference to FIG.
【０００３】 図２（ａ）は従来例による電力用半導体装置の平面図、図２（ｂ）は図２（ａ ）のＡ−Ａ’線断面図である。FIG. 2A is a plan view of a conventional power semiconductor device, and FIG. 2B is a sectional view taken along the line A-A ′ of FIG. 2A.
【０００４】 従来の電力半導体装置は、図２（ａ）の如く、パワートランジスタ等の電力用 半導体素子１をリードフレーム２のボトム２’上に、ハンダ３による共晶ダイボ ンドによって搭載する。In a conventional power semiconductor device, as shown in FIG. 2A, a power semiconductor element 1 such as a power transistor is mounted on a bottom 2 ′ of a lead frame 2 by a eutectic die bond by a solder 3.
【０００５】 そしてボトム２’の別の箇所に電力用半導体素子１を制御する制御用集積回路 素子（以下、単に制御素子と記す）４を絶縁ペースト５によるペーストダイボン ドによって搭載する。Then, a control integrated circuit element (hereinafter, simply referred to as a control element) 4 for controlling the power semiconductor element 1 is mounted on another portion of the bottom 2 ′ by a paste die bond made of an insulating paste 5.
【０００６】 ここで、制御素子４には、電力用半導体素子１の電力印加時に発する熱を感知 し、過熱時に電力用半導体素子１の動作を停止する過熱保護機能が設けられてい る。Here, the control element 4 is provided with an overheat protection function that senses heat generated when power is applied to the power semiconductor element 1 and stops the operation of the power semiconductor element 1 when overheated.
【０００７】 次に、Ａｕワイヤ６にて前記電力用半導体素子１と制御素子４及びリード端子 ７との電気的接続を行ない、最後に素子搭載部及びＡｕワイヤ接続部を樹脂封止 して電力用半導体装置が完成する。Next, the electric power semiconductor element 1 is electrically connected to the control element 4 and the lead terminal 7 by the Au wire 6, and finally, the element mounting portion and the Au wire connecting portion are resin-sealed so that electric power is supplied. Semiconductor device is completed.
【０００８】[0008]
【考案が解決しようとする課題】 ところで、前述の従来例による電力用半導体装置においては、電力用半導体素 子１と制御素子４がリードフレームのボトム２上に並置されている。従って、電 力用半導体素子１で発生した熱は、図１（ｂ）に示すように電力用半導体素子１ →ハンダ３→ボトム２→絶縁ペースト５→制御素子４の順で伝達される。By the way, in the above-described conventional power semiconductor device, the power semiconductor element 1 and the control element 4 are juxtaposed on the bottom 2 of the lead frame. Therefore, the heat generated in the power semiconductor element 1 is transferred in the order of the power semiconductor element 1 → solder 3 → bottom 2 → insulating paste 5 → control element 4 as shown in FIG.
【０００９】 つまり、電力用半導体素子１で発生した熱は制御素子４には即座に伝わらない 。That is, the heat generated in the power semiconductor element 1 is not immediately transferred to the control element 4.
【００１０】 このため、電力用半導体素子１に急激な電力が印加された場合、熱の伝達遅れ の為、制御素子４の過熱保護機能が働く前に電力用半導体素子１が破壊に到ると いう問題があった。Therefore, when abrupt power is applied to the power semiconductor element 1, the power semiconductor element 1 is destroyed before the overheat protection function of the control element 4 is activated due to heat transfer delay. There was a problem saying.
【００１１】 そこで本考案の目的は、急激な電力が印加された場合でも、電力用半導体素子 で発生した熱が制御素子に直ちに伝達され過熱保護機能が動作する高信頼性の電 力用半導体装置を提供することにある。Therefore, an object of the present invention is to provide a highly reliable power semiconductor device in which the heat generated in the power semiconductor element is immediately transferred to the control element and the overheat protection function operates even when sudden power is applied. To provide.
【００１２】[0012]
前記目的を達成するために本考案は、リードフレームと、該リードフレームに 搭載される電力用半導体素子と、該電力用半導体素子上に絶縁ペーストを介して 搭載される過熱保護機能を有する制御用保護回路素子とを有してなることを特徴 とする。 To achieve the above object, the present invention provides a lead frame, a power semiconductor device mounted on the lead frame, and a control device having an overheat protection function mounted on the power semiconductor device via an insulating paste. And a protection circuit element.
【００１３】[0013]
本考案の電力用半導体装置は、以上のような構造であるので、電力用半導体素 子で発生した熱は絶縁ペーストを介して直ちに制御素子に伝達される。 Since the power semiconductor device of the present invention has the above structure, the heat generated in the power semiconductor device is immediately transferred to the control element through the insulating paste.
【００１４】 従って急激な電力印加があった場合でも、過熱状態は制御素子で即座に検知さ れるので、電力用半導体素子は及び回路は確実に保護され信頼性を向上できる。Therefore, even when there is a sudden power application, the overheated state is immediately detected by the control element, so that the power semiconductor element and the circuit are surely protected and the reliability can be improved.
【００１５】 また、リードフレーム上に占める素子搭載領域は電力用半導体素子分のみで良 く小型化も図れる。Further, the element mounting area occupying on the lead frame is only the power semiconductor element, and the size can be reduced.
【００１６】[0016]
本考案の一実施例について図１を参照して説明する。図１（ａ）は本実施例に よる電力用半導体装置の平面図、図１（ｂ）は図１（ａ）のＢ−Ｂ’線断面図で ある。 An embodiment of the present invention will be described with reference to FIG. FIG. 1A is a plan view of the power semiconductor device according to the present embodiment, and FIG. 1B is a sectional view taken along the line B-B ′ of FIG.
【００１７】 なお、図２（ａ）及び（ｂ）に示した従来例と同一機能部分には同一記号を付 している。The same functional parts as those of the conventional example shown in FIGS. 2A and 2B are designated by the same reference numerals.
【００１８】 本実施例の電力用半導体装置は、図１（ａ）の如く、パワートランジスタ等の 電力用半導体素子１をリードフレーム２のボトム２’にハンダ３による共晶ダイ ボンドによって搭載する。In the power semiconductor device of this embodiment, as shown in FIG. 1A, the power semiconductor element 1 such as a power transistor is mounted on the bottom 2 ′ of the lead frame 2 by eutectic die bonding with solder 3.
【００１９】 そして、電力用半導体素子１の表面上に絶縁ペースト５を塗付し、その上に制 御素子４を搭載してペーストダイボンドを行う。Then, an insulating paste 5 is applied on the surface of the power semiconductor element 1, the control element 4 is mounted thereon, and paste die bonding is performed.
【００２０】 しかるのち、Ａｕワイヤ６にて電力用半導体素子１と制御素子４及びリード端 子７との電気的接続を行った後、素子搭載部及びＡｕワイヤ接続部を樹脂封止し 、電力用半導体装置が完成する。After that, after electrically connecting the power semiconductor element 1 to the control element 4 and the lead terminal 7 with the Au wire 6, the element mounting portion and the Au wire connecting portion are resin-sealed, Semiconductor device is completed.
【００２１】 以上のようにして得られた電力用半導体装置においては、電力用半導体素子１ で発生した熱は、電力用半導体素子１の表面より、絶縁ペースト５のみを介して 制御素子４に伝達する。この伝達熱が過熱状態にある場合は、過熱保護機能が働 き電力用半導体素子１の動作が停止する。In the power semiconductor device obtained as described above, the heat generated in the power semiconductor element 1 is transferred from the surface of the power semiconductor element 1 to the control element 4 via only the insulating paste 5. To do. When the transferred heat is in the overheated state, the overheat protection function is activated and the operation of the power semiconductor element 1 is stopped.
【００２２】 このように、本実施例の電力用半導体装置は従来の電力用半導体装置に比べ、 電力用半導体装置素子１−制御素子４間の介在物が少なく、熱伝導に優れており 、急激な電力印加に対しても応答性が良い。As described above, the power semiconductor device according to the present embodiment has less inclusions between the power semiconductor device element 1 and the control element 4 as compared with the conventional power semiconductor device, is excellent in heat conduction, and is sharp. Responsive to various electric power application.
【００２３】 従って、従来のように熱の伝達遅れのため、制御素子４の過熱保護機能が働く 前に電力用半導体素子１が破壊するといった問題を解消でき、信頼性を向上でき る。Therefore, it is possible to solve the problem that the power semiconductor element 1 is destroyed before the overheat protection function of the control element 4 is activated due to the delay of heat transfer as in the conventional case, and the reliability can be improved.
【００２４】 また、電力半導体素子１上に制御素子４を搭載することから、リードフレーム 上の素子搭載面積を低減でき小型化を図れる。或いは、同一ダイボンドエリアを 持つリードフレームにおいては、従来技術に比べ、よりチップサイズの大きい電 力用半導体素子１のダイボンドが可能となる。Further, since the control element 4 is mounted on the power semiconductor element 1, the element mounting area on the lead frame can be reduced and the size can be reduced. Alternatively, in a lead frame having the same die bond area, it is possible to die bond the power semiconductor device 1 having a larger chip size than the conventional technique.
【００２５】[0025]
以上説明したように、本考案によれば、電力用半導体素子と制御素子の間の熱 伝導性を向上でき、過熱保護機能の感度向上を図れ、信頼性の高い電力用半導体 装置を実現できる。 As described above, according to the present invention, the thermal conductivity between the power semiconductor element and the control element can be improved, the sensitivity of the overheat protection function can be improved, and a highly reliable power semiconductor device can be realized.
【００２６】 また、リードフレーム上に素子搭載面積を低減でき、小型化を図れる。Further, the element mounting area can be reduced on the lead frame, and the size can be reduced.
【図１】（ａ）は本考案の一実施例による電力半導体装
置の平面図、（ｂ）は（ａ）のＢ−Ｂ’線断面図であ
る。FIG. 1A is a plan view of a power semiconductor device according to an embodiment of the present invention, and FIG. 1B is a sectional view taken along line BB ′ of FIG.
【図２】（ａ）は従来例による電力半導体装置の平面
図、（ｂ）は（ａ）のＡ−Ａ’線断面図である。2A is a plan view of a power semiconductor device according to a conventional example, and FIG. 2B is a sectional view taken along the line AA ′ of FIG.
１ 電力用半導体素子 ２ リードフレーム ４ 制御素子 ５ 絶縁ぺースト 1 Power semiconductor element 2 Lead frame 4 Control element 5 Insulation paste
Claims (1)
搭載される電力用半導体素子と、該電力用半導体素子上
に絶縁ペーストを介して搭載される過熱保護機能を有す
る制御用集積回路素子とを有してなることを特徴とする
電力用半導体装置。1. A lead frame, a power semiconductor element mounted on the lead frame, and a control integrated circuit element having an overheat protection function mounted on the power semiconductor element via an insulating paste. A power semiconductor device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992052994U JP2602473Y2 (en) | 1992-07-28 | 1992-07-28 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992052994U JP2602473Y2 (en) | 1992-07-28 | 1992-07-28 | Power semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0613156U true JPH0613156U (en) | 1994-02-18 |
| JP2602473Y2 JP2602473Y2 (en) | 2000-01-17 |
Family
ID=12930484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1992052994U Expired - Fee Related JP2602473Y2 (en) | 1992-07-28 | 1992-07-28 | Power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2602473Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0281055U (en) * | 1988-12-09 | 1990-06-22 |
-
1992
- 1992-07-28 JP JP1992052994U patent/JP2602473Y2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0281055U (en) * | 1988-12-09 | 1990-06-22 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2602473Y2 (en) | 2000-01-17 |
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