JPH06131448A - V-ram device and pattern matching processor using same - Google Patents

Abstract

PURPOSE:To execute the multibit operation at a high speed by providing a V-RAM with a multibit operation circuit, a transfer circuit (transfer gate), and plural port parts where the operation result or the like is temporarily stored. CONSTITUTION:When input data is read out and is transferred to and held in a port part 6A of the V-RAM and a command for matching of dictionary data #1 to #n in the V-RAM is given to a pattern matching controller, this controller transfers dictionary data #1 in the V-RAM to a port part 6B. An operation circuit 4 performs pattern matching operation with data of ports 6A and 6B as inputs. After pattern matching, result data is inputted to a serial- parallel conversion part and is supplied to a counter as serial data synchronously with a clock. The counter counts the degree of pattern matching and counts the number of bit '1's to store it as matching result #1.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a V-RAM (video RA
M) a device and a pattern matching processing device using the same, and in particular, a V- having a pattern matching calculation function.
The present invention relates to a RAM device and a pattern matching processing system using the same.

[0002]

2. Description of the Related Art In the case of performing turn matching processing of two data, the amount of day processing capable of pattern matching at one time is about 32 bits at most. Even if the processing is performed by hardware, the number of processing bits is still in units of about 32 bits.

[0003]

As described above, in the conventional pattern matching processing system, the number of bits that can be processed at one time is about 32 bits at most. Therefore, it is extremely difficult to perform pattern matching processing for a large amount of data. It has the disadvantage of requiring a lot of time. Further, when the number of processing bits is increased, the circuit scale is increased in proportion thereto, which is disadvantageous in terms of hardware and impractical.

An object of the present invention is to provide a V-RA capable of internally performing pattern matching calculation processing on a large amount of data at high speed.
It is to provide an M device.

Another object of the present invention is to provide a pattern matching processing device capable of performing a large amount of pattern matching processing at one time using a V-RAM device capable of internally processing a large amount of data at high speed. It is to be.

[0006]

A V-RAM according to the present invention
The device includes a memory cell array, a plurality of port units each including a register for inputting / outputting data of the memory cell array, a selector that selectively selects the port units according to a port selection command, and a predetermined arithmetic operation. A first and second memory cell array including a functioning operation circuit and a transfer gate for controlling data exchange between the memory cell array, the port section, and the operation circuit according to an external input / output selection command. The second read data is stored in separate port sections, the first and second read data stored in the port sections are input to the arithmetic circuit to perform an operation, and the operation result data is stored in the port section. It is characterized in that it is configured to be led to the outside through one of the.

A pattern matching processing apparatus according to the present invention selects a memory cell array, a plurality of port portions each including a register for inputting / outputting data of the memory cell array, and the port portions according to a port selection command. A selector for selectively selecting, an arithmetic circuit having a pattern matching arithmetic function, and a transfer gate for controlling data exchange between the memory cell array, the port section, and the arithmetic circuit according to an external input / output selection command. And storing the first and second read data from the memory cell array in different port sections, respectively, and inputting the first and second read data stored in the port sections to the arithmetic circuit. A matching operation is performed, and this pattern matching operation result data is derived to the outside through one of the port units. V-RAM device configured as described above, counter means for counting the matching state of the pattern matching result data, and the matching state by the counter means while controlling the arithmetic operation of the V-RAM device. Control means for controlling to store at a predetermined address of the cell array.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a V-RAM device according to an embodiment of the present invention. The memory cell array 1 is V-RA
This is the basic memory of the M device, and in this example, 4096 × 40.
A 96-bit RAM is used. This RAM1
Addressing of row decoder 2 and column decoder 3
It is supposed to be done by.

This V-RAM device is provided with an arithmetic circuit 4 in addition to the RAM 1 so that 4096-bit parallel arithmetic can be performed at high speed. The arithmetic function of the arithmetic circuit 4 has the one shown in FIG. 2, and in FIG.
S2 represents a set of input bits to be operated, and 16 destinations (No. 0 to No. 15) of destination logic outputs are generated at high speed in response to an external 4-bit (0 to 3) operation select signal. . In addition, it has a bit shift function and can specify a shift amount and a shift direction.

Further, an input / output port 6A for the RAM1
6D to 6D are provided, and these port units 6A to 6D have a serial register configuration having a width of 4096 bits.

These RAM 1, arithmetic circuit 4, port section 6
A transfer gate 5 is provided between A to 6D, and the transfer gate 5 selectively controls the input / output relationship among the RAM 1, the arithmetic circuit 4, and the port units 6A to 6D.

A port select signal is supplied from the outside in order to select one of the four port units 6A to 6D, and the connection relation with the transfer gate 5 is selectively given according to the port select signal. It is determined and which output of these port units 6A to 6D is to be input to the arithmetic circuit 4 is determined by the selector 7 which operates according to the port select signal.

An example of a pattern matching processing system using the V-RAM device having such a configuration will be described with reference to the block diagram of FIG. The V-RAM 10 is the V shown in FIG.
-A RAM device, the CPU 11 controls the entire pattern matching process, and under the control of the CPU 11, the pattern matching controller 13 actually controls the operation of the V-RAM 10.

The serial-parallel conversion circuit 12 responds to the clock by the port 6 of the V-RAM 10 (port units 6A to 6D in FIG. 1).
1) is serial-parallel converted and supplied to the counter 14. The counter 14 counts the total of the bit "1" of the input data, and the count result indicates the degree of matching of the pattern matching, and the count result (matching result) is V through the data bus 15. -It is stored in a predetermined area in the RAM 10. still,
16 is an address bus.

FIG. 4 shows an example of a memory map in the V-RAM 10, which is input data to be pattern-matched, dictionary data (# 1 to #n), and a matching result (#).
1 to #n) are respectively stored or can be stored.

In the pattern matching process, first, the input data is read out and transferred to the port section 6A which is one of the ports in the V-RAM 10 and held therein. Next, for the pattern matching controller 13, the V-RAM
When a command is issued to perform matching of dictionary data # 1 to #n in 10, the matching controller 13 causes VR
The dictionary data # 1 in the AM 10 is transferred to the port unit 6B which is one of the ports.

The arithmetic circuit 4 receives the data of the ports 6A and 6B as inputs S1 and S2 and performs a pattern matching arithmetic operation. The type of this pattern matching calculation is determined by an instruction from the pattern matching controller 13. At this time, the arithmetic circuit 4 can perform 4096-bit arithmetic at a time, and high-speed processing is performed.

After the pattern matching, the matching result data is input to the serial-parallel converter 12 via the port 6A and is supplied to the counter 14 as serial data in synchronization with the clock. The counter 14 counts the degree of pattern matching, counts the number of bits “1”, and the result is the V-RAM 10.
It is stored in the matching result # 1 in the above.

The above operation is sequentially performed on the dictionary data # 2 to #n, and when all the processing is completed, the VR operation is completed.
When the matching results # 1 to #n stored in the AM 10 are sorted, the pattern matching processing of the dictionaries # 1 to #n is completed.

In the above embodiment, the number of bits that can be subjected to the matching process at one time is 4096, but the number is not limited to this. Further, the number of port portions may be two or more.

[0022]

As described above, according to the present invention, V-RA
Since a multi-bit arithmetic circuit, a transfer circuit (transfer gate), and a plurality of port sections for temporarily storing the arithmetic result and the like are provided inside M, the multi-bit arithmetic can be performed at high speed at once in the V-RAM. The effect is that it can be executed.

This is particularly effective when a large amount of data needs to be processed at high speed, such as pattern matching processing, and is only effective inside the V-RAM incorporated in one IC.
Since a large amount of data is exchanged, the transfer between ICs becomes unnecessary, the speed is remarkably improved, and the circuit scale is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a V-RAM device according to an embodiment of the present invention.

FIG. 2 is a diagram showing types of operations of the arithmetic circuit of FIG.

FIG. 3 is a block diagram showing a pattern matching processing system according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of a memory map in V-RAM.

[Explanation of symbols]

 1 Memory Cell Array (RAM) 2 Row Decoder 3 Column Decoder 4 Operation Circuit 5 Transfer Gate 6A to 6D Port 7 Selector 10 V-RAM 11 CPU 12 Serial / Parallel Conversion Circuit 13 Pattern Matching Controller 14 Counter

Claims (3)

[Claims] 1. A memory cell array, a plurality of port units each comprising a register for inputting / outputting data of the memory cell array, and a selector for selectively selecting the port units according to a port selection command. An arithmetic circuit having a predetermined arithmetic function, the memory cell array, the port section,
A transfer gate that controls the exchange of data between the arithmetic circuits according to an external input / output selection command, and stores the first and second read data from the memory cell array in separate port sections, The first and second read data stored in the port section is input to the arithmetic circuit to perform an operation, and the operation result data is derived to the outside through one of the port sections. V-RAM device characterized by: 2. The V-RAM device according to claim 1, wherein the arithmetic circuit has a plurality of arithmetic functions, and a predetermined arithmetic function can be selected according to an external command. 3. A memory cell array, a plurality of port units each comprising a register for inputting / outputting data of the memory cell array, and a selector for selectively selecting the port units according to a port selection command. An arithmetic circuit having a pattern matching arithmetic function, the memory cell array,
First and second transfer gates from the memory cell array, the transfer gate controlling transfer of data between the port unit and the arithmetic circuit according to an external input / output selection command.
Read data is stored in separate port portions, the first and second read data stored in the port portions are input to the arithmetic circuit to perform pattern matching calculation, and the pattern matching calculation result data is stored in the V-RAM configured to lead to the outside through one of the port sections
Apparatus, counter means for counting the matching state of the pattern matching result data, and storing the matching state by the counter means in a predetermined address of the memory cell array of the V-RAM device while controlling the arithmetic operation of the V-RAM device. And a control means for controlling so that the pattern matching processing device.