JPH0612767B2 - Groove and etching method thereof - Google Patents
Groove and etching method thereofInfo
- Publication number
- JPH0612767B2 JPH0612767B2 JP1002084A JP1002084A JPH0612767B2 JP H0612767 B2 JPH0612767 B2 JP H0612767B2 JP 1002084 A JP1002084 A JP 1002084A JP 1002084 A JP1002084 A JP 1002084A JP H0612767 B2 JPH0612767 B2 JP H0612767B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- etching
- present
- resistant coating
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005530 etching Methods 0.000 title claims description 40
- 238000000034 method Methods 0.000 title claims description 7
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、ドライエツチングによりシリコン溝および、
その形成法に係り、特にサイドエツチングを少なくして
高精度に形成された深い溝およびそれを形成するのに好
適なエツチング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention relates to a silicon groove by dry etching, and
More particularly, the present invention relates to a deep groove formed with a high degree of precision by reducing side etching and an etching method suitable for forming the deep groove.
Ｓｉ（シリコン）のドライエツチングには、従来よりＣ
Ｆ4を始めとするフツ素系のガスあるいはＣＣｌ4を始め
とする塩素系ガスを主成分とするガスが用いられてき
た。しかし、このようなガスによるドライエツチングだ
けで深い溝を形成しようとすると、第１図に示すように
アンダーカツト３（マスクＦ部へのエツチングのまわり
込み）や、第２図に示すような溝中央部のふくらみ４な
どサイドエツテング（横方向へのエツチング）が生じ易
く、加工精度上の問題となつていた。ここで、各図の１
は基板、２１はマスクである。Conventionally, C has been used for dry etching of Si (silicon).
Fluorine-based gas such as F 4 or gas mainly containing chlorine-based gas such as CCl 4 has been used. However, if a deep groove is to be formed only by dry etching with such a gas, the undercut 3 (wrapping around the etching into the mask F portion) as shown in FIG. 1 and the groove as shown in FIG. Side etching (etching in the lateral direction) such as the bulge 4 in the central portion is likely to occur, which is a problem in terms of processing accuracy. Where 1 in each figure
Is a substrate and 21 is a mask.
本発明の目的は、上記の欠点を解消した溝および深い溝
を形成してもサイドエツチングが少ないエツチング法を
提供することにある。It is an object of the present invention to provide an etching method which eliminates the above-mentioned drawbacks and has little side etching even if a groove and a deep groove are formed.
本発明は、ドライエツチングで発生するサイドエツチン
グをＳｉ溝の側壁に形成した耐エツチング性被膜で抑制
しようとするものである。The present invention is intended to suppress side etching generated by dry etching with an etching resistant coating formed on the side wall of the Si groove.
以下、本発明を実施例を参照して詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to examples.
第３図は本発明のエツチング工程を示す図である。先
ず、同図(1)に示すようにＳｉ基板１上に例えばＳｉＯ2
膜（酸化膜）Ｓｉ3Ｎ4膜（窒化膜）などのエツチングマ
スク２を形成した後、ＣＦ4あるいはＳＦ6などのフツ素
系ガスでＳｉ溝を浅くエツチングして、Ｓｉ溝５を形成
する。次に、該Ｓｉ溝の内面を耐エツチング性被膜で被
覆した後、耐エツチング性被膜を異方性エツチングし
て、(2)に示すようにＳｉ溝の底面６の耐エツチング性
被膜を除去し、Ｓｉ溝の側壁のみが耐エツチング性被膜
７で被覆されるようにする。上記耐エツチング性被膜と
しては、プラズマ酸化あるいは堆積によるＳｉＯ2膜を
用いることが好ましい。プラズマ酸化は、エツチングガ
スのかわりにＯ2ガスを導入して放電すればよい。ま
た、堆積は、例えばＳｉＣｌ4−Ｏ2混合ガスを導入して
放電することによつて行うことができる。FIG. 3 is a diagram showing an etching process of the present invention. First, as shown in FIG. 1A, for example, SiO 2 is formed on the Si substrate 1.
After forming the etching mask 2 such as a film (oxide film) Si 3 N 4 film (nitride film), the Si groove is shallowly etched with a fluorine-based gas such as CF 4 or SF 6 to form the Si groove 5. . Next, after the inner surface of the Si groove is coated with an etching resistant coating, the etching resistant coating is anisotropically etched to remove the etching resistant coating on the bottom surface 6 of the Si groove as shown in (2). , The sidewalls of the Si groove are covered with the etching resistant film 7. As the etching resistant film, it is preferable to use a SiO 2 film formed by plasma oxidation or deposition. The plasma oxidation may be performed by introducing O 2 gas instead of the etching gas and discharging. Further, the deposition can be performed, for example, by introducing a SiCl 4 —O 2 mixed gas and discharging.
上記の工程をさらにもう一度繰り返した後、さらにＳｉ
のエツチングを行なうと、(3)の如きＳｉ溝を得る。After repeating the above process once more,
Etching is performed to obtain a Si groove as shown in (3).
以上のようにしてＳｉ溝を形成すると、アンダーカツト
は第１図のａ1から第３図(3)のｂ1のように低減でき
る。本実施例では、Ｓｉのエツチングを３回に分割して
いるので、ｂ1はａ1の３分の１になる。When the Si groove is formed as described above, the undercut can be reduced from a 1 in FIG. 1 to b 1 in FIG. 3 (3). In this embodiment, since the divided three times etching of Si, b 1 is one third of a 1.
また、溝中央部のふくらみによるサイドエツチングも本
発明により第２図のａ2から第４図のｂ2に低減できるこ
とは明らかである。It is also apparent that the present invention can reduce side etching due to the bulge at the center of the groove from a 2 in FIG. 2 to b 2 in FIG.
本発明により形成したＳｉ溝には、第３図(3)および第
４図に示す如くＳｉ溝側壁に波形が付くのが特徴であ
る。The Si groove formed by the present invention is characterized in that the side wall of the Si groove is corrugated as shown in FIGS. 3 (3) and 4.
本発明のＳｉエツチングをさらに多段階に分割すること
によりＳｉ溝側壁の波形の高さを減少させ、見かけ上垂
直なＳｉ溝を形成することもできる。By dividing the Si etching of the present invention into multiple steps, the height of the corrugation on the side wall of the Si groove can be reduced to form an apparently vertical Si groove.
逆に、アンダーカツトあるいはサイドエツチングが生じ
易いエツチング条件を用いて本発明によるＳｉ溝の形成
を行なうと、第５図，第６図の如くＳｉ溝の側壁に大き
な波形を形成することもできる。このような溝は、例え
ば第７図に示すような凹形のキヤパシタの形成に用いる
と、面積効率を良くすることができる。すなわち、第７
図では、溝表面に絶縁膜１２と電極１３を形成してＭＩ
Ｓ型キヤパシタを構成しているが、溝側壁がしわ状にな
つているため、同じ深さで垂直な溝を形成した場合に比
べてキヤパシタ面積が大きくなる。On the contrary, if the Si groove is formed according to the present invention under the etching condition where undercutting or side etching is likely to occur, a large corrugation can be formed on the side wall of the Si groove as shown in FIGS. When such a groove is used to form a concave capacitor as shown in FIG. 7, for example, the area efficiency can be improved. That is, the seventh
In the figure, the insulating film 12 and the electrode 13 are formed on the groove surface, and MI
Although the S-type capacitor is formed, since the groove side wall is wrinkled, the capacitor area is larger than that when a vertical groove is formed at the same depth.
なお、本発明ではＳｉのエツチングと耐エツチング性被
膜の形成とを別々に行なつているが、これを同時に行な
うためにＳｉエツチングガスにＯ2ガスを多量混合して
定常的にエツチング面に被膜を形成しようとすると、エ
ツチング速度が著しく低下したり、エツチング面が荒れ
たりするので好ましくない。In the present invention, the etching of Si and the formation of the etching resistant coating are carried out separately, but in order to carry out this simultaneously, a large amount of O 2 gas is mixed with the Si etching gas to constantly coat the etching surface. However, it is not preferable because the etching speed is remarkably reduced and the etching surface is roughened.
以上説明したように、本発明によつてＳｉ溝をｎ分割し
てエツチングすると、サイドエツチ量ａをａ／ｎに低減
できるので、高精度にＳｉ溝を形成できる。As described above, according to the present invention, when the Si groove is divided into n parts and etched, the side etching amount a can be reduced to a / n, so that the Si groove can be formed with high accuracy.
第１図，第２図は従来法によるＳｉ溝の例を示す断面
図、第３図〜第６図は本発明におけるＳｉ溝の例を示す
断面図、第７図は本発明によるＳｉ溝を用いて形成した
凹形のキヤパシタの例を示す断面図である。 １……Ｓｉ基板、２……エツチングマスク、３……アン
ダーカツト、４……サイドエツチング、５……Ｓｉ溝、
６……Ｓｉ溝の底面、７〜１１……耐エツチング性被
膜、１２……絶縁膜、１３……電極。1 and 2 are sectional views showing an example of a Si groove according to a conventional method, FIGS. 3 to 6 are sectional views showing an example of a Si groove according to the present invention, and FIG. 7 is a sectional view showing an Si groove according to the present invention. It is sectional drawing which shows the example of the concave type capacitor formed using. 1 ... Si substrate, 2 ... etching mask, 3 ... undercut, 4 ... side etching, 5 ... Si groove,
6 ... Bottom of Si groove, 7-11 ... Etching resistant coating, 12 ... Insulating film, 13 ... Electrode.
Claims (4)
が深さ方向で周期的に増減することを特徴とする溝。1. A groove formed on the surface of a silicon substrate, wherein the width of the opening is periodically increased and decreased in the depth direction.
ッチングマスクを形成する工程と、その後、露出された
該基板表面をドライエッチングして溝を形成する工程と
該溝の内面を耐エッチング性被膜で被覆する工程と該溝
の底面の該耐エッチング性被膜を除去して該底面を露出
する工程とを順次繰返し行なうことによりシリコン溝を
形成することを特徴とするエッチング方法。2. A step of forming an etching mask having a desired shape on the surface of a silicon substrate, a step of forming a groove by dry etching the exposed surface of the substrate, and an etching resistant coating on the inner surface of the groove. And a step of removing the etching resistant coating on the bottom surface of the groove to expose the bottom surface, so that a silicon groove is formed.
ラズマを用いて行なうことを特徴とする特許請求の範囲
第２項に記載のエッチング方法。3. The etching method according to claim 2, wherein the dry etching is performed using plasma of a reactive gas.
あるいは堆積により形成されたＳｉＯ2膜であることを
特徴とする特許請求の範囲第２項または第３項に記載の
エッチング方法。4. The etching method according to claim 2 or 3, wherein the etching resistant film is a SiO 2 film formed by plasma oxidation or deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1002084A JPH0612767B2 (en) | 1984-01-25 | 1984-01-25 | Groove and etching method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1002084A JPH0612767B2 (en) | 1984-01-25 | 1984-01-25 | Groove and etching method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60154622A JPS60154622A (en) | 1985-08-14 |
| JPH0612767B2 true JPH0612767B2 (en) | 1994-02-16 |
Family
ID=11738714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1002084A Expired - Lifetime JPH0612767B2 (en) | 1984-01-25 | 1984-01-25 | Groove and etching method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0612767B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007504010A (en) * | 2003-08-29 | 2007-03-01 | コミサリア、ア、レネルジ、アトミク | Micromechanical device including a suspension element attached to a support by a pillar and method for manufacturing the same |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0665214B2 (en) * | 1985-05-17 | 1994-08-22 | 日本電信電話株式会社 | Method for manufacturing semiconductor device |
| JPS62201950U (en) * | 1986-06-13 | 1987-12-23 | ||
| JPH0821720B2 (en) * | 1990-05-30 | 1996-03-04 | 株式会社小電力高速通信研究所 | Method for manufacturing semiconductor device |
| EP0478283B1 (en) * | 1990-09-26 | 1996-12-27 | Hitachi, Ltd. | Microwave plasma processing method and apparatus |
| JPH07123106B2 (en) * | 1991-02-04 | 1995-12-25 | 日本電信電話株式会社 | Method and apparatus for manufacturing X-ray mask absorber |
| EP0729175A1 (en) * | 1995-02-24 | 1996-08-28 | International Business Machines Corporation | Method for producing deep vertical structures in silicon substrates |
| DE69934986T2 (en) * | 1998-07-23 | 2007-11-08 | Surface Technoloy Systems Plc | PROCESS FOR ANISOTROPIC CORES |
| US6235638B1 (en) * | 1999-02-16 | 2001-05-22 | Micron Technology, Inc. | Simplified etching technique for producing multiple undercut profiles |
| US6555480B2 (en) | 2001-07-31 | 2003-04-29 | Hewlett-Packard Development Company, L.P. | Substrate with fluidic channel and method of manufacturing |
| FR2834382B1 (en) * | 2002-01-03 | 2005-03-18 | Cit Alcatel | METHOD AND DEVICE FOR ANISOTROPIC SILICON ETCHING WITH HIGH ASPECT FACTOR |
| JP3823920B2 (en) | 2002-12-27 | 2006-09-20 | 三菱電機株式会社 | Electro-hydraulic power steering device |
| JP4578893B2 (en) * | 2004-08-20 | 2010-11-10 | 住友精密工業株式会社 | Plasma etching method and plasma etching apparatus for silicon material |
| JP2006351208A (en) * | 2005-06-13 | 2006-12-28 | Tokuden Co Ltd | Induction heating roller device |
| KR101174775B1 (en) * | 2005-08-29 | 2012-08-20 | 엘지디스플레이 주식회사 | method for manufacturing of printing plate |
| JP4812512B2 (en) | 2006-05-19 | 2011-11-09 | オンセミコンダクター・トレーディング・リミテッド | Manufacturing method of semiconductor device |
| KR100761408B1 (en) * | 2006-09-29 | 2007-09-27 | 주식회사 하이닉스반도체 | Bulb type recess gate and method for manufacturing the same |
| JP2009021584A (en) * | 2007-06-27 | 2009-01-29 | Applied Materials Inc | High temperature etching method of high k material gate structure |
| JP5913830B2 (en) * | 2011-04-21 | 2016-04-27 | 株式会社アルバック | Etching method of silicon substrate |
| KR101821413B1 (en) * | 2011-09-26 | 2018-01-24 | 매그나칩 반도체 유한회사 | An isolation structure, an semiconductor device comprising the isolation structure, and method for fabricating the isolation structure thereof |
| JP6207947B2 (en) | 2013-09-24 | 2017-10-04 | 東京エレクトロン株式会社 | Method for plasma processing a workpiece |
| US9054050B2 (en) * | 2013-11-06 | 2015-06-09 | Tokyo Electron Limited | Method for deep silicon etching using gas pulsing |
| CN105719965A (en) * | 2014-12-04 | 2016-06-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method and device for etching silicon dioxide substrate |
| JP6524562B2 (en) * | 2017-02-23 | 2019-06-05 | パナソニックＩｐマネジメント株式会社 | Element chip and method of manufacturing the same |
-
1984
- 1984-01-25 JP JP1002084A patent/JPH0612767B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007504010A (en) * | 2003-08-29 | 2007-03-01 | コミサリア、ア、レネルジ、アトミク | Micromechanical device including a suspension element attached to a support by a pillar and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60154622A (en) | 1985-08-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |