JPH0612503A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce a chip area and to prevent runaway. CONSTITUTION:This microcomputer is provided with an instruction decoder 1 which inputs an instruction bus INST and outputs an entry address ENTA, microprogram ROM 3 which inputs an address signal MA and outputs an entry status signal showing a next address NXTA and a start address in the case of instruction execution, address selector 2 to switch either the entry address ENTA or the next address NXTA and to supply it to the microprogram ROM 3 as an address MA microprogram while being controlled the selection by a microprogram start signal MATART, and trap signal generation circuit 9 equipped with an AND gate 6 to input the signal MATART through a delay circuit 4 to one input terminal, to input the entry status signal ENT showing the start address in the case of instruction execution from the ROM 3 through an inverter 5 to the other input terminal, and to output a trap signal TRAP.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a trap function for undefined instructions.

[0002]

2. Description of the Related Art Generally, a microcomputer, when fetching an instruction, analyzes it by an instruction decoder and performs an operation corresponding to the instruction.

In the microcomputer of the micro program control system, the output signal of the instruction decoder is a memory in which a program that describes how to operate internal hardware is stored, that is, the micro program RO.
It becomes the program start address of M (hereinafter referred to as the entry address).

Taking the next address method as an example, when the operation of the instruction extends over a plurality of steps of the microprogram, the next address is designated by the read data of the current microprogram.

The instruction decoder outputs a correct entry address for a defined instruction code, but when an undefined instruction code is erroneously input, the entry address is not what was originally expected and the microprogram ROM. The output data of will adversely affect the internal hardware and lead to abnormal operation of the microcomputer.

In order to prevent this, a dedicated decoder for decoding an undefined instruction is provided, and when an undefined instruction is detected, a signal indicating an abnormality (hereinafter referred to as a trap signal) is output, and this signal is used. There is a microcomputer that activates an interrupt control circuit or the like to prevent runaway.

FIG. 9 is a block diagram of an instruction analysis unit and a control unit of an example of a conventional microcomputer, and the micro program control is called a next address method.

It comprises an instruction bus INST, an instruction decoder 1, an address selector 2, a sequence connection of a microprogram ROM 3a and an undefined instruction decoder 1a. An instruction bus INST is inputted to the instruction decoder 1 and the undefined instruction decoder 1a. The entry address ENTA of the microprogram ROM 3a is output from the instruction decoder 1 and the trap signal TRA is output from the undefined instruction decoder 1a.
P outputs.

The entry address ENTA and the output (next address) NXTA of the microprogram ROM 3a are input to the address selector 2, and one of them is selected by the microprogram start signal MSTART and output as the address MA of the microprogram ROM 3a.

The micro program ROM 3a is a signal group CN for controlling internal hardware of the microcomputer.
T and the next address NXTA are output.

From the outside of the microcomputer, the instruction bus I
When the instruction code is fetched into the NST, the instruction decoder 1
Decodes this and outputs the entry address ENTA.

At the first timing in the execution of one instruction, the microprogram start signal MSTART has a logical value 1 (hereinafter referred to as "1"), and at this time, the address selector 2 sets the entry address ENTA to the address MA of the microprogram ROM 3a. Output as.

The microprogram ROM 3a outputs the control signal group CNT of the first step and controls the internal hardware of the microcomputer corresponding to the instruction.

The microprogram ROM 3a further outputs the next address NXTA, which corresponds to the address describing the operation of the internal hardware in the next step.

After the second step, the microprogram start signal MSTART has a logical value "0", and at this time, the address selector 2 causes the next address NXTA.
Is output as the address MA of the microprogram ROM 3a.

After the desired number of steps has been executed, the microprogram start signal M is again executed for execution of the next instruction.
START becomes “1”, and the entry address ENTA output from the instruction decoder 1 becomes the microprogram R.
It is supplied as the address MA of the OM 3a.

When an undefined instruction code is fetched into the instruction bus INST, the entry address ENTA is not what was originally expected and leads to abnormal operation of the microcomputer.

In order to prevent this, an undefined instruction decoder 1a is provided, a trap signal TRAP is output when an undefined instruction is detected, and this signal activates an interrupt control circuit or the like to prevent runaway. .

[0019]

The conventional microcomputer described above has a dedicated decoder for decoding an undefined instruction in order to prevent the microcomputer from running away.

Since this dedicated decoder needs to detect all combinations of undefined instructions, it generally requires a huge amount of hardware, increases the chip area of the microcomputer LSI, and raises the cost. was there.

An object of the present invention is to provide a microcomputer having a small chip area and no runaway.

[0022]

A microcomputer of the present invention has an instruction decoder for inputting an instruction bus and outputting an entry address, and a microprogram ROM for inputting an address signal and outputting a next address. A trap signal is provided when the instruction bus is an undefined instruction and is selectively controlled by a micro program start signal to select the entry address or the next address and supply it as an address to the micro program ROM. In a microcomputer having a trap signal generation circuit for generating, a data bit for an entry status signal indicating a start address in instruction execution is added to the micro program ROM, and the trap signal generation circuit receives the instruction execution start designation signal. And is configured to include a logic gate determining normality of the output of the instruction decoder to input said entry status signal.

Further, the microcomputer of the present invention inputs a hardware interrupt address generating circuit for outputting an interrupt entry address and the microcomputer program start signal and the interrupt processing instruction signal and logically processes them to generate the selection control signal. And an address selector control circuit for inputting the interrupt entry address to the microprogram R according to the selection control signal.
Except the timing supplied as the OM address,
The determination of the authenticity of the entry address is made invalid regardless of the logical value of the entry status signal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an instruction analysis unit and a control unit according to the first embodiment of the present invention. The microcomputer of this embodiment inputs the instruction bus INST to input the entry address EN.
An instruction decoder 1 which outputs TA, a microprogram ROM 3 which inputs an address signal MA and outputs an entry status signal indicating a start address in the next address NXTA and instruction execution, and an entry address which is selectively controlled by a microprogram start signal MATART. ENTA or next address NXT
An address selector 2 is supplied to the micro program ROM 3 as an address MA micro program by switching between A and A, and a micro program start signal MART is input to one input end via a delay circuit 4 and a micro input to the other input end. The program ROM 3 has a trap signal generation circuit 9 having an AND gate 6 which inputs an entry status signal ENT indicating a start address in executing an instruction through an inverter 5 and outputs a trap signal TRAP.

That is, in the microcomputer of this embodiment, the undefined instruction decoder 1a of the conventional microcomputer shown in FIG. 9 is deleted and a trap signal generating circuit 9 is provided in its place, and the microprogram ROM 3a starts the instruction execution. Instead of the microprogram 3, an entry status signal data bit indicating an address is added.

Therefore, since the operations of the instruction decoder 1, the address selector 2 and the micro program ROM 3 are the same as those of the conventional one, the explanation of the operation of the block is simplified, and the operation of the trap signal generation circuit 8 which is the main feature of this embodiment is mainly described. explain.

The entry status signal ENT is "1" at the first step of the instruction, that is, when the microprogram ROM 3 is designated by the entry address ENTA.
And becomes "0" after the second step of the instruction, that is, when the microprogram ROM 3 is designated by the next address NXTA.

FIG. 2 is a schematic diagram of an example of information described in the microprogram ROM 3. One word is composed of an entry status signal ENT, a control signal group CNT, and a next address NXTA.

Explaining the case where the instruction A is executed as an example, first, when the instruction code of the instruction A is fetched into the instruction bus INST, the instruction decoder 1 decodes it and outputs Ad0 as the entry address ENTA.

At this time, the micro program start signal MSTART is "1", and the address selector 2
The entry address Ad0 is stored in the microprogram ROM 3
Output as the address MA.

The microprogram ROM 3 outputs the control signal group CNT of the first step and controls the internal hardware of the microcomputer. The microprogram ROM 3 further outputs the next address Ad1, which corresponds to the address describing the operation of the internal hardware in the next step.

After the second step, the micro program start signal MSTART is "0", and at this time, the address selector 2 outputs the next address Ad1 as the address MA of the micro program ROM3.

Similarly, when the operations described in Ad2 and Ad3 are executed, the execution of the instruction A ends.

Similarly, in the case of the instruction B, Ad4 becomes the entry address, and A specified as the next address is used.
Execution of one instruction is completed by sequentially executing the operations described in d5 and Ad6.

"1" is placed at the bit position of the entry status signal ENT corresponding to the entry address of each instruction.
"0" is described in the bit positions of the entry status signal ENT corresponding to the other addresses.

FIGS. 3A and 3B are timing charts of respective signals for explaining the operation of the block of FIG. Figure 3 (a)
As shown in, when the definition instruction is fetched into the instruction bus INST, the instruction decoder 1 decodes it and outputs a normal entry address ENTA.

First timing point t in instruction execution
At 1, the microprogram start signal MSTART is "1", and the entry address ENTA becomes the address MA of the microprogram ROM 3.

The microprogram ROM 3 outputs the next address NXTA, which corresponds to the address describing the operation of the internal hardware in the next step.

At time t2 after the second step, the micro program start signal MSTART is "0", and at this time, the address selector 2 sets the next address NXTA to the address MA of the micro program ROM3.
Output as.

When the definition command is fetched, the entry status signal E corresponding to the entry address ENTA
"1" is read from the ROM 3 as NT. The delay circuit 4 is a circuit for digitally delaying the period T of the micro program start signal MSTART until the output timing of the entry status signal ENT.

When the defining instruction is normally entered, both the entry status signal ENT and the output of the delay circuit 4 become "1", and the trap signal TRAP becomes "0" by the inverter 5 and the AND gate 6. That is, no trap signal is output during normal operation.

Next, as shown in FIG. 3B, when an undefined instruction is fetched into the instruction bus INST, the instruction decoder 1 decodes this and the entry address ENTA.
Is output, but this address is not a normal address originally expected as an entry address but an abnormal address.

Therefore, "0" is read as the entry status signal ENT corresponding to the abnormal entry address. At this time t2, the output of the delay circuit 4 is "1", and the trap signal TRAP becomes "1" by the inverter 5 and the AND gate 6. That is, a trap signal is output in the case of abnormal operation.

In response to the trap signal TRAP, the microcomputer operates the internal interrupt circuit or the external interrupt circuit to perform the processing corresponding to the trap.

As described above, the micro program ROM
By only adding 1 bit of the entry status signal ENT to 3, the trap function of the undefined instruction can be realized without using the dedicated undefined instruction decoder 1a used conventionally.

Since the microprogram ROM is composed of memory cells and normally has a width of several tens of bits per word, even if one bit is added to this as an entry status signal, it is a slight increase in hardware as a whole. Compared with the conventional method that uses the undefined instruction decoder,
The chip area of the LSI can be reduced.

FIG. 4 is a block diagram of an instruction analysis unit and a control unit according to the second embodiment of the present invention. The basic operation is similar to that of the first embodiment, but a trap address generation circuit 7 is added to FIG. 1, and a trap address signal output from the trap address generation circuit 7 corresponding to the address selector 2 is added. An input terminal of TRPA and a trap signal TRAP for selectively controlling the TRPA is added to form an address selector 2a.

FIG. 5 is a timing chart for explaining the operation of the block of FIG. 4, and the operation of the block of this embodiment will be described with reference to FIGS. 4 and 5. When an undefined instruction is fetched on the instruction bus INST, a trap signal TRAP
Is the same as in the first embodiment until it becomes "1".

In the present embodiment, at the time point t1, the trap signal T
When the RAP becomes "1", the address selector 2a sends the trap address signal TRPA to the microprogram ROM.
It is output as the address MA of 3.

As a result, the trap address signal TRP
The contents of the microprogram designated by A are forcibly read, and the trap processing starts at time t3.
In this case, since the processing is performed by the built-in microprogram, it is not necessary to activate the interrupt circuit, and higher-speed trap processing can be expected.

A microprogram basically describes the internal hardware operation relating to the execution of instructions. However, by utilizing the fact that a series of operations can be described by a program, when describing operations other than the execution of instructions There are also many.

For example, initialization of internal hardware by system reset may be described.

Further, various peripheral circuits (timer, serial,
In a microcomputer with a built-in interface, etc., processing by an interrupt signal from these peripheral circuits (a signal indicating the count value overflow of the timer, data reception completion of the serial interface, etc.), that is, processing caused by an interrupt of internal hardware, is performed. It may be described.

In such a special process as a hardware interrupt, a fixed value is assigned to the entry address of the microprogram ROM, and when the system reset or the interrupt process is activated, the dedicated address generating circuit generates the entry address. . The trap address generation circuit 7 of FIG. 4 of the second embodiment also corresponds to this.

FIG. 6 is a block diagram of an instruction analysis unit and a control unit according to the third embodiment of the present invention. The basic operation is similar to that of the first embodiment, but a hardware interrupt address generating circuit 8 is added to FIG.

Further, instead of the address selector 2 of FIG. 1, the interrupt entry address INTA output from the hardware interrupt address generation circuit 8 is additionally input and the address selector 2b is used.

Further, an interrupt processing designation signal INT is added, and the micro program start signal MSTAR is added.
T, interrupt processing designation signal INT, AND gate 11, 1
2 and inverters 13 and 14 perform logical processing,
MA supplied to the address of the microprogram ROM 3
An address select control circuit 10 for selecting and controlling is added.

The address selector 2b has an AND gate 1
If the output of 1 is "1", the interrupt entry address IN
TA, the entry address ENTA when the output of the AND gate 12 is "1", and the next address NXTA when the output of the inverter 13 is "1" are selected and output as the address MA of the microprogram ROM 3.

The output of the AND gate 12 is input to the AND gate 6 via the delay circuit 4. This is because the trap determination is made only when the entry address ENTA is selected as the address of the microprogram ROM 3. It means to be effective.

FIG. 7 is a schematic diagram of an example of information described in the microprogram ROM of FIG. 6, and the description of interrupt processing is added to that of FIG.

The case where the instruction A is executed will be described with reference to FIGS. 6 and 7 as an example. First, the instruction A is placed on the instruction bus INST.
When the instruction code is fetched, the instruction decoder 1 decodes it and sets it as Ad0 as the entry address ENTA.
Is output.

At this time, since the micro program start signal MSTART is "1" and the interrupt processing designation signal INT is "0", the output of the AND gate 11 is "0",
The output of the AND gate 12 becomes "1" and the output of the inverter 13 becomes "0", and the address selector 2b outputs the entry address Ad0 as the address MA of the microprogram ROM 3.

The micro program ROM 3 outputs the control signal group CNT of the first step and controls the internal hardware of the microcomputer. The microprogram ROM 3 further outputs Ad1 as the next address NA, which corresponds to the address describing the operation of the internal hardware in the next step.

After the second step, since the microprogram start signal MSTART is "0" and the interrupt processing designation signal INT is "0", the output of the AND gate 11 is "0" and the output of the AND gate 12 is "0". , And the output of the inverter 13 becomes "1", at which time the address selector 2b outputs the next address Ad1 as the address MA of the microprogram ROM 3. Similarly, when the operations described in Ad2 and Ad3 are executed,
Execution of instruction A ends.

Similarly, in the case of the instruction B, Ad4 becomes the entry address and A specified as the next address is used.
Execution of one instruction is completed by sequentially executing the operations described in d5 and Ad6.

"1" is set in the bit position of the entry status signal ENT corresponding to the entry address of the instructions A and B.
However, "0" is described in the bit positions of the entry status signal ENT corresponding to other addresses.

When the interrupt processing is activated, the output of the AND gate 11 is "1" and the output of the AND gate 12 is "1" because the micro program start signal MSTART is "1" and the interrupt processing designating signal INT is also "1". Is "0", and the output of the inverter 13 is "0".

At this time, the address selector 2b outputs Ad7 as the interrupt entry address INTA output from the hardware interrupt address generating circuit 8 and the address MA of the microprogram ROM 3.

Thereafter, as in the case of the instructions A and B, the operations described in Ad8 and Ad9 designated as the next address are sequentially executed to complete the execution of the interrupt processing. However, "0" is described in the bit position of the entry status signal ENT corresponding to the entry address Ad7 of the interrupt process.

The reason for describing "0" instead of "1" as the entry status signal ENT, unlike the case of the instructions A and B, is as follows.

That is, when an undefined instruction is fetched into the instruction bus INST during instruction execution, the entry address ENTA generated by the instruction decoder 1 may coincide with the interrupt entry address.

This address is not originally expected as an entry address when executing an instruction. Therefore, "0" must be read as the entry status signal ENT corresponding to this irregular entry address.

FIG. 8 is a timing chart of each signal for explaining the block operation of FIG. As shown in FIG. 8A, when a definition instruction is fetched into the instruction bus INST, the instruction decoder 1 decodes it and outputs a normal entry address ENTA, and the trap signal TRAP becomes "0". It is shown that the trap signal is not output for the operation, that is, the definition instruction, and is the same as that of FIG. 3A except that the interrupt processing designation signal INT is “0”. Next, as shown in FIG. 8B, when the interrupt processing is activated, both the microprogram start signal MSTART and the interrupt processing designation signal INT are "1".
Therefore, the interrupt entry address INTA becomes the address MA of the microprogram ROM 3.

As described with reference to FIG. 7, "0" is read as the entry status signal ENT corresponding to the interrupt entry address INTA, but since the interrupt processing designation signal INT is "1" at this time, the inverter 14 Output is "0", and the output of AND gate 12 is also "0"
As a result, the output of the delay circuit 4 also becomes "0", so that the trap signal TRAP which is the output of the AND gate 6 becomes "0" without depending on the output of the inverter 5.

Therefore, when the interrupt process is activated, the trap signal TRAP is not output although the entry status signal ENT is "0".

Although not shown, the instruction bus IN
When an undefined instruction is fetched into ST, the trap signal TRAP becomes "1" as in the first embodiment,
Detects abnormal operation during instruction execution.

As described above, the trap determination is invalid in the special processing such as the hardware interrupt, and the trap determination is valid only when the instruction is executed, that is, when the entry address ENTA is selected as the address of the microprogram ROM 3. A microcomputer can be realized.

[0078]

As described above, the microcomputer of the present invention is a microcomputer resulting from the input of an undefined instruction without using a dedicated undefined instruction decoder which generally requires a huge amount of hardware. You can prevent runaway.

Therefore, the chip area of the microcomputer LSI can be reduced and the cost can be reduced, so that there is an effect that an inexpensive microcomputer can be provided.

Further, conventionally, when designing a microcomputer having a different instruction system, it was necessary to redesign the undefined instruction decoder each time, but according to the present invention, a microcomputer having a different instruction system is required. There is an effect that it can respond flexibly.

[0081]

[Brief description of drawings]

FIG. 1 is a partial block diagram of a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of information described in the microprogram ROM of FIG.

3 is a timing diagram of each signal for explaining the operation of the block of FIG.

FIG. 4 is a partial block diagram of a second embodiment of the present invention.

FIG. 5 is a timing diagram of signals for explaining the operation of the block of FIG.

FIG. 6 is a block diagram of a part of the third embodiment of the present invention.

7 is a schematic diagram showing an example of information described in the microprogram ROM of FIG.

FIG. 8 is a timing diagram of signals for explaining the operation of the block of FIG.

FIG. 9 is a partial block diagram of an example of a conventional microcomputer.

[Explanation of symbols]

 1 Instruction Decoder 2, 2a, 2b Address Selector 3 Micro Program ROM 4 Delay Circuit 5, 13, 14 Inverter 6, 11, 12 AND Gate 7 Trap Address Generation Circuit 8 Hardware Interrupt Generation Circuit 9 Trap Signal Generation Circuit 10 Hardware Interrupt Address generation circuit ENT entry status signal ENTA entry address INST instruction bus INT interrupt processing instruction signal INTA interrupt entry address MA address MSTART micro program start signal NXTA next address TRAP trap signal TRPA trap address signal

Claims (3)

[Claims] 1. An entry decoder which inputs an instruction bus and outputs an entry address, and a microprogram ROM which inputs an address signal and outputs a next address, the entry being selectively controlled by a microprogram start signal. A microcomputer having an address selector for selecting an address or the next address and supplying it to the micro program ROM as an address, and a trap signal generating circuit for generating a trap signal when the instruction bus is an undefined instruction. A data bit for an entry status signal indicating a start address in instruction execution is added to the microprogram ROM, and the trap signal generation circuit inputs the instruction execution start designation signal and the entry status signal A microcomputer provided with a logic gate for determining normality of an output of an instruction decoder. 2. The microcomputer according to claim 1, further comprising a trap address generation circuit for outputting a trap address signal, and the address selector inputs the trap address signal and the trap signal. 3. A hardware interrupt address generation circuit which outputs an interrupt entry address, and an address selector control circuit which inputs the microprogram start signal and an interrupt processing instruction signal and logically processes them to generate the selection control signal. And the address selector is
Except the timing at which the entry address is supplied as the address of the microprogram ROM by the signal of the selection control by further inputting the interrupt entry address, it does not depend on the logical value of the entry status signal and the normalization of the entry address. 2. The microcomputer according to claim 1, wherein the determination of sex is invalidated.