JPH06124595A - Flash memory - Google Patents

Abstract

PURPOSE:To enable performing erasing in which erasing verification time is shortened, a time required to erase can be shortened, while a cell transistor overly erased does not occur. CONSTITUTION:Reference voltage Vref is assumed as 'the lowest limit threshold allowed to VCC-cell transistors 1100-1122'. And word lines WL0-WL2 and a source lines SL are made VCC, nMOS transistors 120-122 and 29 are made an ON state (gate voltage =VCC + Vth - n), erasing verification is performed by comparing a voltage value of a data bus 13 with a voltage value of the reference voltage Vref.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM (electrically erasable and program) capable of electrically erasing and writing.
mable read only memory (EEPROM), avalanche breakdown is used for writing,
The present invention relates to an EEPROM, which is a so-called flash memory, that erases using a tunnel current.

In a flash memory, when erasing,
The erase operation and the erase verify operation are repeated so that a cell transistor that is under-erased does not remain in the memory cell transistor, so-called cell transistor.

Here, the generation of over-erased cell transistors must be absolutely avoided. On the other hand, there is a demand for shortening the time required for erasing.

[0004]

2. Description of the Related Art Conventionally, as a flash memory, FIG.
It is known that a block diagram is shown in FIG.

In the figure, 1 is a chip body, 2 ₀ , 2 ₁ ... 2
_n is an address signal input terminal to which the address signals A ₀ , A ₁ ... A _n are input, 3 is an address signal input terminal 2 ₀ , 2 _1.
..Address signals A ₀ and A ₁ input via 2 _n
An address buffer that waveform-shapes A _n .

Further, 4 is address signals A ₀ , A ₁ ... A
_{In n} , a row decoder 5 for decoding a row address to select a word line is a cell array section in which cell transistors are arranged.

Further, 6 is an address signal A ₀ , A ₁ ... A
_{In n} , a column decoder that decodes a column address and outputs a bit line selection signal, and a column gate 7 that selects a bit line based on the bit line selection signal output from the column decoder 6.

Further, 8 is a sense amplifier for detecting the data stored in the selected cell transistor, 9 is an output buffer for outputting the data detected by the sense amplifier 8 to the outside, and 10 is a data output terminal. .

[0009] Figure 7 is cell array 5, a circuit diagram specifically showing part of the column gate 7 and the sense amplifier 8, the cell array 5, 11 _{00-11 22} cell transistors, WL ₀ to WL ₂ is a word line, BL _{0 to} B
L ₂ is a bit line.

In the column gate 7, Y _{0 to} Y ₂
Is a bit line selection signal output from the column decoder 6,
12 _{0 to} 12 ₂ are turned on by the bit line selection signals Y _{0 to} Y ₂ ,
It is an enhancement type nMOS transistor whose OFF is controlled. In addition, 13 is a data bus.

In the sense amplifier 8, 14 is a VCC power supply line for supplying a power supply voltage VCC, and 15 is a pMOS.
A load using the ON resistance of the transistor, 16 is an inverter, 17 is an enhancement type nMOS transistor, 18 is a load 15 and an nMOS transistor 17
It is a voltage comparison circuit that compares the voltage of the node 19 which is a connection point with and the reference voltage Vref, and outputs the comparison result as output data.

Here, the reference voltage Vref has a different voltage value at the time of reading and at the time of erase verify, and at the time of reading, when the power supply voltage VCC is applied to the selected word line, the voltage of the selected cell transistor is changed. It is a voltage at which data can be read.

On the other hand, at the time of erase verify, for example, the threshold value after erase required for the cell transistor which is the slowest to erase for the word lines WL _{0 to} WL ₂ ,
That is, due to variations in characteristics, the cell transistor 11 _00-
When the same voltage value as the upper limit threshold value allowed to 11 ₂₂ is applied and the cell transistors 11 _{00 to} 11 ₂₂ are read one by one, the cell transistors 11 _{00 to} 11
Voltage that can determine whether or not a current flows through ₂₂ ,
That is, in the case of this example, the voltage is the same as the power supply voltage VCC.

As a result, in this flash memory,
At the time of erase verify, the cell transistors 11 _{00 to} 11 ₂₂
When the cells are read one by one, the cell transistor 11
_{00-11 22} when a current does not flow, i.e., in the case of voltage = reference voltage Vref at the node 19, insufficient erasing, the node 19
When the voltage value of <the reference voltage Vref, it is determined that the erase is completed.

[0015] Here, FIG. 8 shows the relationship between the erase time and the cell transistor 11 _{00-11 22} threshold,
Solid line 20 is for the slowest erasing cell transistor, and solid line 21 is for the fastest erasing cell transistor.

In this flash memory, as shown in FIG. 8, the erasing is performed after the threshold required for the cell transistor having the slowest erasing, ie, the upper limit threshold which is allowed. Is set as a reference potential, and erasing is performed so as to end when the threshold value of the cell transistor which is the slowest reaches the reference potential. Specifically, it is performed according to the procedure shown in FIG.

That is, first, the all-cell transistor 11 ₀₀
Writing to 11 ₂₂ is performed (step A1).
Then, the erasing operation is started (step A2) and, after a wait state (erasing operation maintaining state) for a predetermined time, the erasing operation is stopped (steps A3 and A4).

After that, the cell transistors 11 _{00 to} 11
₂₂ are read one by one, and the node 19 of the sense amplifier 8 is read.
The erase verify is performed by comparing the voltage of 1 to the reference voltage Vref (step A5).

The cell transistors 11 _{00 to} 11
The voltage value of the node 19 <reference voltage Vre for all ₂₂
Whether or not f, that is, all-cell transistor 1
About 1 _{00-11 22,} whether the erase has been completed is determined (step A6).

Here, all cell transistors 11 ₀₀ to 1
If no erasure has been performed on 1 ₂₂ (step A)
If NO in step 6), the process returns to step A2 and all cells
For transistor 11 _{00-11 22,} in the case (YES in step A6) which erasing has been completed, the erase is terminated.

[0021]

In THE INVENTION Problems to be Solved] such conventional flash memory, its structure, the cell transistors 11 ₀₀ to 11 ₂₂ to read state one by one, only one each cell transistors to perform the erase verify I can't.

In other words, the erase verify can be performed only for each cell transistor per sense amplifier. This lengthens the erase verify time,
This has been a cause of lengthening the time required for erasing.

Further, in this conventional flash memory, by confirming that the threshold value of the cell transistor which is the slowest to erase due to its configuration has reached the allowable upper limit threshold value, All cell transistor 1
Per ₀₀ to 11 _22, so that it is determined that the erasing has been completed.

For this reason, even when the cell transistor that erases quickly is over-erased, this cannot be avoided, and the existence of the over-erased cell transistor may be allowed. was there.

In view of the above point, the present invention can shorten the erase verify time, shorten the time required for erasing, and perform erasing without generating over-erased cell transistors. An object is to provide a flash memory that can be used.

[0026]

In the present invention, the flash memory according to the first invention serves as a control gate of a plurality of cell transistors each having a source connected to a common source line during erase verify. Applying the same or different positive voltage of a predetermined voltage value or more to all or part of the plurality of word lines and the source line, and corresponding to the plurality of bit lines to which the drains of the plurality of cell transistors are connected. When the data bus provided as a whole is connected to all or a part of the plurality of bit lines, the voltage of the data bus is compared with a predetermined reference voltage, and all or a plurality of the cell transistors are connected. A portion of the drain voltage is the positive voltage applied to the word line minus the lower threshold allowed for the cell transistors. Configured with a voltage determination circuit determines whether or not reached.

In the present invention, the flash according to the second invention
In the memory, during erase verification, all or part of a plurality of word lines forming the control gates of a plurality of cell transistors whose sources are connected to a common source line and the drains of the plurality of cell transistors are connected. A positive voltage equal to or higher than a predetermined voltage value is applied to the data buses provided corresponding to the plurality of bit lines, and the data bus and all or a part of the plurality of bit lines are applied. The source line voltage is compared with a predetermined reference voltage to connect the plurality of cells.
Determine whether the source voltage of all or part of the transistor has reached a value obtained by subtracting the lower limit threshold value allowed for the plurality of cell transistors from the positive voltage applied to the word line. It is configured to include a voltage determination circuit that operates.

[0028]

According to the first aspect of the present invention, at the time of erase verify, for example, the same or different positive voltage of a predetermined voltage value or more is applied to all of the plurality of word lines and the source line, and the data bus and the plurality of bit lines are applied. , The drain voltage of multiple cell transistors is "the positive voltage applied to the word line-the cell with the fastest erase.
The threshold value of the transistor (threshold value of the cell transistor that minimizes the threshold value) ".

Here, in the first aspect of the present invention, the voltage determination circuit causes the drain voltages of the plurality of cell transistors to reach “a positive voltage applied to the word line−the allowable lower limit threshold value”. It is determined whether or not
When "the threshold value of the cell transistor in which erasing is quickest = the lower limit threshold value that is allowed", the drain voltage of the plurality of cell transistors becomes "the positive voltage applied to the word line- It is the lower limit threshold that is allowed.

In other words, when the drain voltages of the plurality of cell transistors reach “the positive voltage applied to the word line−the allowable lower limit threshold value”, the cell transistor with the fastest erasure is erased. It can be determined that the threshold has reached the lower allowed threshold, and in this case the threshold of the cell transistor with the slowest erase is the upper allowed threshold. You can judge that you have reached.

That is, in the first aspect of the invention, the same or different positive voltage of a predetermined voltage value or more is applied to all of the plurality of word lines and the source lines, and the data bus and all of the plurality of bit lines are applied. Connect and use a voltage determination circuit to determine whether the drain voltage of multiple cell transistors has reached the positive voltage applied to the word line minus the allowed lower threshold. Thus, the erase verify can be simultaneously performed on all of the plurality of cell transistors.

As described above, according to the first aspect of the present invention, the erase verify can be simultaneously performed with respect to a plurality of cell transistors, and it is not necessary to read all the cell transistors one by one. It can be shortened.

According to the first aspect of the present invention, the erase verify is performed by detecting the case where the threshold value of the cell transistor in which the erasing is fastest becomes the lower limit threshold value. Therefore, the over-erased cell
It is possible to perform erasing without causing a transistor.

When the erase verify by the conventional method is performed after the threshold value of the cell transistor having the fastest erase reaches the lower limit threshold value, the cell having the slowest erase is used. The existence of a cell transistor having a threshold value higher than the threshold value after erasing allowed for the transistor can be confirmed, and a device defect can be found.

Even in such a case, since the erase verify by the conventional method needs to be performed only once for each cell transistor, the time required for the erase verify is shorter than that in the conventional case. can do.

According to the first aspect of the present invention, the voltage of the data bus is compared with a predetermined reference voltage, and the drain voltages of all or some of the plurality of cell transistors are applied to the word line. Since it has a voltage judgment circuit that judges whether or not it has reached a value obtained by subtracting the lower limit threshold value allowed from the positive voltage, it is possible to use one cell transistor or one cell transistor with a common bit line. It is also possible to carry out erase verify for each cell transistor.

In this case, at the time of erase verify, the same or different positive voltage of a predetermined voltage value or more is applied to a part of the plurality of word lines and the source line, and the data bus and a part of the plurality of bit lines are applied. It suffices to connect and.

Further, in the second invention, at the time of erase verify, for example, the same or different positive voltage of a predetermined voltage value or more is applied to all of the plurality of word lines and the data bus, and the data bus and the plurality of data lines are connected. When all of the bit lines are connected, the source voltage of the plurality of cell transistors is “the positive voltage applied to the word line−the threshold value of the cell transistor with the fastest erase”.

Here, in the second aspect of the present invention, the source voltage of the plurality of cell transistors reaches “the positive voltage applied to the word line−the allowable lower limit threshold value” by the voltage determination circuit. It is determined whether or not
When "the threshold value of the cell transistor in which erasing is quickest = the lower limit threshold value that is allowed", the drain voltage of the plurality of cell transistors becomes "the positive voltage applied to the word line- It is the lower limit threshold that is allowed.

In other words, when the source voltages of the plurality of cell transistors reach “the positive voltage applied to the word line−the allowable lower threshold value”, the cell transistor of the fastest erasing is performed. It can be determined that the threshold has reached the lower threshold allowed, and in this case the threshold for the slowest erased cell transistor is
It can be determined that the upper limit threshold value that is allowed has been reached.

That is, according to the second aspect of the present invention, at the time of erase verify, the same or different positive voltage of a predetermined voltage value or more is applied to all of the plurality of word lines and the data bus, and the data bus and the plurality of bits are applied. Whether all the lines are connected and the voltage decision circuit has determined that the drain voltages of the cell transistors have reached the positive voltage applied to the word line minus the lower limit threshold value allowed. By determining whether or not, erase verification can be simultaneously performed on a plurality of cell transistors.

As described above, according to the second aspect of the invention, as in the case of the first aspect of the invention, the erase verify can be simultaneously performed for a plurality of cell transistors, and one for each cell transistor. Since it is not necessary to read, the erase verify time can be shortened.

According to the second aspect of the invention, the erase verify can be performed by detecting the case where the threshold value of the cell transistor in which erasing is fastest becomes the lower limit threshold value. Therefore, erasing can be performed without the occurrence of over-erased cell transistors.

When the erase verify according to the conventional method is performed after the threshold value of the cell transistor having the fastest erase reaches the allowable lower threshold value, the cell having the slowest erase speed is erased. The existence of a cell transistor having a threshold value higher than the threshold value after erasing allowed for the transistor can be confirmed, and a device defect can be found.

Even in such a case, since the erase verify by the conventional method needs to be performed only once for each cell transistor, the time required for the erase verify is shorter than that in the conventional case. can do.

According to the second aspect of the invention, the voltage of the source line is compared with a predetermined reference voltage, and the source voltage of all or some of the plurality of cell transistors is applied to the word line. Since it has a voltage judgment circuit that judges whether or not it has reached a value obtained by subtracting the lower limit threshold value allowed from the positive voltage, it is possible to use one cell transistor or one cell transistor with a common bit line. It is also possible to carry out erase verify for each cell transistor.

In this case, at the time of erase verify, the same or different positive voltage of a predetermined voltage value or more is applied to part of the plurality of word lines and the data bus, and at the same time, part of the data bus and the plurality of bit lines are applied. It suffices to connect and.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
An example and a second example will be described. Note that FIG.
2 and 4, parts corresponding to those in FIGS. 7 and 8 are designated by the same reference numerals, and duplicate description thereof will be omitted.

First Embodiment FIG. 1 to FIG. 3 FIG. 1 is a circuit diagram showing an essential part of the first embodiment of the present invention.
In the figure, SL is a source line to which the sources of the cell transistors 11 ₀₀ to 11 ₂₂ are connected, in the first embodiment, erase verify, the power supply voltage VCC to the source line SL
A voltage application circuit 23 for applying the voltage is provided.

During erase verify, the data bus 13
Voltage of "VCC-cell transistor 11 _{00 to} 11 ₂₂
A voltage determination circuit 24 is provided to determine whether or not it is larger than a “lower limit threshold value allowed by the above”. Others are the same as those of the conventional flash memory shown in FIG.

Here, in the voltage judgment circuit 24, 25
Is an operational amplifier forming a comparator, 26 and 27 are depletion-type nMOS transistors forming a load, 28 is a reference voltage generating circuit for generating a reference voltage Vref, and the reference voltage Vref is "VCC-cell transistor 11 _00".
The lower limit threshold value permitted up to 11 ₂₂ ”.

Reference numeral 29 is an enhancement type nMOS transistor having the same size as the nMOS transistors 12 _{0 to} 12 ₂ of the column gate 7. The gate of the nMOS transistor 29 has a VCC level during erase verify.
+ Vth-n (threshold voltage of nMOS transistor) is applied. Further, reference numeral 30 is a judgment output terminal to which a judgment output is outputted.

In this first embodiment, erasing is performed by
As shown in, the threshold value after erasure required for the cell transistor with the fastest erasure, that is, the lower limit threshold value allowed is set as the reference potential, and the threshold of the cell transistor with the fastest erasure is set. After confirming whether or not the threshold value has reached the reference potential, erase verification is performed by a conventional method. Specifically, the procedure shown in FIG. 3 is performed.

That is, first, all cell transistors 11 ₀₀
Writing to 11 ₂₂ is performed (step B1).
Then, after the erase operation is started, a wait state (erase operation maintaining state) is set for a predetermined time (steps B2, B).
3).

Here, the erase operation is performed by the source line SL = VC.
C, word lines WL _{0 to} WL ₂ = negative voltage, bit lines BL ₀ to
BL ₂ = open (nMOS transistor 12 ₀ ~12 ₂ = O
FF) or by setting the source line SL = high voltage, for example, 12 [V], word lines WL _{0 to} WL ₂ = 0 [V], and bit lines BL _{0 to} BL ₂ = open. .

Next, erase verify is performed (step B4). This word line WL ₀ ~WL ₂ = VCC, the source line SL = VCC, nMOS transistor 12 _0-1
2 ₂ , 29 = ON (gate voltage = VCC + Vth-n) and the voltage value of the data bus 13 is compared with the voltage value of the reference voltage Vref.

In this case, the voltage of the data bus 13 and the cell
Match the drain voltage of the transistor 11 _{00-11 22,} the voltage of the data bus 13, "among the VCC-nMOS transistor 11 _{00-11 22,} the fastest cell erased,
The threshold value of the transistor (threshold value of the cell transistor that minimizes the threshold value) ".

Here, it is judged whether or not the judgment output obtained at the judgment output terminal 30 is "H" (step B5).
If the determination output is not "H" (NO at step B5), that is, when the voltage> the reference voltage Vref of the data bus 13, of the cell transistor 11 _{00-11 22,}
The threshold value of the cell transistor that erases the fastest will be higher than the lower limit threshold value allowed.

In this case, due to variations in characteristics, a threshold value larger than the threshold value after erasure (the allowable upper limit threshold value) required for the cell transistor with the latest erasure is shown. Since the cell transistor may exist, the process returns to step B2, and the erasing is performed again.

On the other hand, when the judgment output obtained at the judgment output terminal 30 is “L” (YES in step B5), that is, when the voltage of the data bus 13 ≦ the reference voltage Vref, the cell Of the transistors 11 _{00 to} 11 ₂₂
This means that the threshold value of the cell transistor which is erased fastest has reached the lower limit threshold value which is allowed.

In this case, it can be considered that the threshold value of the cell transistor which is the slowest to erase reaches the upper limit threshold value which is allowed, but it is allowed because of the defect. It cannot be ruled out that there may be cell transistors that exhibit a threshold greater than the upper threshold.

Therefore, in the first embodiment, step B
Even if YES in 5 determines erasing by conventional methods verification, i.e., the output of the sense amplifier 8 to the cell transistors 11 ₀₀ to 11 ₂₂ to read state one by one (step B6), the sense amplifier It is determined whether or not there is a cell transistor having the output of 8 = “H”, that is, a cell transistor having a threshold value larger than the allowable upper limit threshold value (step B7).

If there is no cell transistor in which the output of the sense amplifier 8 is "H", there is no cell transistor (step B).
In the case of NO) at 7, the device is not a defective device, for all the cell transistors 11 ₀₀ to 11 _22, erasing the erasing is completed is terminated.

On the other hand, the output of the sense amplifier 8 =
If there is a cell transistor that becomes "H" (YES in step B7), the device is processed as a defective device (step B8).

As described above, in the first embodiment, the threshold value after erasure required for the cell transistor having the fastest erasure, that is, the allowable lower limit threshold value is used as a reference because of its configuration. It is regarded as the electric potential, and it is confirmed whether the threshold of the cell transistor that erases fastest reaches the reference potential,
At the same time, it is possible to confirm that there is no cell transistor for which the output of the sense amplifier 8 = “H”, and to finish the erasing.

Whether or not the threshold value of the cell transistor which is erased fastest reaches the reference potential depends on the word line W.
L _{0 to} WL ₂ = VCC, source line SL = VCC, nMOS
Gates of the transistors 12 _{0 to} 12 ₂ and 29 = VCC + V
can be performed by a th-n, it is not necessary to the cell transistors 11 ₀₀ to 11 ₂₂ to read state one by one.

[0067] It should be noted, nMOS transistor 12 _0-1
When a voltage of VCC + Vth-n or higher is applied to the gates of 2 ₂ and 29, these nMOS transistors 12 ₀ to 1
The voltage drop of 2 ₂ and 29 can be ignored.

Further, it is determined whether or not there is a cell transistor whose output of the sense amplifier 8 is "H" by performing erase verify by the conventional method on all cell transistors 1.
About 1 _{00-11 22,} the maximum, it is sufficient to performed once.

Further, according to the first embodiment, the erase verify can be performed by detecting the case where the cell transistor which is erased fastest reaches the allowable lower limit threshold value. No over-erased cell transistor is generated.

Therefore, according to the first embodiment, the erase verify time can be shortened, the time required for the erase can be shortened, and the erase can be performed without generating the over-erased cell transistor. be able to.

Further, in the first embodiment, each cell transistor having a common bit line, or 1
Erase verification can also be performed for each cell transistor.

Here, in the case where the erase verify is performed for each cell transistor having a common bit line, for example, the erase verify is simultaneously performed on the cell transistors 11 ₀₀ , 11 ₁₀ , 11 ₂₀ connected to the bit line BL _0. To perform the word line WL _{0 to} WL ₂ = VCC,
The source line SL = VCC, nMOS transistor 12 _0,
29 = ON (gate voltage = VCC + Vth-n), nMOS
The transistors 12 ₁ and 12 ₂ = OFF (gate voltage = ground voltage VSS) may be set.

[0073] Also, in the case of performing the erase verify for each one of the cell transistors, for example, the cell transistors 11 _00, in the case of performing the erase verify, the word line WL ₀ = VCC, the word lines WL _1, WL ₂ =
VSS, the source line SL = VCC, nMOS transistor 12 _0, 29 = ON (gate voltage = VCC + Vth-n),
The nMOS transistors 12 ₁ and 12 ₂ may be turned off (gate voltage = VSS).

In the first embodiment, the nMO
When the S transistors 12 _{0 to} 12 ₂ and 29 are turned on, VCC + Vth-n is applied to their gates, but VCC may be applied.

Second Embodiment ... FIG. 4 and FIG. 5 FIG. 4 is a circuit diagram showing an essential part of a second embodiment of the present invention.
In the second embodiment, a voltage application circuit 31 for applying the power supply voltage VCC to the data bus 13 at the time of erase verify is provided.

Reference numeral 32 is a VCC power supply line, and 33 is an nMO.
This nMOS transistor 33 is an S transistor.
Is turned on by applying VCC + Vth-n to the gate at the time of erase verify, and at the time other than erase verify,
VSS is applied to the gate and turned off.

[0077] Also, during erase verify, the voltage determines whether the voltage of the source line SL is greater than "VCC- cell transistors 11 ₀₀ to 11 ₂₂ to allowed to have lower threshold" determination circuit 34 Is provided. Others are the same as those of the conventional flash memory shown in FIG.

Here, in the voltage determination circuit 34, 35
Is a reference voltage generating circuit for generating a reference voltage Vref,
The reference voltage Vref is “VCC-cell transistor 11
_{00-11 22} there is a allowed to have lower threshold ".

Further, 36 and 37 are enhancement type nMOS transistors of the same size which form gates, and 3
Reference numerals 8 and 39 are depletion-type nMOS transistors of the same size that form a load, 40 is an operational amplifier, and 41 is a determination output terminal for outputting a determination output.

The nMOS transistors 36 and 37
Is turned on by applying VCC + Vth-n to the gate at the time of erase verify, and at the time other than erase verify,
VSS is applied to the gate to turn it off.

In this second embodiment, as in the case of the first embodiment, erasing is performed after the erasure required for the cell transistor having the fastest erasing, as shown in FIG. The threshold value, that is, the lower limit threshold value allowed is used as the reference potential, and after confirming whether or not the threshold value of the cell transistor with the fastest erasing reaches the reference potential, the erasing by the conventional method is performed. It is performed by performing verification. Specifically, the procedure is shown in FIG.

That is, first, all cell transistors 11 ₀₀
Writing to 11 ₂₂ is performed (step C1).
Then, after the erase operation is started, a wait state (erase operation maintaining state) is set for a predetermined time (steps C2, C).
3).

In the erase operation, the source line SL = VC
C, word lines WL _{0 to} WL ₂ = negative voltage, bit lines BL ₀ to
BL ₂ = open (nMOS transistor 12 ₀ ~12 ₂ = O
FF) or by setting the source line SL = high voltage, for example, 12 [V], word lines WL _{0 to} WL ₂ = 0 [V], and bit lines BL _{0 to} BL ₂ = open. .

Next, erase verify is performed (step C4). This is, nMOS transistor 12 _0-1
2 ₂ , 33, 36, 37 = ON (gate voltage = VCC +
Vth-n), the voltage of the bit lines BL _{0 to} BL ₂ is VCC, and the word lines WL _{0 to} WL ₂ = VCC, and the voltage value of the source line SL and the voltage value of the reference voltage Vref are compared. Done by.

In this case, the cell transistors 11 ₀₀ to 1
Source voltage of 1 to _22, that is, the voltage of the source line SL "VC
Of C- cell transistors 11 ₀₀ to 11 _22, the erased fastest cell transistor threshold (threshold minimum cell transistor threshold) ".

Here, it is judged whether or not the judgment output obtained at the judgment output terminal 41 is "H" (step C5).
If the determination output is not "H" (NO in step C5), that is, when the voltage> the reference voltage Vref of the source line SL of the cell transistor 11 _{00-11 22,} cell erasure fastest This means that the threshold value of the transistor is higher than the allowable lower limit threshold value.

In this case, due to variations in characteristics, a threshold value larger than the threshold value after erasure (the allowable upper threshold value) required for the cell transistor with the slowest erasure is shown. Since the cell transistor may be present, the process returns to step C2 and the erasing is performed again.

On the other hand, if the judgment output obtained at the judgment output terminal 41 is "L" (YES in step C5), that is, if the voltage of the source line SL ≤ the reference voltage Vref, the cell among the transistors 11 ₀₀ to 11 _22, so that the threshold is met the lower limit threshold of the fastest cell transistors erased is permitted.

In this case, it can be considered that the threshold value of the cell transistor which is the slowest to erase reaches the upper limit threshold value which is allowed, but it is allowed because of the defect. It cannot be ruled out that there may be cell transistors that exhibit a threshold greater than the upper threshold.

Therefore, in the second embodiment, step C
Even if YES in 5 determines erasing by conventional methods verification, i.e., the output of the sense amplifier 8 to the cell transistors 11 ₀₀ to 11 ₂₂ to read state one by one (step C6), the sense amplifier It is determined whether or not there is a cell transistor having the output of 8 = “H”, that is, a cell transistor having a threshold value larger than the allowable upper limit threshold value (step C7).

If there is no cell transistor for which the output of the sense amplifier 8 is "H", then (step C)
In the case of NO) at 7, the device is not a defective device, for all the cell transistors 11 ₀₀ to 11 _22, erasing the erasing is completed is terminated.

On the other hand, the output of the sense amplifier 8 =
If there is a cell transistor that becomes "H" (YES in step C7), the device is treated as a defective device (step C8).

As described above, in the second embodiment, the threshold value after erasure required for the cell transistor having the fastest erasure, that is, the allowable lower limit threshold value is used as a reference because of its configuration. It is regarded as the electric potential, and it is confirmed whether the threshold of the cell transistor that erases fastest reaches the reference potential,
At the same time, it is possible to confirm that there is no cell transistor for which the output of the sense amplifier 8 = “H”, and to finish the erase.

Here, the cell transistor with the fastest erasure
The word line W determines whether the threshold value of the data has reached the reference potential.
L₀~ WL₂= VCC, bit line BL₀~ BL₂= VCC,
nMOS transistor 12₀~ 12₂, 33, 36, 37
= ON (gate voltage = VCC + Vth-n)
Cell transistor 11₀₀~ 11 _{twenty two}
It is not necessary to put each one in a read state.

Further, it is determined whether or not there is a cell transistor whose output of the sense amplifier 8 becomes "H" by performing erase verify by the conventional method on all cell transistors 1.
About 1 _{00-11 22,} the maximum, it is sufficient to performed once.

Further, according to the second embodiment, the erase verify can be carried out by detecting the case where the cell transistor which is erased fastest reaches the allowable lower limit threshold value. No over-erased cell transistor is generated.

Therefore, according to the second embodiment, the erase verify time can be shortened, the time required for the erase can be shortened, and the erase can be performed without generating the over-erased cell transistor. be able to.

In the second embodiment, each cell transistor having a common bit line, or 1
Erase verification can also be performed for each cell transistor.

Here, in the case where the erase verify is performed for each cell transistor having a common bit line, for example, the erase verify is simultaneously performed on the cell transistors 11 ₀₀ , 11 ₁₀ , 11 ₂₀ connected to the bit line BL _0. To perform the word line WL _{0 to} WL ₂ = VCC,
nMOS transistor 12 _0, 33,36,37 = ON
(Gate voltage = VCC + Vth-n), nMOS transistors 12 ₁ and 12 ₂ = OFF (gate voltage = VSS).

[0100] Also, in the case of performing the erase verify for each one of the cell transistors, for example, the cell transistors 11 _00, in the case of performing the erase verify, the word line WL ₀ = VCC, the word lines WL _1, WL ₂ =
VSS, nMOS transistor 12 _0, 33,36,3
7 = ON (gate voltage = VCC + Vth-n), nMOS transistors 12 ₁ and 12 ₂ = OFF (gate voltage = VS
S).

In the second embodiment, the nMO
S transistor 12 _{0-12 2,} when the ON of 36, 37, but so as to apply the VCC + Vth-n to the gate, may be applied to VCC.

[0102]

As described above, according to the present invention (first and second inventions), erase verification can be simultaneously performed on a plurality of cell transistors, and all the cell transistors are read one by one. Since it is not necessary, the erase verify time can be shortened, the time required for erase can be shortened, and the threshold value of the cell transistor with the fastest erase has reached the lower limit threshold value. By detecting the case, the erase verify can be performed, so that the erase can be performed without generating the over-erased cell transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an erase time and a threshold value of a cell transistor.

FIG. 3 is a flowchart showing an erasing procedure performed in the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 5 is a flowchart showing an erasing procedure performed in the second embodiment of the present invention.

FIG. 6 is a block diagram showing a main part of an example of a conventional flash memory.

FIG. 7 is a diagram specifically showing a cell array portion, a column gate, and a sense amplifier portion forming the conventional flash memory shown in FIG.

FIG. 8 is a diagram showing a relationship between an erase time and a threshold value of a cell transistor.

9 is a flowchart showing an erasing procedure performed in the conventional flash memory shown in FIG.

[Explanation of symbols]

5 cell array 7 column gate 8 sense amplifiers 11 _{00-11 22} cell transistors 12 ₀ to 12 ₂ enhancement type nMOS transistor 13 data bus 23 voltage application circuit 24 voltage determining circuit 25 operational amplifiers 26, 27 depletion type nMOS transistor 28 reference Voltage generation circuit 29 Enhancement type nMOS transistor

Claims (2)

[Claims] 1. At the time of erase verify, a predetermined voltage is applied to all or a part of a plurality of word lines forming a control gate of a plurality of cell transistors each having a source connected to a common source line and the source line. The same or different positive voltage equal to or more than the value is applied, and all or one of the plurality of bit lines and the data bus provided corresponding to the plurality of bit lines to which the drains of the plurality of cell transistors are connected. The voltage of the data bus is compared with a predetermined reference voltage so that the drain voltage of all or some of the plurality of cell transistors is changed from the positive voltage applied to the word line. The plurality of cells
A flash memory comprising a voltage judgment circuit for judging whether or not a value obtained by subtracting a lower limit threshold value allowed for a transistor has been reached. 2. Erase verify, all or part of a plurality of word lines forming control gates of a plurality of cell transistors whose sources are connected to a common source line, and drains of the plurality of cell transistors. A positive voltage equal to or higher than a predetermined voltage value is applied to a data bus provided corresponding to a plurality of bit lines connected to each other, and all or one of the data bus and the plurality of bit lines is applied. The voltage of the source line is compared with a predetermined reference voltage, the source voltage of all or some of the plurality of cell transistors is changed from the positive voltage applied to the word line. It is configured to include a voltage determination circuit that determines whether or not a value obtained by subtracting the lower limit threshold value allowed for the plurality of cell transistors has been reached. Flash memory and features.